Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26235

1

T1

39

T2

3

T3

130

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22398

1

T1

16

T2

1

T3

130

auto[ADC_CTRL_FILTER_COND_OUT]

3837

1

T1

23

T2

2

T6

18

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19953

1

T2

2

T3

130

T6

18

auto[1]

6282

1

T1

39

T2

1

T5

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21981

1

T1

25

T2

3

T3

130

auto[1]

4254

1

T1

14

T5

10

T6

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	26	1			T258	10		T273	2		T287	7
values[0]	45	1			T60	16		T149	6		T187	1
values[1]	701	1			T12	11		T48	1		T49	8
values[2]	505	1			T2	1		T156	9		T51	1
values[3]	821	1			T1	23		T6	18		T210	1
values[4]	553	1			T12	15		T48	1		T135	24
values[5]	872	1			T2	1		T147	12		T209	12
values[6]	964	1			T12	16		T56	12		T59	11
values[7]	700	1			T147	13		T140	28		T99	10
values[8]	683	1			T2	1		T56	13		T64	25
values[9]	3485	1			T1	16		T5	11		T8	1
minimum	16880	1			T3	130		T7	150		T48	125

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	795	1			T12	11		T48	1		T49	8
values[1]	580	1			T2	1		T156	9		T141	18
values[2]	701	1			T1	23		T6	18		T210	1
values[3]	773	1			T12	15		T48	1		T135	24
values[4]	774	1			T2	1		T56	12		T209	20
values[5]	1023	1			T59	11		T139	13		T135	41
values[6]	2894	1			T5	11		T9	29		T10	32
values[7]	739	1			T2	1		T56	13		T64	18
values[8]	787	1			T71	11		T134	16		T147	3
values[9]	255	1			T1	16		T8	1		T53	8
minimum	16914	1			T3	130		T7	150		T48	125

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

4166

1

T1

23

T6

8

T12

33

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T48	1		T49	2		T99	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	11		T134	9		T51	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T2	1		T141	12		T150	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T156	1		T142	10		T154	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T208	1		T51	2		T96	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	12		T6	9		T210	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T12	13		T48	1		T135	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T144	7		T155	10		T226	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T209	20		T158	5		T14	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T2	1		T56	12		T52	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T139	1		T135	22		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T59	11		T152	10		T51	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1537	1			T5	1		T9	3		T10	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T49	4		T64	7		T72	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T64	18		T139	1		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T2	1		T56	13		T140	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T147	1		T152	9		T51	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T71	3		T134	8		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T1	13		T157	1		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T8	1		T53	4		T29	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16725	1			T3	130		T7	150		T48	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T60	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T49	6		T99	8		T215	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T134	8		T149	14		T157	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T141	6		T254	6		T160	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T156	8		T142	13		T154	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T51	8		T43	8		T242	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	11		T6	9		T221	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T12	2		T135	12		T147	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T144	12		T155	9		T226	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T158	4		T31	11		T107	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T215	15		T155	8		T43	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T139	12		T135	19		T147	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T51	3		T72	9		T191	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1017	1			T5	10		T9	26		T10	29
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T49	2		T72	11		T40	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T139	14		T141	13		T142	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T140	13		T215	14		T158	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T147	2		T51	12		T141	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T71	8		T134	8		T154	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T1	3		T157	15		T217	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T53	4		T29	6		T159	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T48	1		T60	1		T49	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T60	8		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T258	10		T273	1		T287	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T288	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T289	1		T290	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T60	8		T149	1		T187	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T48	1		T49	2		T99	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	11		T134	9		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T2	1		T157	1		T150	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T156	1		T51	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T208	1		T51	2		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	12		T6	9		T210	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T12	13		T48	1		T135	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T144	7		T221	1		T155	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T147	1		T209	12		T50	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T2	1		T52	3		T215	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T12	12		T139	1		T135	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T56	12		T59	11		T49	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T147	1		T99	1		T141	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T140	15		T72	23		T187	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T64	18		T142	15		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T2	1		T56	13		T64	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1677	1			T1	13		T5	1		T9	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T8	1		T71	3		T134	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16717	1			T3	130		T7	150		T48	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T273	1		T287	4		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T288	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T60	8		T149	5		T268	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T49	6		T99	8		T215	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T134	8		T247	2		T169	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T157	13		T167	1		T291	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T156	8		T149	9		T157	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T51	8		T141	6		T43	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T1	11		T6	9		T154	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T12	2		T135	12		T140	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T144	12		T221	12		T155	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T147	11		T50	7		T158	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T215	15		T43	6		T29	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	4		T139	12		T135	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T49	2		T51	3		T191	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T147	12		T99	9		T141	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T140	13		T72	19		T40	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T142	14		T27	12		T247	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T72	1		T215	14		T165	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1184	1			T1	3		T5	10		T9	26
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T71	8		T134	8		T53	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	1		T60	1		T49	3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T48	1		T49	8		T99	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	1		T134	9		T51	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T2	1		T141	7		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T156	9		T142	14		T154	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T208	1		T51	10		T96	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T1	12		T6	10		T210	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T12	3		T48	1		T135	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T144	13		T155	10		T226	19
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T209	2		T158	5		T14	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T2	1		T56	1		T52	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T139	13		T135	21		T147	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T59	1		T152	1		T51	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T5	11		T9	29		T10	32
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T49	5		T64	1		T72	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T64	1		T139	15		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T2	1		T56	1		T140	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T147	3		T152	1		T51	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T71	9		T134	9		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T1	4		T157	16		T217	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T8	1		T53	7		T29	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16891	1			T3	130		T7	150		T48	125
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T60	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T215	8		T34	11		T233	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T12	10		T134	8		T212	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T141	11		T150	8		T212	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T142	9		T154	6		T34	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T43	4		T24	7		T242	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T1	11		T6	8		T245	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T12	12		T135	11		T140	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T144	6		T155	9		T226	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T209	18		T158	4		T107	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T56	11		T52	1		T215	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T135	20		T150	9		T211	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T59	10		T152	9		T51	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1202	1			T12	11		T63	29		T223	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T49	1		T64	6		T72	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T64	17		T141	9		T142	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T56	12		T140	14		T215	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T152	8		T51	9		T141	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T71	2		T134	7		T154	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T1	12		T292	9		T166	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T53	1		T29	3		T293	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T237	7		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T60	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T258	1		T273	2		T287	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T288	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T289	1		T290	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T60	9		T149	6		T187	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T48	1		T49	8		T99	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	1		T134	9		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T2	1		T157	14		T150	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T156	9		T51	1		T149	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T208	1		T51	10		T96	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	12		T6	10		T210	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	3		T48	1		T135	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T144	13		T221	13		T155	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T147	12		T209	1		T50	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T2	1		T52	2		T215	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T12	5		T139	13		T135	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T56	1		T59	1		T49	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T147	13		T99	10		T141	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T140	14		T72	21		T187	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T64	1		T142	15		T27	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T2	1		T56	1		T64	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1550	1			T1	4		T5	11		T9	29
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T8	1		T71	9		T134	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16880	1			T3	130		T7	150		T48	125
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T258	9		T287	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T60	7		T268	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T215	8		T34	11		T254	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T12	10		T134	8		T212	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T150	8		T212	6		T167	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T142	9		T233	12		T224	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T141	11		T43	4		T24	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	11		T6	8		T154	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T12	12		T135	11		T140	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T144	6		T155	9		T225	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T209	11		T50	3		T158	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T52	1		T215	11		T43	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T12	11		T135	20		T209	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T56	11		T59	10		T49	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T141	9		T150	9		T211	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T140	14		T72	21		T211	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T64	17		T142	14		T247	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T56	12		T64	6		T215	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T1	12		T63	29		T223	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T71	2		T134	7		T53	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22069

1

T1

16

T2

3

T3

130

auto[1]

auto[0]

4166

1

T1

23

T6

8

T12

33