Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.77 99.07 96.67 100.00 100.00 98.83 98.33 91.46


Total test records in report: 920
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T796 /workspace/coverage/default/31.adc_ctrl_filters_polled.925072382 Mar 31 12:41:21 PM PDT 24 Mar 31 01:00:48 PM PDT 24 495514230564 ps
T797 /workspace/coverage/default/38.adc_ctrl_smoke.3670321576 Mar 31 12:42:09 PM PDT 24 Mar 31 12:42:12 PM PDT 24 5737944351 ps
T798 /workspace/coverage/default/9.adc_ctrl_clock_gating.2793314947 Mar 31 12:40:00 PM PDT 24 Mar 31 12:42:47 PM PDT 24 503343631401 ps
T799 /workspace/coverage/default/36.adc_ctrl_alert_test.2666481041 Mar 31 12:42:07 PM PDT 24 Mar 31 12:42:10 PM PDT 24 480317635 ps
T800 /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1710875687 Mar 31 12:40:05 PM PDT 24 Mar 31 12:43:53 PM PDT 24 363236927958 ps
T801 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2667250815 Mar 31 12:24:14 PM PDT 24 Mar 31 12:24:16 PM PDT 24 514600614 ps
T114 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1431376773 Mar 31 12:24:12 PM PDT 24 Mar 31 12:24:14 PM PDT 24 471095182 ps
T127 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2435746205 Mar 31 12:24:11 PM PDT 24 Mar 31 12:24:12 PM PDT 24 369286935 ps
T68 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1984643528 Mar 31 12:24:03 PM PDT 24 Mar 31 12:24:22 PM PDT 24 4424990940 ps
T76 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.99830465 Mar 31 12:23:56 PM PDT 24 Mar 31 12:23:57 PM PDT 24 853603566 ps
T132 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.936582854 Mar 31 12:24:11 PM PDT 24 Mar 31 12:24:13 PM PDT 24 329190960 ps
T77 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.386227886 Mar 31 12:24:31 PM PDT 24 Mar 31 12:24:33 PM PDT 24 605595225 ps
T69 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1184116640 Mar 31 12:24:12 PM PDT 24 Mar 31 12:24:14 PM PDT 24 1882955832 ps
T802 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1660874052 Mar 31 12:24:19 PM PDT 24 Mar 31 12:24:22 PM PDT 24 417464947 ps
T78 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2793871587 Mar 31 12:24:10 PM PDT 24 Mar 31 12:24:12 PM PDT 24 700163554 ps
T89 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2004542868 Mar 31 12:24:04 PM PDT 24 Mar 31 12:24:06 PM PDT 24 566803608 ps
T73 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1166544586 Mar 31 12:24:58 PM PDT 24 Mar 31 12:25:02 PM PDT 24 4332373880 ps
T803 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3949655607 Mar 31 12:24:19 PM PDT 24 Mar 31 12:24:22 PM PDT 24 412535018 ps
T84 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1565817396 Mar 31 12:24:02 PM PDT 24 Mar 31 12:24:04 PM PDT 24 477588957 ps
T82 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3136031194 Mar 31 12:24:11 PM PDT 24 Mar 31 12:24:13 PM PDT 24 748385716 ps
T95 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.153959351 Mar 31 12:24:05 PM PDT 24 Mar 31 12:24:07 PM PDT 24 330226245 ps
T74 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2126868650 Mar 31 12:24:09 PM PDT 24 Mar 31 12:24:16 PM PDT 24 4443342164 ps
T75 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3320587160 Mar 31 12:24:01 PM PDT 24 Mar 31 12:24:05 PM PDT 24 9232159732 ps
T79 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.698902508 Mar 31 12:24:15 PM PDT 24 Mar 31 12:24:21 PM PDT 24 8886143755 ps
T804 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3820666015 Mar 31 12:24:54 PM PDT 24 Mar 31 12:24:56 PM PDT 24 366509320 ps
T128 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.161090214 Mar 31 12:23:58 PM PDT 24 Mar 31 12:23:59 PM PDT 24 459624286 ps
T805 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1069171640 Mar 31 12:24:12 PM PDT 24 Mar 31 12:24:14 PM PDT 24 396191880 ps
T115 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2707681637 Mar 31 12:24:15 PM PDT 24 Mar 31 12:24:17 PM PDT 24 402995983 ps
T806 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3255943957 Mar 31 12:24:18 PM PDT 24 Mar 31 12:24:21 PM PDT 24 430540370 ps
T133 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1286380565 Mar 31 12:24:13 PM PDT 24 Mar 31 12:24:15 PM PDT 24 342351810 ps
T83 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1559656897 Mar 31 12:24:10 PM PDT 24 Mar 31 12:24:14 PM PDT 24 451548920 ps
T85 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.4153761061 Mar 31 12:24:03 PM PDT 24 Mar 31 12:24:08 PM PDT 24 9436050386 ps
T86 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.674267301 Mar 31 12:24:11 PM PDT 24 Mar 31 12:24:13 PM PDT 24 1329447279 ps
T807 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2097893771 Mar 31 12:24:17 PM PDT 24 Mar 31 12:24:20 PM PDT 24 371080736 ps
T90 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3551622259 Mar 31 12:24:09 PM PDT 24 Mar 31 12:24:10 PM PDT 24 540408796 ps
T70 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.911219802 Mar 31 12:24:12 PM PDT 24 Mar 31 12:24:15 PM PDT 24 4953082214 ps
T808 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.4061954832 Mar 31 12:24:13 PM PDT 24 Mar 31 12:24:16 PM PDT 24 523337924 ps
T809 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2027872786 Mar 31 12:24:16 PM PDT 24 Mar 31 12:24:20 PM PDT 24 298437709 ps
T810 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3069233649 Mar 31 12:24:03 PM PDT 24 Mar 31 12:24:04 PM PDT 24 430444153 ps
T129 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2373638879 Mar 31 12:24:03 PM PDT 24 Mar 31 12:24:08 PM PDT 24 4223523797 ps
T811 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.39044375 Mar 31 12:24:08 PM PDT 24 Mar 31 12:24:09 PM PDT 24 423852059 ps
T116 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2554826383 Mar 31 12:23:59 PM PDT 24 Mar 31 12:24:02 PM PDT 24 1284553856 ps
T812 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1538326586 Mar 31 12:24:03 PM PDT 24 Mar 31 12:24:05 PM PDT 24 507638994 ps
T130 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3380125911 Mar 31 12:24:08 PM PDT 24 Mar 31 12:24:26 PM PDT 24 4890349906 ps
T88 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3100947604 Mar 31 12:24:05 PM PDT 24 Mar 31 12:24:27 PM PDT 24 8450025260 ps
T813 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.603241524 Mar 31 12:24:15 PM PDT 24 Mar 31 12:24:17 PM PDT 24 335251882 ps
T323 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2007339332 Mar 31 12:24:08 PM PDT 24 Mar 31 12:24:16 PM PDT 24 8666550373 ps
T131 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3710608021 Mar 31 12:24:09 PM PDT 24 Mar 31 12:24:23 PM PDT 24 5542935251 ps
T814 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.4050859346 Mar 31 12:24:06 PM PDT 24 Mar 31 12:24:07 PM PDT 24 539355553 ps
T815 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3005622284 Mar 31 12:24:08 PM PDT 24 Mar 31 12:24:20 PM PDT 24 5058671263 ps
T117 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1624700418 Mar 31 12:24:18 PM PDT 24 Mar 31 12:24:30 PM PDT 24 404207610 ps
T87 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2500175746 Mar 31 12:24:03 PM PDT 24 Mar 31 12:24:06 PM PDT 24 513795773 ps
T816 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.4012235043 Mar 31 12:24:08 PM PDT 24 Mar 31 12:24:09 PM PDT 24 525259848 ps
T817 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3014614524 Mar 31 12:24:09 PM PDT 24 Mar 31 12:24:11 PM PDT 24 518063125 ps
T818 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2016897228 Mar 31 12:24:07 PM PDT 24 Mar 31 12:24:08 PM PDT 24 353996217 ps
T819 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2568456682 Mar 31 12:24:07 PM PDT 24 Mar 31 12:24:08 PM PDT 24 437468235 ps
T820 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2303049763 Mar 31 12:24:20 PM PDT 24 Mar 31 12:24:23 PM PDT 24 419286512 ps
T821 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2064781246 Mar 31 12:24:21 PM PDT 24 Mar 31 12:24:22 PM PDT 24 506904193 ps
T822 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1486281577 Mar 31 12:24:10 PM PDT 24 Mar 31 12:24:21 PM PDT 24 4581288721 ps
T823 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3343147560 Mar 31 12:24:15 PM PDT 24 Mar 31 12:24:19 PM PDT 24 369852862 ps
T824 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1584766502 Mar 31 12:24:16 PM PDT 24 Mar 31 12:24:20 PM PDT 24 742535079 ps
T825 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1214795400 Mar 31 12:24:16 PM PDT 24 Mar 31 12:24:25 PM PDT 24 2521551504 ps
T91 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1193791687 Mar 31 12:24:05 PM PDT 24 Mar 31 12:24:12 PM PDT 24 8019951530 ps
T826 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.81229592 Mar 31 12:24:00 PM PDT 24 Mar 31 12:24:07 PM PDT 24 4586704065 ps
T827 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1032348613 Mar 31 12:24:08 PM PDT 24 Mar 31 12:24:10 PM PDT 24 401395887 ps
T828 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1495716337 Mar 31 12:24:14 PM PDT 24 Mar 31 12:24:16 PM PDT 24 359861756 ps
T118 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.464445571 Mar 31 12:24:08 PM PDT 24 Mar 31 12:24:09 PM PDT 24 447235958 ps
T829 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1133881180 Mar 31 12:24:18 PM PDT 24 Mar 31 12:24:21 PM PDT 24 446155798 ps
T830 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1716425674 Mar 31 12:24:10 PM PDT 24 Mar 31 12:24:12 PM PDT 24 356978679 ps
T831 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.592635383 Mar 31 12:24:11 PM PDT 24 Mar 31 12:24:12 PM PDT 24 544141710 ps
T832 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3784487682 Mar 31 12:24:11 PM PDT 24 Mar 31 12:24:13 PM PDT 24 462918717 ps
T833 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1568027586 Mar 31 12:24:14 PM PDT 24 Mar 31 12:24:16 PM PDT 24 541272433 ps
T119 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1563395513 Mar 31 12:24:06 PM PDT 24 Mar 31 12:24:14 PM PDT 24 9827444940 ps
T834 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1892914243 Mar 31 12:24:07 PM PDT 24 Mar 31 12:24:20 PM PDT 24 8696755600 ps
T835 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.594226146 Mar 31 12:24:06 PM PDT 24 Mar 31 12:24:18 PM PDT 24 4695776701 ps
T836 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.4009606428 Mar 31 12:24:18 PM PDT 24 Mar 31 12:24:21 PM PDT 24 425429254 ps
T837 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2336039937 Mar 31 12:24:14 PM PDT 24 Mar 31 12:24:51 PM PDT 24 54093982969 ps
T838 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3133259219 Mar 31 12:24:20 PM PDT 24 Mar 31 12:24:23 PM PDT 24 473958139 ps
T839 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2097192514 Mar 31 12:24:14 PM PDT 24 Mar 31 12:24:16 PM PDT 24 483655458 ps
T840 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.4266274167 Mar 31 12:24:08 PM PDT 24 Mar 31 12:24:16 PM PDT 24 8344802731 ps
T841 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.4180280623 Mar 31 12:24:16 PM PDT 24 Mar 31 12:24:20 PM PDT 24 489060395 ps
T842 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.4022024872 Mar 31 12:24:17 PM PDT 24 Mar 31 12:24:31 PM PDT 24 5166500200 ps
T843 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3784232485 Mar 31 12:23:58 PM PDT 24 Mar 31 12:24:02 PM PDT 24 4248374328 ps
T120 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1527615949 Mar 31 12:24:13 PM PDT 24 Mar 31 12:24:15 PM PDT 24 465543488 ps
T121 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1225570970 Mar 31 12:23:53 PM PDT 24 Mar 31 12:25:35 PM PDT 24 28091550869 ps
T844 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3150133280 Mar 31 12:24:15 PM PDT 24 Mar 31 12:24:16 PM PDT 24 793700665 ps
T845 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.791697672 Mar 31 12:24:17 PM PDT 24 Mar 31 12:24:20 PM PDT 24 410525131 ps
T846 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2782743762 Mar 31 12:24:16 PM PDT 24 Mar 31 12:24:18 PM PDT 24 454064711 ps
T847 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3590745109 Mar 31 12:24:01 PM PDT 24 Mar 31 12:24:03 PM PDT 24 925716721 ps
T848 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2197592724 Mar 31 12:24:17 PM PDT 24 Mar 31 12:24:24 PM PDT 24 455251919 ps
T849 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1056477154 Mar 31 12:24:19 PM PDT 24 Mar 31 12:24:22 PM PDT 24 340631834 ps
T850 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2108041730 Mar 31 12:24:13 PM PDT 24 Mar 31 12:24:16 PM PDT 24 2177598329 ps
T851 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2661067694 Mar 31 12:24:17 PM PDT 24 Mar 31 12:24:21 PM PDT 24 458540294 ps
T852 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.859986923 Mar 31 12:24:15 PM PDT 24 Mar 31 12:24:19 PM PDT 24 605975919 ps
T853 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.761158463 Mar 31 12:24:17 PM PDT 24 Mar 31 12:24:21 PM PDT 24 396668311 ps
T92 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.142483669 Mar 31 12:24:16 PM PDT 24 Mar 31 12:24:39 PM PDT 24 8509124738 ps
T854 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3688575170 Mar 31 12:24:04 PM PDT 24 Mar 31 12:24:08 PM PDT 24 590523383 ps
T855 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.427243009 Mar 31 12:24:12 PM PDT 24 Mar 31 12:24:17 PM PDT 24 1370414968 ps
T856 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2612593399 Mar 31 12:24:01 PM PDT 24 Mar 31 12:24:05 PM PDT 24 1319372647 ps
T857 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3598935920 Mar 31 12:24:10 PM PDT 24 Mar 31 12:24:11 PM PDT 24 373566157 ps
T858 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.256461032 Mar 31 12:24:11 PM PDT 24 Mar 31 12:24:13 PM PDT 24 1120022981 ps
T859 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1286743468 Mar 31 12:24:12 PM PDT 24 Mar 31 12:24:14 PM PDT 24 519856563 ps
T860 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1862769408 Mar 31 12:24:06 PM PDT 24 Mar 31 12:24:26 PM PDT 24 7861289598 ps
T861 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.115971751 Mar 31 12:24:01 PM PDT 24 Mar 31 12:24:03 PM PDT 24 367281984 ps
T862 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1337606293 Mar 31 12:24:24 PM PDT 24 Mar 31 12:24:26 PM PDT 24 496044305 ps
T863 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.396911478 Mar 31 12:24:14 PM PDT 24 Mar 31 12:24:17 PM PDT 24 613040013 ps
T864 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3958486503 Mar 31 12:24:56 PM PDT 24 Mar 31 12:24:58 PM PDT 24 430514495 ps
T865 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1315759420 Mar 31 12:24:03 PM PDT 24 Mar 31 12:24:06 PM PDT 24 535360617 ps
T122 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2920242635 Mar 31 12:24:07 PM PDT 24 Mar 31 12:24:54 PM PDT 24 35443647587 ps
T866 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1469358075 Mar 31 12:24:12 PM PDT 24 Mar 31 12:24:14 PM PDT 24 715716016 ps
T867 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.627898547 Mar 31 12:24:12 PM PDT 24 Mar 31 12:24:13 PM PDT 24 369800179 ps
T123 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.487154244 Mar 31 12:24:05 PM PDT 24 Mar 31 12:24:06 PM PDT 24 324342895 ps
T868 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2667677891 Mar 31 12:24:22 PM PDT 24 Mar 31 12:24:23 PM PDT 24 389241717 ps
T869 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3803387633 Mar 31 12:24:15 PM PDT 24 Mar 31 12:24:24 PM PDT 24 4659301366 ps
T870 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.313954605 Mar 31 12:24:14 PM PDT 24 Mar 31 12:24:20 PM PDT 24 4468875364 ps
T871 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.98144853 Mar 31 12:24:09 PM PDT 24 Mar 31 12:24:13 PM PDT 24 515291790 ps
T872 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.542524739 Mar 31 12:24:21 PM PDT 24 Mar 31 12:24:23 PM PDT 24 574560271 ps
T873 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3490825137 Mar 31 12:24:18 PM PDT 24 Mar 31 12:24:21 PM PDT 24 322527307 ps
T124 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3369455493 Mar 31 12:24:16 PM PDT 24 Mar 31 12:24:23 PM PDT 24 1086642550 ps
T874 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3780384753 Mar 31 12:24:20 PM PDT 24 Mar 31 12:24:22 PM PDT 24 373577358 ps
T125 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2040549011 Mar 31 12:24:03 PM PDT 24 Mar 31 12:24:05 PM PDT 24 540935555 ps
T875 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3981249449 Mar 31 12:24:02 PM PDT 24 Mar 31 12:24:08 PM PDT 24 2280738523 ps
T876 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.4181071832 Mar 31 12:24:09 PM PDT 24 Mar 31 12:24:30 PM PDT 24 8363546361 ps
T877 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2677888410 Mar 31 12:24:12 PM PDT 24 Mar 31 12:24:15 PM PDT 24 508718468 ps
T878 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3826720641 Mar 31 12:24:04 PM PDT 24 Mar 31 12:24:05 PM PDT 24 317122365 ps
T879 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1263693139 Mar 31 12:24:12 PM PDT 24 Mar 31 12:24:19 PM PDT 24 491057693 ps
T880 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2283495021 Mar 31 12:24:11 PM PDT 24 Mar 31 12:24:14 PM PDT 24 764153434 ps
T881 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.193975179 Mar 31 12:24:06 PM PDT 24 Mar 31 12:24:07 PM PDT 24 321273249 ps
T882 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1347393737 Mar 31 12:23:58 PM PDT 24 Mar 31 12:24:00 PM PDT 24 554838380 ps
T883 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2832834187 Mar 31 12:24:24 PM PDT 24 Mar 31 12:24:26 PM PDT 24 332870980 ps
T884 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.4026623570 Mar 31 12:24:05 PM PDT 24 Mar 31 12:24:06 PM PDT 24 371103560 ps
T885 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2358675819 Mar 31 12:24:17 PM PDT 24 Mar 31 12:24:21 PM PDT 24 2646166695 ps
T324 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.4017067912 Mar 31 12:24:07 PM PDT 24 Mar 31 12:24:29 PM PDT 24 8341743749 ps
T126 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2089845073 Mar 31 12:24:11 PM PDT 24 Mar 31 12:24:39 PM PDT 24 29577591083 ps
T886 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3186424908 Mar 31 12:24:10 PM PDT 24 Mar 31 12:24:12 PM PDT 24 452158111 ps
T887 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.894211313 Mar 31 12:24:01 PM PDT 24 Mar 31 12:24:04 PM PDT 24 2415898980 ps
T888 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1457632394 Mar 31 12:24:18 PM PDT 24 Mar 31 12:24:21 PM PDT 24 420966190 ps
T889 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2689070060 Mar 31 12:24:10 PM PDT 24 Mar 31 12:24:11 PM PDT 24 348064284 ps
T890 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3784856419 Mar 31 12:24:17 PM PDT 24 Mar 31 12:24:20 PM PDT 24 432477359 ps
T891 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2002088731 Mar 31 12:24:58 PM PDT 24 Mar 31 12:25:00 PM PDT 24 555161360 ps
T892 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1025864783 Mar 31 12:24:58 PM PDT 24 Mar 31 12:24:59 PM PDT 24 378460024 ps
T893 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3790239113 Mar 31 12:24:15 PM PDT 24 Mar 31 12:24:19 PM PDT 24 2859113664 ps
T894 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2217585600 Mar 31 12:24:18 PM PDT 24 Mar 31 12:24:21 PM PDT 24 414549465 ps
T895 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.4144221347 Mar 31 12:24:13 PM PDT 24 Mar 31 12:24:15 PM PDT 24 378500748 ps
T896 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.4207257345 Mar 31 12:24:01 PM PDT 24 Mar 31 12:24:03 PM PDT 24 753145158 ps
T897 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2101667136 Mar 31 12:24:14 PM PDT 24 Mar 31 12:24:17 PM PDT 24 661925004 ps
T898 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2371002980 Mar 31 12:24:06 PM PDT 24 Mar 31 12:24:08 PM PDT 24 619968657 ps
T899 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.591034171 Mar 31 12:24:07 PM PDT 24 Mar 31 12:24:09 PM PDT 24 573075644 ps
T325 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.504085466 Mar 31 12:24:06 PM PDT 24 Mar 31 12:24:10 PM PDT 24 4528201410 ps
T900 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.523933736 Mar 31 12:23:57 PM PDT 24 Mar 31 12:23:58 PM PDT 24 436563841 ps
T901 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2520091039 Mar 31 12:24:59 PM PDT 24 Mar 31 12:25:01 PM PDT 24 476394573 ps
T902 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2442610635 Mar 31 12:24:16 PM PDT 24 Mar 31 12:24:20 PM PDT 24 325026057 ps
T903 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3882370180 Mar 31 12:24:19 PM PDT 24 Mar 31 12:24:21 PM PDT 24 508321781 ps
T904 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.547204601 Mar 31 12:23:56 PM PDT 24 Mar 31 12:23:58 PM PDT 24 595100917 ps
T905 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1709847169 Mar 31 12:24:10 PM PDT 24 Mar 31 12:24:12 PM PDT 24 485430689 ps
T906 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.982350689 Mar 31 12:24:00 PM PDT 24 Mar 31 12:24:12 PM PDT 24 4479359626 ps
T907 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1438778891 Mar 31 12:23:57 PM PDT 24 Mar 31 12:24:00 PM PDT 24 1021848258 ps
T908 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3834043268 Mar 31 12:24:04 PM PDT 24 Mar 31 12:24:06 PM PDT 24 799155483 ps
T909 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2137545864 Mar 31 12:24:01 PM PDT 24 Mar 31 12:24:17 PM PDT 24 8326343637 ps
T910 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.891242576 Mar 31 12:24:10 PM PDT 24 Mar 31 12:24:11 PM PDT 24 532922146 ps
T911 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2333374417 Mar 31 12:24:05 PM PDT 24 Mar 31 12:24:07 PM PDT 24 504987684 ps
T912 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1958017304 Mar 31 12:24:17 PM PDT 24 Mar 31 12:24:20 PM PDT 24 430468648 ps
T913 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2054644678 Mar 31 12:24:16 PM PDT 24 Mar 31 12:24:19 PM PDT 24 307750990 ps
T914 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.535351327 Mar 31 12:24:13 PM PDT 24 Mar 31 12:24:18 PM PDT 24 826712335 ps
T915 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2137706937 Mar 31 12:24:20 PM PDT 24 Mar 31 12:24:22 PM PDT 24 526983542 ps
T916 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.433138844 Mar 31 12:24:03 PM PDT 24 Mar 31 12:24:14 PM PDT 24 2411046803 ps
T917 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2725131575 Mar 31 12:24:02 PM PDT 24 Mar 31 12:24:03 PM PDT 24 483010486 ps
T918 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2157171805 Mar 31 12:24:19 PM PDT 24 Mar 31 12:24:41 PM PDT 24 8239684405 ps
T919 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.4245141661 Mar 31 12:24:31 PM PDT 24 Mar 31 12:24:33 PM PDT 24 2397770641 ps
T920 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.668872152 Mar 31 12:24:06 PM PDT 24 Mar 31 12:24:15 PM PDT 24 7983430120 ps

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2819536307
Short name T1
Test name
Test status
Simulation time 342021516572 ps
CPU time 187.36 seconds
Started Mar 31 12:40:09 PM PDT 24
Finished Mar 31 12:43:17 PM PDT 24
Peak memory 201780 kb
Host smart-8e81496e-45c4-4fd4-badd-86a055beed08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819536307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2819536307
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3482768327
Short name T49
Test name
Test status
Simulation time 405554367451 ps
CPU time 304.67 seconds
Started Mar 31 12:40:34 PM PDT 24
Finished Mar 31 12:45:39 PM PDT 24
Peak memory 218168 kb
Host smart-e17f13de-b3e8-4c5c-971c-a1ab1eb4cf85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482768327 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.3482768327
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.3086148258
Short name T51
Test name
Test status
Simulation time 588612365236 ps
CPU time 260.17 seconds
Started Mar 31 12:42:56 PM PDT 24
Finished Mar 31 12:47:16 PM PDT 24
Peak memory 210564 kb
Host smart-b38c7e07-1c9f-4e20-80f1-ecacbae38818
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086148258 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.3086148258
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2297781446
Short name T158
Test name
Test status
Simulation time 674380677167 ps
CPU time 151.24 seconds
Started Mar 31 12:40:34 PM PDT 24
Finished Mar 31 12:43:06 PM PDT 24
Peak memory 201872 kb
Host smart-046b2ba2-aae6-42bd-9d8b-312a8617311c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297781446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2297781446
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.4190025349
Short name T65
Test name
Test status
Simulation time 84740094613 ps
CPU time 312.49 seconds
Started Mar 31 12:40:31 PM PDT 24
Finished Mar 31 12:45:43 PM PDT 24
Peak memory 202140 kb
Host smart-9c43e42c-508f-4acb-985f-2db21e5f43d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190025349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.4190025349
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.1372417314
Short name T12
Test name
Test status
Simulation time 533588525824 ps
CPU time 398.85 seconds
Started Mar 31 12:43:14 PM PDT 24
Finished Mar 31 12:49:54 PM PDT 24
Peak memory 201900 kb
Host smart-bd7957aa-9ec1-4532-af61-4b8679075e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372417314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1372417314
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.387118656
Short name T15
Test name
Test status
Simulation time 58114405657 ps
CPU time 104.04 seconds
Started Mar 31 12:39:57 PM PDT 24
Finished Mar 31 12:41:41 PM PDT 24
Peak memory 210520 kb
Host smart-50bf91d1-bbd5-408c-be2f-404f9a4da4d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387118656 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.387118656
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3098609573
Short name T142
Test name
Test status
Simulation time 497788573019 ps
CPU time 1158.82 seconds
Started Mar 31 12:41:56 PM PDT 24
Finished Mar 31 01:01:15 PM PDT 24
Peak memory 201804 kb
Host smart-f5861947-d529-4c17-b3e0-ded338bb7e72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098609573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3098609573
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.408059746
Short name T155
Test name
Test status
Simulation time 551473342185 ps
CPU time 286.11 seconds
Started Mar 31 12:40:01 PM PDT 24
Finished Mar 31 12:44:47 PM PDT 24
Peak memory 201956 kb
Host smart-d7a3b2d2-a66d-4cb8-9d43-200083a4da74
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408059746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin
g.408059746
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3553086967
Short name T141
Test name
Test status
Simulation time 497503700432 ps
CPU time 1248.57 seconds
Started Mar 31 12:40:07 PM PDT 24
Finished Mar 31 01:00:55 PM PDT 24
Peak memory 201772 kb
Host smart-4932d5f4-1daf-496a-9ccd-917fb7b3449f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553086967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3553086967
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1558394077
Short name T4
Test name
Test status
Simulation time 8914283766 ps
CPU time 19.73 seconds
Started Mar 31 12:40:11 PM PDT 24
Finished Mar 31 12:40:32 PM PDT 24
Peak memory 217816 kb
Host smart-c6599345-41e8-4e1b-a437-e56ee1b53a68
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558394077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1558394077
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3136031194
Short name T82
Test name
Test status
Simulation time 748385716 ps
CPU time 1.67 seconds
Started Mar 31 12:24:11 PM PDT 24
Finished Mar 31 12:24:13 PM PDT 24
Peak memory 201912 kb
Host smart-8d92f781-3965-46df-b0ca-cf267936bba5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136031194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3136031194
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3441449903
Short name T72
Test name
Test status
Simulation time 514701258774 ps
CPU time 906.26 seconds
Started Mar 31 12:41:26 PM PDT 24
Finished Mar 31 12:56:33 PM PDT 24
Peak memory 201828 kb
Host smart-152167bf-8136-4c70-8f92-818016803b01
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441449903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3441449903
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1887987398
Short name T5
Test name
Test status
Simulation time 163325430617 ps
CPU time 62.4 seconds
Started Mar 31 12:41:22 PM PDT 24
Finished Mar 31 12:42:25 PM PDT 24
Peak memory 201820 kb
Host smart-0f36cadf-44d7-4860-9646-a2f679c3aa57
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887987398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.1887987398
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.493458187
Short name T233
Test name
Test status
Simulation time 667590177653 ps
CPU time 481.63 seconds
Started Mar 31 12:43:57 PM PDT 24
Finished Mar 31 12:51:59 PM PDT 24
Peak memory 202256 kb
Host smart-bbdb5bf6-d1e3-49e5-83d9-f9426919ac46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493458187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
493458187
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.507468857
Short name T160
Test name
Test status
Simulation time 577777050772 ps
CPU time 205.17 seconds
Started Mar 31 12:40:02 PM PDT 24
Finished Mar 31 12:43:27 PM PDT 24
Peak memory 201852 kb
Host smart-997c7c6a-8218-40a2-aa26-4774bf8a7ac8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507468857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gatin
g.507468857
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3961792959
Short name T99
Test name
Test status
Simulation time 500904661267 ps
CPU time 316.19 seconds
Started Mar 31 12:40:42 PM PDT 24
Finished Mar 31 12:45:59 PM PDT 24
Peak memory 201876 kb
Host smart-6636f471-dab7-4ca2-9f03-d649a65f1551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961792959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3961792959
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.4036103875
Short name T247
Test name
Test status
Simulation time 331779416939 ps
CPU time 193.78 seconds
Started Mar 31 12:42:09 PM PDT 24
Finished Mar 31 12:45:23 PM PDT 24
Peak memory 201888 kb
Host smart-84e89ebe-4646-4049-922c-682e9a10961c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036103875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.4036103875
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.4250393811
Short name T60
Test name
Test status
Simulation time 161774035492 ps
CPU time 386.57 seconds
Started Mar 31 12:43:42 PM PDT 24
Finished Mar 31 12:50:09 PM PDT 24
Peak memory 201860 kb
Host smart-30f4be1c-39ed-4572-aa77-699fdffbe579
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250393811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.4250393811
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1431376773
Short name T114
Test name
Test status
Simulation time 471095182 ps
CPU time 1.3 seconds
Started Mar 31 12:24:12 PM PDT 24
Finished Mar 31 12:24:14 PM PDT 24
Peak memory 201560 kb
Host smart-fcf2e71a-041f-475a-8b7f-b4ad74323db6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431376773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1431376773
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.3865574427
Short name T230
Test name
Test status
Simulation time 336056374762 ps
CPU time 382.97 seconds
Started Mar 31 12:40:29 PM PDT 24
Finished Mar 31 12:46:52 PM PDT 24
Peak memory 201960 kb
Host smart-972cb6ba-a379-446f-a817-4d21528a8edc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865574427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.3865574427
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.1822757465
Short name T29
Test name
Test status
Simulation time 588656041793 ps
CPU time 281.86 seconds
Started Mar 31 12:43:49 PM PDT 24
Finished Mar 31 12:48:31 PM PDT 24
Peak memory 201820 kb
Host smart-1800c548-306d-41a3-bc45-34f6efed6617
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822757465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.1822757465
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.1311619372
Short name T191
Test name
Test status
Simulation time 412550036610 ps
CPU time 490.09 seconds
Started Mar 31 12:40:14 PM PDT 24
Finished Mar 31 12:48:25 PM PDT 24
Peak memory 201772 kb
Host smart-c47ae1ca-46a5-49ee-9e0d-ca5cf996a5d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311619372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.1311619372
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.2510999109
Short name T282
Test name
Test status
Simulation time 578781958543 ps
CPU time 1147.31 seconds
Started Mar 31 12:40:15 PM PDT 24
Finished Mar 31 12:59:23 PM PDT 24
Peak memory 201928 kb
Host smart-d391ced9-b35d-4ee6-a931-d80c654b5583
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510999109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.2510999109
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.4112509572
Short name T14
Test name
Test status
Simulation time 31738115614 ps
CPU time 20.17 seconds
Started Mar 31 12:41:27 PM PDT 24
Finished Mar 31 12:41:47 PM PDT 24
Peak memory 202036 kb
Host smart-a06ad666-b859-49c0-b026-169e4bc2ec90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112509572 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.4112509572
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3477162635
Short name T286
Test name
Test status
Simulation time 161972772714 ps
CPU time 91.36 seconds
Started Mar 31 12:41:02 PM PDT 24
Finished Mar 31 12:42:34 PM PDT 24
Peak memory 201884 kb
Host smart-bdca1f2b-9690-4f27-ac86-55f2f25a39c4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477162635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3477162635
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2774595783
Short name T169
Test name
Test status
Simulation time 320177111311 ps
CPU time 134.1 seconds
Started Mar 31 12:42:11 PM PDT 24
Finished Mar 31 12:44:26 PM PDT 24
Peak memory 201804 kb
Host smart-60fa86ce-ef39-4c19-8dca-5a4d0270178f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774595783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2774595783
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.698902508
Short name T79
Test name
Test status
Simulation time 8886143755 ps
CPU time 3.79 seconds
Started Mar 31 12:24:15 PM PDT 24
Finished Mar 31 12:24:21 PM PDT 24
Peak memory 201844 kb
Host smart-4e1a25af-1e9f-424c-8504-80d9b78df4c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698902508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.698902508
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3710608021
Short name T131
Test name
Test status
Simulation time 5542935251 ps
CPU time 13.12 seconds
Started Mar 31 12:24:09 PM PDT 24
Finished Mar 31 12:24:23 PM PDT 24
Peak memory 201880 kb
Host smart-9a024052-2897-4161-bcc0-be289f1af2a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710608021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3710608021
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3823215637
Short name T260
Test name
Test status
Simulation time 163311639152 ps
CPU time 218.49 seconds
Started Mar 31 12:40:38 PM PDT 24
Finished Mar 31 12:44:18 PM PDT 24
Peak memory 201960 kb
Host smart-121279ee-726f-4bb2-b4ca-6b7a2fc84ee3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823215637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3823215637
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3163946998
Short name T266
Test name
Test status
Simulation time 528748282244 ps
CPU time 1326.09 seconds
Started Mar 31 12:43:29 PM PDT 24
Finished Mar 31 01:05:36 PM PDT 24
Peak memory 201932 kb
Host smart-8780c04c-0535-46ae-b064-7c074463a2bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163946998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3163946998
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2817131902
Short name T108
Test name
Test status
Simulation time 329552410536 ps
CPU time 774.24 seconds
Started Mar 31 12:40:55 PM PDT 24
Finished Mar 31 12:53:49 PM PDT 24
Peak memory 201892 kb
Host smart-d487d348-f985-4671-be67-16100a3f4f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817131902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2817131902
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3142418985
Short name T396
Test name
Test status
Simulation time 301883255 ps
CPU time 1.35 seconds
Started Mar 31 12:40:11 PM PDT 24
Finished Mar 31 12:40:14 PM PDT 24
Peak memory 201456 kb
Host smart-46921102-0a26-4d96-9958-6c6f7fa42a82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142418985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3142418985
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.3939377996
Short name T149
Test name
Test status
Simulation time 493296967641 ps
CPU time 299.29 seconds
Started Mar 31 12:40:25 PM PDT 24
Finished Mar 31 12:45:24 PM PDT 24
Peak memory 201852 kb
Host smart-2c684787-444a-45ed-89e5-7820fddac25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939377996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.3939377996
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.21750006
Short name T268
Test name
Test status
Simulation time 515578206019 ps
CPU time 1260.47 seconds
Started Mar 31 12:40:08 PM PDT 24
Finished Mar 31 01:01:10 PM PDT 24
Peak memory 201944 kb
Host smart-7885c157-1772-432d-a1db-3f7b3e760e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21750006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.21750006
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2074770039
Short name T109
Test name
Test status
Simulation time 327472014896 ps
CPU time 109.1 seconds
Started Mar 31 12:39:51 PM PDT 24
Finished Mar 31 12:41:40 PM PDT 24
Peak memory 201936 kb
Host smart-63590e4f-3f4f-4832-857e-ea96d812cc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074770039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2074770039
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1412336736
Short name T275
Test name
Test status
Simulation time 346463150390 ps
CPU time 805.1 seconds
Started Mar 31 12:42:27 PM PDT 24
Finished Mar 31 12:55:52 PM PDT 24
Peak memory 201816 kb
Host smart-ab3d7eab-05e2-4615-97e3-4a5e03e9c9a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412336736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1412336736
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.3560368662
Short name T258
Test name
Test status
Simulation time 355578915363 ps
CPU time 848.82 seconds
Started Mar 31 12:40:07 PM PDT 24
Finished Mar 31 12:54:16 PM PDT 24
Peak memory 201804 kb
Host smart-ae009148-12d5-4d98-b9fe-3a60db95e9ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560368662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.3560368662
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2838764332
Short name T157
Test name
Test status
Simulation time 497524724924 ps
CPU time 797.35 seconds
Started Mar 31 12:40:49 PM PDT 24
Finished Mar 31 12:54:07 PM PDT 24
Peak memory 201944 kb
Host smart-793967bd-6feb-42a0-a460-292dac30140e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838764332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2838764332
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3893479751
Short name T241
Test name
Test status
Simulation time 360409596156 ps
CPU time 357.69 seconds
Started Mar 31 12:41:21 PM PDT 24
Finished Mar 31 12:47:19 PM PDT 24
Peak memory 201872 kb
Host smart-874f6192-e4cb-4029-9b5f-a02b0e67d59b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893479751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3893479751
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.1126622836
Short name T271
Test name
Test status
Simulation time 324967318042 ps
CPU time 742.9 seconds
Started Mar 31 12:41:15 PM PDT 24
Finished Mar 31 12:53:38 PM PDT 24
Peak memory 201860 kb
Host smart-24838760-06ef-4e9b-b03e-7635f11c0f05
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126622836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.1126622836
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.923276320
Short name T237
Test name
Test status
Simulation time 498787492508 ps
CPU time 1297.26 seconds
Started Mar 31 12:40:08 PM PDT 24
Finished Mar 31 01:01:45 PM PDT 24
Peak memory 201808 kb
Host smart-5736211d-06c4-43d0-a5e7-6108fda1a1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923276320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.923276320
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.4058875501
Short name T223
Test name
Test status
Simulation time 215037780639 ps
CPU time 127.92 seconds
Started Mar 31 12:40:10 PM PDT 24
Finished Mar 31 12:42:19 PM PDT 24
Peak memory 201808 kb
Host smart-42d48e21-caa0-4151-b3e9-e8ba29db6ed3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058875501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.4058875501
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.297638224
Short name T135
Test name
Test status
Simulation time 501453285910 ps
CPU time 1163.54 seconds
Started Mar 31 12:40:12 PM PDT 24
Finished Mar 31 12:59:36 PM PDT 24
Peak memory 201880 kb
Host smart-465f05e9-87c7-467c-9ba0-ee05fcd3c8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297638224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.297638224
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.3523565337
Short name T33
Test name
Test status
Simulation time 108450540392 ps
CPU time 236.33 seconds
Started Mar 31 12:40:47 PM PDT 24
Finished Mar 31 12:44:44 PM PDT 24
Peak memory 210156 kb
Host smart-33355bb5-a5d3-43f1-8d1b-0dfe5a129851
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523565337 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.3523565337
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2843011165
Short name T202
Test name
Test status
Simulation time 1066353397675 ps
CPU time 1127.25 seconds
Started Mar 31 12:40:52 PM PDT 24
Finished Mar 31 12:59:39 PM PDT 24
Peak memory 210592 kb
Host smart-280f4da7-94d2-4036-a85d-6134160e5d92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843011165 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.2843011165
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3046717056
Short name T302
Test name
Test status
Simulation time 187114305197 ps
CPU time 88.66 seconds
Started Mar 31 12:41:51 PM PDT 24
Finished Mar 31 12:43:20 PM PDT 24
Peak memory 201764 kb
Host smart-02e1c615-b996-469b-8eb5-2949c96f601d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046717056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3046717056
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2316020553
Short name T248
Test name
Test status
Simulation time 325490740433 ps
CPU time 141.45 seconds
Started Mar 31 12:41:25 PM PDT 24
Finished Mar 31 12:43:46 PM PDT 24
Peak memory 201888 kb
Host smart-2d3ec218-5d24-4548-ad79-629e105a6245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316020553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2316020553
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.48157613
Short name T251
Test name
Test status
Simulation time 341733854614 ps
CPU time 90.35 seconds
Started Mar 31 12:40:13 PM PDT 24
Finished Mar 31 12:41:45 PM PDT 24
Peak memory 201948 kb
Host smart-81714d9e-5ffb-46a5-96f1-fef8bf9f4fae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48157613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gatin
g.48157613
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.596485876
Short name T209
Test name
Test status
Simulation time 349551016784 ps
CPU time 218.86 seconds
Started Mar 31 12:41:15 PM PDT 24
Finished Mar 31 12:44:54 PM PDT 24
Peak memory 201884 kb
Host smart-9d22be0b-41af-478a-a552-ebbcaff4b9bb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596485876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_
wakeup.596485876
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1469168121
Short name T270
Test name
Test status
Simulation time 164448224375 ps
CPU time 374.64 seconds
Started Mar 31 12:41:49 PM PDT 24
Finished Mar 31 12:48:04 PM PDT 24
Peak memory 201884 kb
Host smart-4895cfc5-624b-486c-b4fe-c01dff0b57be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469168121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1469168121
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2508545340
Short name T144
Test name
Test status
Simulation time 253947938052 ps
CPU time 485.68 seconds
Started Mar 31 12:40:48 PM PDT 24
Finished Mar 31 12:48:55 PM PDT 24
Peak memory 202288 kb
Host smart-f6c12dd5-f3e6-4624-a08d-41baf59e2b82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508545340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2508545340
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.872179215
Short name T250
Test name
Test status
Simulation time 328167273783 ps
CPU time 39.31 seconds
Started Mar 31 12:41:46 PM PDT 24
Finished Mar 31 12:42:26 PM PDT 24
Peak memory 201876 kb
Host smart-70a3ab49-cba5-4634-a7c7-6236643df154
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872179215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gati
ng.872179215
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3388704424
Short name T280
Test name
Test status
Simulation time 325995505881 ps
CPU time 463.13 seconds
Started Mar 31 12:42:17 PM PDT 24
Finished Mar 31 12:50:01 PM PDT 24
Peak memory 210576 kb
Host smart-14bc5885-30bc-4e3e-91ba-1fef7f268cb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388704424 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3388704424
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3525641021
Short name T38
Test name
Test status
Simulation time 332596610714 ps
CPU time 154.75 seconds
Started Mar 31 12:42:27 PM PDT 24
Finished Mar 31 12:45:02 PM PDT 24
Peak memory 201932 kb
Host smart-96d73a25-9280-4d94-bcbc-8b6e58bf7f49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525641021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3525641021
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.4235102769
Short name T207
Test name
Test status
Simulation time 535319048071 ps
CPU time 581.74 seconds
Started Mar 31 12:43:10 PM PDT 24
Finished Mar 31 12:52:53 PM PDT 24
Peak memory 201872 kb
Host smart-b4c56d2e-00ff-4002-afcd-7eae48e43b58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235102769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.4235102769
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.1295911249
Short name T107
Test name
Test status
Simulation time 500769851993 ps
CPU time 177.23 seconds
Started Mar 31 12:40:13 PM PDT 24
Finished Mar 31 12:43:11 PM PDT 24
Peak memory 218444 kb
Host smart-519fec27-6044-490c-93ef-7d7482fe8ff0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295911249 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.1295911249
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.2200678433
Short name T24
Test name
Test status
Simulation time 460775039620 ps
CPU time 114.39 seconds
Started Mar 31 12:40:11 PM PDT 24
Finished Mar 31 12:42:07 PM PDT 24
Peak memory 201740 kb
Host smart-803510a4-9163-4f04-973c-d25cfcdcec0b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200678433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.2200678433
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.548835529
Short name T319
Test name
Test status
Simulation time 338668146028 ps
CPU time 214.18 seconds
Started Mar 31 12:40:46 PM PDT 24
Finished Mar 31 12:44:21 PM PDT 24
Peak memory 201940 kb
Host smart-8fa4c102-730c-4aed-b8a0-f157cea980cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548835529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gati
ng.548835529
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.44211905
Short name T218
Test name
Test status
Simulation time 331705000062 ps
CPU time 57.49 seconds
Started Mar 31 12:41:27 PM PDT 24
Finished Mar 31 12:42:25 PM PDT 24
Peak memory 201780 kb
Host smart-4f95b2b7-26a5-4882-902b-54e4d8d1c7ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44211905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.44211905
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.1790559529
Short name T235
Test name
Test status
Simulation time 324884237612 ps
CPU time 394.75 seconds
Started Mar 31 12:40:12 PM PDT 24
Finished Mar 31 12:46:47 PM PDT 24
Peak memory 201796 kb
Host smart-1da4bdbb-3a87-423b-9c88-30c0d45a0ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790559529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.1790559529
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3771941530
Short name T27
Test name
Test status
Simulation time 343154391020 ps
CPU time 424.21 seconds
Started Mar 31 12:40:13 PM PDT 24
Finished Mar 31 12:47:18 PM PDT 24
Peak memory 201936 kb
Host smart-78ea05a2-6a61-4657-925f-3a6dd3d602dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771941530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3771941530
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2798632809
Short name T305
Test name
Test status
Simulation time 490217346325 ps
CPU time 549.38 seconds
Started Mar 31 12:40:32 PM PDT 24
Finished Mar 31 12:49:41 PM PDT 24
Peak memory 201916 kb
Host smart-59177d4c-9ca9-4c9b-955c-75579d80261f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798632809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2798632809
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.778990959
Short name T284
Test name
Test status
Simulation time 330321401604 ps
CPU time 404.27 seconds
Started Mar 31 12:40:50 PM PDT 24
Finished Mar 31 12:47:35 PM PDT 24
Peak memory 201800 kb
Host smart-1a7bf24d-d95d-41cd-ab30-b03bf6a0ad24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778990959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.778990959
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.141660722
Short name T265
Test name
Test status
Simulation time 332377364157 ps
CPU time 741.08 seconds
Started Mar 31 12:40:00 PM PDT 24
Finished Mar 31 12:52:21 PM PDT 24
Peak memory 201972 kb
Host smart-eba8901f-ec0f-42ea-b741-223f83a4a8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141660722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.141660722
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1706368737
Short name T204
Test name
Test status
Simulation time 77773968074 ps
CPU time 85.14 seconds
Started Mar 31 12:41:45 PM PDT 24
Finished Mar 31 12:43:10 PM PDT 24
Peak memory 211540 kb
Host smart-29a83b9a-fb30-4367-81ab-e9a62074e9c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706368737 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1706368737
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3220334383
Short name T288
Test name
Test status
Simulation time 42109385246 ps
CPU time 54.24 seconds
Started Mar 31 12:40:00 PM PDT 24
Finished Mar 31 12:40:54 PM PDT 24
Peak memory 210400 kb
Host smart-9a715fc2-a985-4b12-bf70-67574bca501d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220334383 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3220334383
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.4153761061
Short name T85
Test name
Test status
Simulation time 9436050386 ps
CPU time 5.41 seconds
Started Mar 31 12:24:03 PM PDT 24
Finished Mar 31 12:24:08 PM PDT 24
Peak memory 201860 kb
Host smart-5a99634b-1519-4fa4-bdb4-d09b1a47659b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153761061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.4153761061
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1951019997
Short name T198
Test name
Test status
Simulation time 130442618565 ps
CPU time 523.01 seconds
Started Mar 31 12:40:09 PM PDT 24
Finished Mar 31 12:48:53 PM PDT 24
Peak memory 202184 kb
Host smart-3416c4c1-bf74-42b2-9c98-9bb44db286db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951019997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1951019997
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.86618612
Short name T488
Test name
Test status
Simulation time 534453938673 ps
CPU time 1244.03 seconds
Started Mar 31 12:40:28 PM PDT 24
Finished Mar 31 01:01:13 PM PDT 24
Peak memory 201940 kb
Host smart-86428452-a6db-41a9-b12e-8849277cd7f8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86618612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_w
akeup.86618612
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.821794137
Short name T257
Test name
Test status
Simulation time 569553565263 ps
CPU time 264.53 seconds
Started Mar 31 12:40:35 PM PDT 24
Finished Mar 31 12:44:59 PM PDT 24
Peak memory 201900 kb
Host smart-86431ad2-aa18-4e2e-9c5d-00e7a05bd994
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821794137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gati
ng.821794137
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.2285722064
Short name T154
Test name
Test status
Simulation time 545621037960 ps
CPU time 168.54 seconds
Started Mar 31 12:40:43 PM PDT 24
Finished Mar 31 12:43:32 PM PDT 24
Peak memory 201944 kb
Host smart-88f04330-e231-4663-8fbc-35f3ec52a0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285722064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.2285722064
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2501363583
Short name T290
Test name
Test status
Simulation time 491868806065 ps
CPU time 280.61 seconds
Started Mar 31 12:40:46 PM PDT 24
Finished Mar 31 12:45:27 PM PDT 24
Peak memory 201760 kb
Host smart-38f06be8-05ee-4be2-b8df-ac5cefb7eebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501363583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2501363583
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.4109036479
Short name T162
Test name
Test status
Simulation time 188678148065 ps
CPU time 64.2 seconds
Started Mar 31 12:41:01 PM PDT 24
Finished Mar 31 12:42:06 PM PDT 24
Peak memory 201912 kb
Host smart-ead7062b-eed8-4847-8ae4-7650bf5b2fee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109036479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.4109036479
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.60519755
Short name T201
Test name
Test status
Simulation time 125791262685 ps
CPU time 595.65 seconds
Started Mar 31 12:42:25 PM PDT 24
Finished Mar 31 12:52:20 PM PDT 24
Peak memory 202168 kb
Host smart-36b3a9e9-a5d6-43a0-acf5-98c1da89aa1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60519755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.60519755
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.3109831437
Short name T273
Test name
Test status
Simulation time 323850005784 ps
CPU time 110.09 seconds
Started Mar 31 12:43:48 PM PDT 24
Finished Mar 31 12:45:38 PM PDT 24
Peak memory 201872 kb
Host smart-04d70732-b073-4af3-8aa6-45c6210decbd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109831437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.3109831437
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.4006942421
Short name T277
Test name
Test status
Simulation time 166245748151 ps
CPU time 96.37 seconds
Started Mar 31 12:40:15 PM PDT 24
Finished Mar 31 12:41:52 PM PDT 24
Peak memory 201916 kb
Host smart-88a45d46-1cb4-4a94-8458-ba9388254957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006942421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.4006942421
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1999161033
Short name T278
Test name
Test status
Simulation time 572487947589 ps
CPU time 364.49 seconds
Started Mar 31 12:40:44 PM PDT 24
Finished Mar 31 12:46:49 PM PDT 24
Peak memory 201988 kb
Host smart-4d493831-03ec-4109-ab48-bb45ba80d119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999161033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1999161033
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3339078083
Short name T211
Test name
Test status
Simulation time 376755483491 ps
CPU time 918.26 seconds
Started Mar 31 12:40:51 PM PDT 24
Finished Mar 31 12:56:09 PM PDT 24
Peak memory 201820 kb
Host smart-be41ee8b-110c-4c82-9c8e-0fd10734dcdf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339078083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3339078083
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.998090166
Short name T306
Test name
Test status
Simulation time 364305839582 ps
CPU time 138.62 seconds
Started Mar 31 12:40:54 PM PDT 24
Finished Mar 31 12:43:13 PM PDT 24
Peak memory 201900 kb
Host smart-c52a6af1-239e-48aa-9bd1-239ee714429c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998090166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.998090166
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2319135586
Short name T326
Test name
Test status
Simulation time 65695266908 ps
CPU time 376.24 seconds
Started Mar 31 12:41:26 PM PDT 24
Finished Mar 31 12:47:42 PM PDT 24
Peak memory 202248 kb
Host smart-9263be15-3ed5-4d35-9a69-81d754745869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319135586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2319135586
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2163361549
Short name T329
Test name
Test status
Simulation time 127047844529 ps
CPU time 515.7 seconds
Started Mar 31 12:41:28 PM PDT 24
Finished Mar 31 12:50:04 PM PDT 24
Peak memory 202164 kb
Host smart-96c65b77-3906-4e5e-bcd2-2f4539545912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163361549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2163361549
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2700385440
Short name T300
Test name
Test status
Simulation time 368800819265 ps
CPU time 808.81 seconds
Started Mar 31 12:43:16 PM PDT 24
Finished Mar 31 12:56:46 PM PDT 24
Peak memory 201964 kb
Host smart-94b7628d-0b87-4b74-a9b3-b74ae86e8b6a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700385440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2700385440
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2605859242
Short name T64
Test name
Test status
Simulation time 346451371123 ps
CPU time 199.24 seconds
Started Mar 31 12:43:37 PM PDT 24
Finished Mar 31 12:46:56 PM PDT 24
Peak memory 201892 kb
Host smart-6bb4347f-7b57-4f85-a4f8-ed409a049d00
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605859242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2605859242
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2913278570
Short name T166
Test name
Test status
Simulation time 571127854649 ps
CPU time 1294.11 seconds
Started Mar 31 12:43:50 PM PDT 24
Finished Mar 31 01:05:25 PM PDT 24
Peak memory 201968 kb
Host smart-06386d65-d007-4fda-b762-1e9db77e4364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913278570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2913278570
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3078402706
Short name T244
Test name
Test status
Simulation time 193412300167 ps
CPU time 147.43 seconds
Started Mar 31 12:43:56 PM PDT 24
Finished Mar 31 12:46:23 PM PDT 24
Peak memory 201952 kb
Host smart-84aebfbd-ec10-489b-bd14-f7bc74458998
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078402706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3078402706
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3590745109
Short name T847
Test name
Test status
Simulation time 925716721 ps
CPU time 1.87 seconds
Started Mar 31 12:24:01 PM PDT 24
Finished Mar 31 12:24:03 PM PDT 24
Peak memory 201820 kb
Host smart-d2f71537-08c9-4697-8b35-5669c1d87239
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590745109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3590745109
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1225570970
Short name T121
Test name
Test status
Simulation time 28091550869 ps
CPU time 102.34 seconds
Started Mar 31 12:23:53 PM PDT 24
Finished Mar 31 12:25:35 PM PDT 24
Peak memory 201812 kb
Host smart-1a695799-7794-40fe-adaa-2128cc655f93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225570970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1225570970
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2283495021
Short name T880
Test name
Test status
Simulation time 764153434 ps
CPU time 2.55 seconds
Started Mar 31 12:24:11 PM PDT 24
Finished Mar 31 12:24:14 PM PDT 24
Peak memory 201600 kb
Host smart-3ec969d8-457a-47de-a20d-0bb36b5df4dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283495021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2283495021
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2371002980
Short name T898
Test name
Test status
Simulation time 619968657 ps
CPU time 1.12 seconds
Started Mar 31 12:24:06 PM PDT 24
Finished Mar 31 12:24:08 PM PDT 24
Peak memory 201664 kb
Host smart-be604a35-3c86-43bc-9ae6-41f41ccf34ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371002980 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2371002980
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2097192514
Short name T839
Test name
Test status
Simulation time 483655458 ps
CPU time 0.98 seconds
Started Mar 31 12:24:14 PM PDT 24
Finished Mar 31 12:24:16 PM PDT 24
Peak memory 201576 kb
Host smart-04cd59a8-96df-4db0-9023-7611368b7e80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097192514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2097192514
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.523933736
Short name T900
Test name
Test status
Simulation time 436563841 ps
CPU time 1.01 seconds
Started Mar 31 12:23:57 PM PDT 24
Finished Mar 31 12:23:58 PM PDT 24
Peak memory 201916 kb
Host smart-14ca1e38-e43d-4470-ae22-297757509d65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523933736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.523933736
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3981249449
Short name T875
Test name
Test status
Simulation time 2280738523 ps
CPU time 5.15 seconds
Started Mar 31 12:24:02 PM PDT 24
Finished Mar 31 12:24:08 PM PDT 24
Peak memory 201624 kb
Host smart-cf787fd9-5c79-4084-8860-ee07c943c5fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981249449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.3981249449
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3784487682
Short name T832
Test name
Test status
Simulation time 462918717 ps
CPU time 1.59 seconds
Started Mar 31 12:24:11 PM PDT 24
Finished Mar 31 12:24:13 PM PDT 24
Peak memory 201876 kb
Host smart-ad29fe95-5c86-4568-8709-1d67e2f9ab26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784487682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3784487682
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1862769408
Short name T860
Test name
Test status
Simulation time 7861289598 ps
CPU time 19.84 seconds
Started Mar 31 12:24:06 PM PDT 24
Finished Mar 31 12:24:26 PM PDT 24
Peak memory 201808 kb
Host smart-fa446542-712e-4a70-aaf6-86cc4b2d8e82
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862769408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.1862769408
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3834043268
Short name T908
Test name
Test status
Simulation time 799155483 ps
CPU time 2 seconds
Started Mar 31 12:24:04 PM PDT 24
Finished Mar 31 12:24:06 PM PDT 24
Peak memory 202020 kb
Host smart-6a2098b8-e1c2-435c-ba5e-3c79149a2e01
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834043268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3834043268
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.2336039937
Short name T837
Test name
Test status
Simulation time 54093982969 ps
CPU time 35.94 seconds
Started Mar 31 12:24:14 PM PDT 24
Finished Mar 31 12:24:51 PM PDT 24
Peak memory 201860 kb
Host smart-37fbb8ab-96a7-410a-878e-edc7f2ee4160
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336039937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.2336039937
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2040549011
Short name T125
Test name
Test status
Simulation time 540935555 ps
CPU time 1.92 seconds
Started Mar 31 12:24:03 PM PDT 24
Finished Mar 31 12:24:05 PM PDT 24
Peak memory 201560 kb
Host smart-2c92554d-fc9d-4cc4-af08-482c4ba689a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040549011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2040549011
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2004542868
Short name T89
Test name
Test status
Simulation time 566803608 ps
CPU time 2.26 seconds
Started Mar 31 12:24:04 PM PDT 24
Finished Mar 31 12:24:06 PM PDT 24
Peak memory 201636 kb
Host smart-b6fd89b8-433a-4c57-a22c-dd504a81505f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004542868 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.2004542868
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2016897228
Short name T818
Test name
Test status
Simulation time 353996217 ps
CPU time 0.92 seconds
Started Mar 31 12:24:07 PM PDT 24
Finished Mar 31 12:24:08 PM PDT 24
Peak memory 201604 kb
Host smart-8eb3efa0-6ebe-46c2-90b0-49282b96feab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016897228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2016897228
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.115971751
Short name T861
Test name
Test status
Simulation time 367281984 ps
CPU time 1.48 seconds
Started Mar 31 12:24:01 PM PDT 24
Finished Mar 31 12:24:03 PM PDT 24
Peak memory 201600 kb
Host smart-114696a5-0ee5-47c0-b4df-4e6e03553200
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115971751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.115971751
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2677888410
Short name T877
Test name
Test status
Simulation time 508718468 ps
CPU time 3.27 seconds
Started Mar 31 12:24:12 PM PDT 24
Finished Mar 31 12:24:15 PM PDT 24
Peak memory 201848 kb
Host smart-84e31f9b-1b21-43cd-b84c-4c56b5562108
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677888410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2677888410
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.542524739
Short name T872
Test name
Test status
Simulation time 574560271 ps
CPU time 1.3 seconds
Started Mar 31 12:24:21 PM PDT 24
Finished Mar 31 12:24:23 PM PDT 24
Peak memory 201632 kb
Host smart-02f7a2a6-4822-40be-9189-316d813e5b8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542524739 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.542524739
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1069171640
Short name T805
Test name
Test status
Simulation time 396191880 ps
CPU time 1.13 seconds
Started Mar 31 12:24:12 PM PDT 24
Finished Mar 31 12:24:14 PM PDT 24
Peak memory 201564 kb
Host smart-eb53f944-c3de-4b20-b80a-6df8510a7ef4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069171640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1069171640
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1984643528
Short name T68
Test name
Test status
Simulation time 4424990940 ps
CPU time 18.49 seconds
Started Mar 31 12:24:03 PM PDT 24
Finished Mar 31 12:24:22 PM PDT 24
Peak memory 201852 kb
Host smart-c2f5a3c3-0c64-400a-809e-a50235d52998
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984643528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.1984643528
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1032348613
Short name T827
Test name
Test status
Simulation time 401395887 ps
CPU time 2.35 seconds
Started Mar 31 12:24:08 PM PDT 24
Finished Mar 31 12:24:10 PM PDT 24
Peak memory 201804 kb
Host smart-8c3eff4c-b7ed-410d-a41a-05ba8096af81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032348613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1032348613
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1286743468
Short name T859
Test name
Test status
Simulation time 519856563 ps
CPU time 1.35 seconds
Started Mar 31 12:24:12 PM PDT 24
Finished Mar 31 12:24:14 PM PDT 24
Peak memory 201636 kb
Host smart-d29cd576-45ae-4faa-8eac-bc227173fd97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286743468 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1286743468
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.4012235043
Short name T816
Test name
Test status
Simulation time 525259848 ps
CPU time 1.13 seconds
Started Mar 31 12:24:08 PM PDT 24
Finished Mar 31 12:24:09 PM PDT 24
Peak memory 201568 kb
Host smart-2c96fb01-eb26-4a2f-b5a1-e86c9061af63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012235043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.4012235043
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.3014614524
Short name T817
Test name
Test status
Simulation time 518063125 ps
CPU time 2.02 seconds
Started Mar 31 12:24:09 PM PDT 24
Finished Mar 31 12:24:11 PM PDT 24
Peak memory 201560 kb
Host smart-d8454453-b9a5-4945-ac90-8387d4aac400
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014614524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.3014614524
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2373638879
Short name T129
Test name
Test status
Simulation time 4223523797 ps
CPU time 4.75 seconds
Started Mar 31 12:24:03 PM PDT 24
Finished Mar 31 12:24:08 PM PDT 24
Peak memory 201816 kb
Host smart-dad1f600-022e-4c11-b45e-5f110b5c9f58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373638879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2373638879
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1584766502
Short name T824
Test name
Test status
Simulation time 742535079 ps
CPU time 3.21 seconds
Started Mar 31 12:24:16 PM PDT 24
Finished Mar 31 12:24:20 PM PDT 24
Peak memory 201784 kb
Host smart-22b57664-6e6e-4e65-a35f-2392d0341877
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584766502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1584766502
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2126868650
Short name T74
Test name
Test status
Simulation time 4443342164 ps
CPU time 6.97 seconds
Started Mar 31 12:24:09 PM PDT 24
Finished Mar 31 12:24:16 PM PDT 24
Peak memory 201852 kb
Host smart-72347f07-6881-4a3f-a4c0-5558343133d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126868650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2126868650
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.396911478
Short name T863
Test name
Test status
Simulation time 613040013 ps
CPU time 1.41 seconds
Started Mar 31 12:24:14 PM PDT 24
Finished Mar 31 12:24:17 PM PDT 24
Peak memory 201624 kb
Host smart-670cccd6-0564-4123-befb-703a72a3b145
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396911478 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.396911478
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.487154244
Short name T123
Test name
Test status
Simulation time 324342895 ps
CPU time 1.12 seconds
Started Mar 31 12:24:05 PM PDT 24
Finished Mar 31 12:24:06 PM PDT 24
Peak memory 201548 kb
Host smart-b5e9def5-e677-4583-9789-80357b7021d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487154244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.487154244
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2568456682
Short name T819
Test name
Test status
Simulation time 437468235 ps
CPU time 1.72 seconds
Started Mar 31 12:24:07 PM PDT 24
Finished Mar 31 12:24:08 PM PDT 24
Peak memory 201568 kb
Host smart-c856b3f5-d4df-47bc-b319-c90919568090
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568456682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.2568456682
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3380125911
Short name T130
Test name
Test status
Simulation time 4890349906 ps
CPU time 17.65 seconds
Started Mar 31 12:24:08 PM PDT 24
Finished Mar 31 12:24:26 PM PDT 24
Peak memory 201804 kb
Host smart-e9b8489d-bb34-4bc3-974d-faaf6bc0ef60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380125911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3380125911
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.1559656897
Short name T83
Test name
Test status
Simulation time 451548920 ps
CPU time 3.1 seconds
Started Mar 31 12:24:10 PM PDT 24
Finished Mar 31 12:24:14 PM PDT 24
Peak memory 218036 kb
Host smart-0337cda5-0692-4b77-819e-05e6873cbe7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559656897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.1559656897
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.504085466
Short name T325
Test name
Test status
Simulation time 4528201410 ps
CPU time 4.31 seconds
Started Mar 31 12:24:06 PM PDT 24
Finished Mar 31 12:24:10 PM PDT 24
Peak memory 201840 kb
Host smart-13feb297-c310-4b78-983d-b436fb4f63fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504085466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_in
tg_err.504085466
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1709847169
Short name T905
Test name
Test status
Simulation time 485430689 ps
CPU time 1.07 seconds
Started Mar 31 12:24:10 PM PDT 24
Finished Mar 31 12:24:12 PM PDT 24
Peak memory 201592 kb
Host smart-cc8c8d2e-520b-4c35-9d3c-496e4349747d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709847169 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.1709847169
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.4009606428
Short name T836
Test name
Test status
Simulation time 425429254 ps
CPU time 1.42 seconds
Started Mar 31 12:24:18 PM PDT 24
Finished Mar 31 12:24:21 PM PDT 24
Peak memory 201556 kb
Host smart-c719d8bd-b54d-4aca-845f-2af63845154e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009606428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.4009606428
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.1660874052
Short name T802
Test name
Test status
Simulation time 417464947 ps
CPU time 1.62 seconds
Started Mar 31 12:24:19 PM PDT 24
Finished Mar 31 12:24:22 PM PDT 24
Peak memory 201560 kb
Host smart-d9762b01-6677-40ce-9fca-6bd0fd9d0385
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660874052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.1660874052
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.4022024872
Short name T842
Test name
Test status
Simulation time 5166500200 ps
CPU time 12.15 seconds
Started Mar 31 12:24:17 PM PDT 24
Finished Mar 31 12:24:31 PM PDT 24
Peak memory 201916 kb
Host smart-5b76e123-6223-43cf-9716-965c93368933
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022024872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.4022024872
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3688575170
Short name T854
Test name
Test status
Simulation time 590523383 ps
CPU time 3.75 seconds
Started Mar 31 12:24:04 PM PDT 24
Finished Mar 31 12:24:08 PM PDT 24
Peak memory 217816 kb
Host smart-59e29207-c392-44d5-89cc-b0324eb1d877
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688575170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3688575170
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.4181071832
Short name T876
Test name
Test status
Simulation time 8363546361 ps
CPU time 20.5 seconds
Started Mar 31 12:24:09 PM PDT 24
Finished Mar 31 12:24:30 PM PDT 24
Peak memory 201848 kb
Host smart-07e08367-775d-41df-906b-e4712df0788c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181071832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.4181071832
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.2197592724
Short name T848
Test name
Test status
Simulation time 455251919 ps
CPU time 1.31 seconds
Started Mar 31 12:24:17 PM PDT 24
Finished Mar 31 12:24:24 PM PDT 24
Peak memory 201636 kb
Host smart-c2a6e3e1-b85f-4fe6-b18f-72e49ff25805
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197592724 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.2197592724
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1624700418
Short name T117
Test name
Test status
Simulation time 404207610 ps
CPU time 1.57 seconds
Started Mar 31 12:24:18 PM PDT 24
Finished Mar 31 12:24:30 PM PDT 24
Peak memory 201592 kb
Host smart-01ba943b-210a-4dea-ad2e-7d53662648fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624700418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1624700418
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1056477154
Short name T849
Test name
Test status
Simulation time 340631834 ps
CPU time 1.36 seconds
Started Mar 31 12:24:19 PM PDT 24
Finished Mar 31 12:24:22 PM PDT 24
Peak memory 201560 kb
Host smart-f0f2f842-42e3-49c5-b33a-5b520d54661e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056477154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1056477154
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.3005622284
Short name T815
Test name
Test status
Simulation time 5058671263 ps
CPU time 12.46 seconds
Started Mar 31 12:24:08 PM PDT 24
Finished Mar 31 12:24:20 PM PDT 24
Peak memory 201804 kb
Host smart-20245d21-3df4-4341-b04a-dcb770cef833
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005622284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.3005622284
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2303049763
Short name T820
Test name
Test status
Simulation time 419286512 ps
CPU time 2.6 seconds
Started Mar 31 12:24:20 PM PDT 24
Finished Mar 31 12:24:23 PM PDT 24
Peak memory 201868 kb
Host smart-636c5815-b9d6-43c4-bdf8-b596dcdb8a58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303049763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2303049763
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.668872152
Short name T920
Test name
Test status
Simulation time 7983430120 ps
CPU time 9 seconds
Started Mar 31 12:24:06 PM PDT 24
Finished Mar 31 12:24:15 PM PDT 24
Peak memory 201832 kb
Host smart-e3a3b9dc-9a40-4722-8ffd-b81079e519bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668872152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_in
tg_err.668872152
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.591034171
Short name T899
Test name
Test status
Simulation time 573075644 ps
CPU time 2.04 seconds
Started Mar 31 12:24:07 PM PDT 24
Finished Mar 31 12:24:09 PM PDT 24
Peak memory 201648 kb
Host smart-578e499e-e39c-491b-9041-6238eb3a4b9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591034171 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.591034171
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.464445571
Short name T118
Test name
Test status
Simulation time 447235958 ps
CPU time 0.96 seconds
Started Mar 31 12:24:08 PM PDT 24
Finished Mar 31 12:24:09 PM PDT 24
Peak memory 201580 kb
Host smart-13542fc2-a444-475e-88f8-765d85eae20b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464445571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.464445571
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3069233649
Short name T810
Test name
Test status
Simulation time 430444153 ps
CPU time 0.69 seconds
Started Mar 31 12:24:03 PM PDT 24
Finished Mar 31 12:24:04 PM PDT 24
Peak memory 201536 kb
Host smart-90839ba2-f484-49ac-b4ae-7f7e953a342e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069233649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3069233649
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1214795400
Short name T825
Test name
Test status
Simulation time 2521551504 ps
CPU time 5.73 seconds
Started Mar 31 12:24:16 PM PDT 24
Finished Mar 31 12:24:25 PM PDT 24
Peak memory 201660 kb
Host smart-254ebbda-7e18-40f8-b15e-cf705e9486b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214795400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1214795400
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1716425674
Short name T830
Test name
Test status
Simulation time 356978679 ps
CPU time 2.07 seconds
Started Mar 31 12:24:10 PM PDT 24
Finished Mar 31 12:24:12 PM PDT 24
Peak memory 202156 kb
Host smart-aae39d32-a77d-4454-95b6-0aaa8893e0c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716425674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1716425674
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.2007339332
Short name T323
Test name
Test status
Simulation time 8666550373 ps
CPU time 7.35 seconds
Started Mar 31 12:24:08 PM PDT 24
Finished Mar 31 12:24:16 PM PDT 24
Peak memory 201780 kb
Host smart-4b175f46-435f-4876-b6b4-fd2b536c0775
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007339332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.2007339332
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.99830465
Short name T76
Test name
Test status
Simulation time 853603566 ps
CPU time 1.17 seconds
Started Mar 31 12:23:56 PM PDT 24
Finished Mar 31 12:23:57 PM PDT 24
Peak memory 201536 kb
Host smart-e402ddbd-c128-4606-a30e-d3513a1dfc99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99830465 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.99830465
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2442610635
Short name T902
Test name
Test status
Simulation time 325026057 ps
CPU time 1.6 seconds
Started Mar 31 12:24:16 PM PDT 24
Finished Mar 31 12:24:20 PM PDT 24
Peak memory 201568 kb
Host smart-2ef65eae-792e-4bb0-81f3-9698c13a784d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442610635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2442610635
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2689070060
Short name T889
Test name
Test status
Simulation time 348064284 ps
CPU time 0.82 seconds
Started Mar 31 12:24:10 PM PDT 24
Finished Mar 31 12:24:11 PM PDT 24
Peak memory 201548 kb
Host smart-ace60d60-3b9f-4460-9901-f5fb12e6c76f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689070060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2689070060
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.433138844
Short name T916
Test name
Test status
Simulation time 2411046803 ps
CPU time 11.49 seconds
Started Mar 31 12:24:03 PM PDT 24
Finished Mar 31 12:24:14 PM PDT 24
Peak memory 201656 kb
Host smart-3b9adf1e-8c29-419c-9aa4-081b0d42eeac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433138844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.433138844
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.535351327
Short name T914
Test name
Test status
Simulation time 826712335 ps
CPU time 3.38 seconds
Started Mar 31 12:24:13 PM PDT 24
Finished Mar 31 12:24:18 PM PDT 24
Peak memory 218068 kb
Host smart-690a51d3-ad48-4970-9d61-d8755cd00894
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535351327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.535351327
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2137545864
Short name T909
Test name
Test status
Simulation time 8326343637 ps
CPU time 16.55 seconds
Started Mar 31 12:24:01 PM PDT 24
Finished Mar 31 12:24:17 PM PDT 24
Peak memory 201800 kb
Host smart-3fdd5121-1f5e-4df1-b6ff-5cd40ce661ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137545864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.2137545864
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3551622259
Short name T90
Test name
Test status
Simulation time 540408796 ps
CPU time 1.11 seconds
Started Mar 31 12:24:09 PM PDT 24
Finished Mar 31 12:24:10 PM PDT 24
Peak memory 201672 kb
Host smart-923e10e2-7bad-4c94-9245-eec8beebaea3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551622259 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3551622259
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.592635383
Short name T831
Test name
Test status
Simulation time 544141710 ps
CPU time 1.01 seconds
Started Mar 31 12:24:11 PM PDT 24
Finished Mar 31 12:24:12 PM PDT 24
Peak memory 201576 kb
Host smart-9f9a82d2-91e6-47e9-8b77-b825a498f12b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592635383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.592635383
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.4026623570
Short name T884
Test name
Test status
Simulation time 371103560 ps
CPU time 0.7 seconds
Started Mar 31 12:24:05 PM PDT 24
Finished Mar 31 12:24:06 PM PDT 24
Peak memory 201596 kb
Host smart-f1c2ccca-f443-4f4f-a2bb-196b36425c8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026623570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.4026623570
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2358675819
Short name T885
Test name
Test status
Simulation time 2646166695 ps
CPU time 2.26 seconds
Started Mar 31 12:24:17 PM PDT 24
Finished Mar 31 12:24:21 PM PDT 24
Peak memory 201652 kb
Host smart-b0aaa969-f626-46ef-b112-341df8b0fab4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358675819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.2358675819
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3186424908
Short name T886
Test name
Test status
Simulation time 452158111 ps
CPU time 2.04 seconds
Started Mar 31 12:24:10 PM PDT 24
Finished Mar 31 12:24:12 PM PDT 24
Peak memory 201804 kb
Host smart-7ad0dceb-c7fa-4192-9971-6ee0c63a459f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186424908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3186424908
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3803387633
Short name T869
Test name
Test status
Simulation time 4659301366 ps
CPU time 7.18 seconds
Started Mar 31 12:24:15 PM PDT 24
Finished Mar 31 12:24:24 PM PDT 24
Peak memory 201872 kb
Host smart-e94c2da7-b407-4097-9f08-116a8e4884df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803387633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3803387633
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.386227886
Short name T77
Test name
Test status
Simulation time 605595225 ps
CPU time 2.32 seconds
Started Mar 31 12:24:31 PM PDT 24
Finished Mar 31 12:24:33 PM PDT 24
Peak memory 201644 kb
Host smart-8db24055-78c9-4858-a191-0b0d08cb5f1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386227886 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.386227886
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.2435746205
Short name T127
Test name
Test status
Simulation time 369286935 ps
CPU time 1.14 seconds
Started Mar 31 12:24:11 PM PDT 24
Finished Mar 31 12:24:12 PM PDT 24
Peak memory 201568 kb
Host smart-2a2a965f-b5a3-49de-97b0-12a269ce20bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435746205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.2435746205
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.891242576
Short name T910
Test name
Test status
Simulation time 532922146 ps
CPU time 1.01 seconds
Started Mar 31 12:24:10 PM PDT 24
Finished Mar 31 12:24:11 PM PDT 24
Peak memory 201544 kb
Host smart-14aaa920-042d-4b98-a1fb-77086d306eab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891242576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.891242576
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.4245141661
Short name T919
Test name
Test status
Simulation time 2397770641 ps
CPU time 2.27 seconds
Started Mar 31 12:24:31 PM PDT 24
Finished Mar 31 12:24:33 PM PDT 24
Peak memory 201232 kb
Host smart-291206c5-922a-4a4c-94b7-9225299f2d1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245141661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.4245141661
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.3343147560
Short name T823
Test name
Test status
Simulation time 369852862 ps
CPU time 2.18 seconds
Started Mar 31 12:24:15 PM PDT 24
Finished Mar 31 12:24:19 PM PDT 24
Peak memory 201828 kb
Host smart-d821252c-0d1d-4d64-acc1-8f2907f81b47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343147560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.3343147560
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1193791687
Short name T91
Test name
Test status
Simulation time 8019951530 ps
CPU time 7.03 seconds
Started Mar 31 12:24:05 PM PDT 24
Finished Mar 31 12:24:12 PM PDT 24
Peak memory 201872 kb
Host smart-8ce02c60-718b-414f-bc89-784a7ee18b21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193791687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1193791687
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.859986923
Short name T852
Test name
Test status
Simulation time 605975919 ps
CPU time 2.28 seconds
Started Mar 31 12:24:15 PM PDT 24
Finished Mar 31 12:24:19 PM PDT 24
Peak memory 201624 kb
Host smart-047aa226-bb82-4216-84b5-df70f7860bb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859986923 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.859986923
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.603241524
Short name T813
Test name
Test status
Simulation time 335251882 ps
CPU time 0.88 seconds
Started Mar 31 12:24:15 PM PDT 24
Finished Mar 31 12:24:17 PM PDT 24
Peak memory 201616 kb
Host smart-c6bc29f3-4276-422f-9944-d493f3869618
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603241524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.603241524
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1133881180
Short name T829
Test name
Test status
Simulation time 446155798 ps
CPU time 0.91 seconds
Started Mar 31 12:24:18 PM PDT 24
Finished Mar 31 12:24:21 PM PDT 24
Peak memory 201548 kb
Host smart-04219b69-a945-44eb-b5a1-61253c562b84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133881180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1133881180
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1184116640
Short name T69
Test name
Test status
Simulation time 1882955832 ps
CPU time 1.53 seconds
Started Mar 31 12:24:12 PM PDT 24
Finished Mar 31 12:24:14 PM PDT 24
Peak memory 201580 kb
Host smart-2d03f417-5702-458c-88c1-2d19a3acf26f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184116640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.1184116640
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2101667136
Short name T897
Test name
Test status
Simulation time 661925004 ps
CPU time 2.05 seconds
Started Mar 31 12:24:14 PM PDT 24
Finished Mar 31 12:24:17 PM PDT 24
Peak memory 201868 kb
Host smart-c8610842-2955-472e-bd81-2deec691fa91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101667136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2101667136
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2157171805
Short name T918
Test name
Test status
Simulation time 8239684405 ps
CPU time 20.87 seconds
Started Mar 31 12:24:19 PM PDT 24
Finished Mar 31 12:24:41 PM PDT 24
Peak memory 201844 kb
Host smart-4edbe240-1ec5-4093-b208-b888ad6a1e75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157171805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2157171805
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2612593399
Short name T856
Test name
Test status
Simulation time 1319372647 ps
CPU time 3.23 seconds
Started Mar 31 12:24:01 PM PDT 24
Finished Mar 31 12:24:05 PM PDT 24
Peak memory 201708 kb
Host smart-559b2755-8c4e-433b-ad73-6356243db020
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612593399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2612593399
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.2089845073
Short name T126
Test name
Test status
Simulation time 29577591083 ps
CPU time 28.05 seconds
Started Mar 31 12:24:11 PM PDT 24
Finished Mar 31 12:24:39 PM PDT 24
Peak memory 201840 kb
Host smart-a19d67a9-372e-4ac2-be3c-dd66c9c3b135
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089845073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.2089845073
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3369455493
Short name T124
Test name
Test status
Simulation time 1086642550 ps
CPU time 1.4 seconds
Started Mar 31 12:24:16 PM PDT 24
Finished Mar 31 12:24:23 PM PDT 24
Peak memory 201524 kb
Host smart-2a791080-9f49-45d4-8aa1-4ee704b7c3f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369455493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3369455493
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1315759420
Short name T865
Test name
Test status
Simulation time 535360617 ps
CPU time 2.04 seconds
Started Mar 31 12:24:03 PM PDT 24
Finished Mar 31 12:24:06 PM PDT 24
Peak memory 201700 kb
Host smart-6e699171-993d-497c-b8ec-fbe5e54955e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315759420 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.1315759420
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.161090214
Short name T128
Test name
Test status
Simulation time 459624286 ps
CPU time 0.96 seconds
Started Mar 31 12:23:58 PM PDT 24
Finished Mar 31 12:23:59 PM PDT 24
Peak memory 201600 kb
Host smart-86296162-8cc3-4f38-9816-413c49bb4dbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161090214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.161090214
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3826720641
Short name T878
Test name
Test status
Simulation time 317122365 ps
CPU time 0.81 seconds
Started Mar 31 12:24:04 PM PDT 24
Finished Mar 31 12:24:05 PM PDT 24
Peak memory 201584 kb
Host smart-3c8a6f45-5d69-4a84-b1d7-dcaa18e0ba80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826720641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3826720641
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.81229592
Short name T826
Test name
Test status
Simulation time 4586704065 ps
CPU time 6.21 seconds
Started Mar 31 12:24:00 PM PDT 24
Finished Mar 31 12:24:07 PM PDT 24
Peak memory 201848 kb
Host smart-e976bd91-0b4e-4bb7-9c56-3ddc3f517c73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81229592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctr
l_same_csr_outstanding.81229592
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.4266274167
Short name T840
Test name
Test status
Simulation time 8344802731 ps
CPU time 6.64 seconds
Started Mar 31 12:24:08 PM PDT 24
Finished Mar 31 12:24:16 PM PDT 24
Peak memory 201960 kb
Host smart-ffb74672-5e41-4eb0-94d8-e1b60a13dc72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266274167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.4266274167
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2064781246
Short name T821
Test name
Test status
Simulation time 506904193 ps
CPU time 0.85 seconds
Started Mar 31 12:24:21 PM PDT 24
Finished Mar 31 12:24:22 PM PDT 24
Peak memory 201592 kb
Host smart-4276626a-a207-4b98-858d-a0fdce71d1e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064781246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2064781246
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2667250815
Short name T801
Test name
Test status
Simulation time 514600614 ps
CPU time 1.54 seconds
Started Mar 31 12:24:14 PM PDT 24
Finished Mar 31 12:24:16 PM PDT 24
Peak memory 201564 kb
Host smart-56f13f6d-e089-4f1d-b770-835db1a14c5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667250815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2667250815
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2027872786
Short name T809
Test name
Test status
Simulation time 298437709 ps
CPU time 0.98 seconds
Started Mar 31 12:24:16 PM PDT 24
Finished Mar 31 12:24:20 PM PDT 24
Peak memory 201580 kb
Host smart-97f275ba-4cc1-47cd-8f3e-d7ad190c4f1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027872786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2027872786
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3598935920
Short name T857
Test name
Test status
Simulation time 373566157 ps
CPU time 0.76 seconds
Started Mar 31 12:24:10 PM PDT 24
Finished Mar 31 12:24:11 PM PDT 24
Peak memory 201644 kb
Host smart-55969ff6-8cf9-425a-af3d-eca7c39f2980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598935920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3598935920
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.3784856419
Short name T890
Test name
Test status
Simulation time 432477359 ps
CPU time 0.87 seconds
Started Mar 31 12:24:17 PM PDT 24
Finished Mar 31 12:24:20 PM PDT 24
Peak memory 201548 kb
Host smart-11c0a5b5-6923-4271-a3b6-cf5243c16aaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784856419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.3784856419
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.2782743762
Short name T846
Test name
Test status
Simulation time 454064711 ps
CPU time 0.9 seconds
Started Mar 31 12:24:16 PM PDT 24
Finished Mar 31 12:24:18 PM PDT 24
Peak memory 201552 kb
Host smart-5d8b3f68-13eb-4002-af05-4191aada04cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782743762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.2782743762
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1958017304
Short name T912
Test name
Test status
Simulation time 430468648 ps
CPU time 0.9 seconds
Started Mar 31 12:24:17 PM PDT 24
Finished Mar 31 12:24:20 PM PDT 24
Peak memory 201596 kb
Host smart-ec4e971c-735b-4b28-8887-3b031a76c57d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958017304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.1958017304
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3490825137
Short name T873
Test name
Test status
Simulation time 322527307 ps
CPU time 0.83 seconds
Started Mar 31 12:24:18 PM PDT 24
Finished Mar 31 12:24:21 PM PDT 24
Peak memory 201584 kb
Host smart-7b9efb81-d882-45c6-bbd8-9a77456638bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490825137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3490825137
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2137706937
Short name T915
Test name
Test status
Simulation time 526983542 ps
CPU time 0.87 seconds
Started Mar 31 12:24:20 PM PDT 24
Finished Mar 31 12:24:22 PM PDT 24
Peak memory 201560 kb
Host smart-ef4bc68e-05c9-4779-ace1-1a1875000ef1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137706937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2137706937
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.2667677891
Short name T868
Test name
Test status
Simulation time 389241717 ps
CPU time 1.49 seconds
Started Mar 31 12:24:22 PM PDT 24
Finished Mar 31 12:24:23 PM PDT 24
Peak memory 201592 kb
Host smart-84abb9d3-6f0a-4b7a-9643-82205b528848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667677891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.2667677891
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.427243009
Short name T855
Test name
Test status
Simulation time 1370414968 ps
CPU time 5.32 seconds
Started Mar 31 12:24:12 PM PDT 24
Finished Mar 31 12:24:17 PM PDT 24
Peak memory 201772 kb
Host smart-1667c960-2943-46bf-bd5a-a7b103de3b8a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427243009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alias
ing.427243009
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2920242635
Short name T122
Test name
Test status
Simulation time 35443647587 ps
CPU time 47.08 seconds
Started Mar 31 12:24:07 PM PDT 24
Finished Mar 31 12:24:54 PM PDT 24
Peak memory 201892 kb
Host smart-b69b9898-b15c-438f-bca2-ec419f1e1192
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920242635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.2920242635
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1438778891
Short name T907
Test name
Test status
Simulation time 1021848258 ps
CPU time 3.33 seconds
Started Mar 31 12:23:57 PM PDT 24
Finished Mar 31 12:24:00 PM PDT 24
Peak memory 201616 kb
Host smart-3a97533b-dc43-41fe-9fd4-ab87885438ec
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438778891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1438778891
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1565817396
Short name T84
Test name
Test status
Simulation time 477588957 ps
CPU time 2.09 seconds
Started Mar 31 12:24:02 PM PDT 24
Finished Mar 31 12:24:04 PM PDT 24
Peak memory 201656 kb
Host smart-b5b77f5f-08ed-4b94-b2c7-a4acdfc4164a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565817396 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.1565817396
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.2333374417
Short name T911
Test name
Test status
Simulation time 504987684 ps
CPU time 1.86 seconds
Started Mar 31 12:24:05 PM PDT 24
Finished Mar 31 12:24:07 PM PDT 24
Peak memory 201580 kb
Host smart-6e42d34d-4703-4288-bb20-d10622f9745a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333374417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.2333374417
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1263693139
Short name T879
Test name
Test status
Simulation time 491057693 ps
CPU time 0.72 seconds
Started Mar 31 12:24:12 PM PDT 24
Finished Mar 31 12:24:19 PM PDT 24
Peak memory 201856 kb
Host smart-05831bea-9a18-4afa-844d-ba795428ea96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263693139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.1263693139
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.594226146
Short name T835
Test name
Test status
Simulation time 4695776701 ps
CPU time 12.09 seconds
Started Mar 31 12:24:06 PM PDT 24
Finished Mar 31 12:24:18 PM PDT 24
Peak memory 201800 kb
Host smart-aa2e3970-eb55-4212-9544-b7f19297edf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594226146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ct
rl_same_csr_outstanding.594226146
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2500175746
Short name T87
Test name
Test status
Simulation time 513795773 ps
CPU time 3.4 seconds
Started Mar 31 12:24:03 PM PDT 24
Finished Mar 31 12:24:06 PM PDT 24
Peak memory 210052 kb
Host smart-f345ce11-22b4-4bef-91a2-b62e17ccb2aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500175746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2500175746
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.142483669
Short name T92
Test name
Test status
Simulation time 8509124738 ps
CPU time 22.1 seconds
Started Mar 31 12:24:16 PM PDT 24
Finished Mar 31 12:24:39 PM PDT 24
Peak memory 201768 kb
Host smart-40c7c175-6819-4614-a2e9-002761f612bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142483669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.142483669
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3949655607
Short name T803
Test name
Test status
Simulation time 412535018 ps
CPU time 1.55 seconds
Started Mar 31 12:24:19 PM PDT 24
Finished Mar 31 12:24:22 PM PDT 24
Peak memory 201556 kb
Host smart-ab6e4107-5453-405c-9a34-fda30ca572ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949655607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3949655607
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1495716337
Short name T828
Test name
Test status
Simulation time 359861756 ps
CPU time 0.85 seconds
Started Mar 31 12:24:14 PM PDT 24
Finished Mar 31 12:24:16 PM PDT 24
Peak memory 201584 kb
Host smart-cc4d2b57-bbfa-4238-b0b2-b73a4b033f75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495716337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1495716337
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2217585600
Short name T894
Test name
Test status
Simulation time 414549465 ps
CPU time 1.1 seconds
Started Mar 31 12:24:18 PM PDT 24
Finished Mar 31 12:24:21 PM PDT 24
Peak memory 201548 kb
Host smart-35b992a5-8ff1-4167-b3a1-cfcf9c1cc800
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217585600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2217585600
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3882370180
Short name T903
Test name
Test status
Simulation time 508321781 ps
CPU time 1.7 seconds
Started Mar 31 12:24:19 PM PDT 24
Finished Mar 31 12:24:21 PM PDT 24
Peak memory 201604 kb
Host smart-3e2be698-86a4-4dab-9c62-ad6caf772d0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882370180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3882370180
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2054644678
Short name T913
Test name
Test status
Simulation time 307750990 ps
CPU time 1.08 seconds
Started Mar 31 12:24:16 PM PDT 24
Finished Mar 31 12:24:19 PM PDT 24
Peak memory 201604 kb
Host smart-07bbfc74-70a0-41d3-a296-b4fa1f523978
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054644678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2054644678
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.4180280623
Short name T841
Test name
Test status
Simulation time 489060395 ps
CPU time 1.43 seconds
Started Mar 31 12:24:16 PM PDT 24
Finished Mar 31 12:24:20 PM PDT 24
Peak memory 201580 kb
Host smart-4153a5d2-20ca-4eaa-b1dc-96b011bbd206
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180280623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.4180280623
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3133259219
Short name T838
Test name
Test status
Simulation time 473958139 ps
CPU time 1.77 seconds
Started Mar 31 12:24:20 PM PDT 24
Finished Mar 31 12:24:23 PM PDT 24
Peak memory 201580 kb
Host smart-eb1b1a61-2d6d-4762-a316-33494ee3dc64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133259219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3133259219
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.761158463
Short name T853
Test name
Test status
Simulation time 396668311 ps
CPU time 1.47 seconds
Started Mar 31 12:24:17 PM PDT 24
Finished Mar 31 12:24:21 PM PDT 24
Peak memory 201572 kb
Host smart-b68835a0-896f-4886-a881-c6d39bd286da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761158463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.761158463
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.4061954832
Short name T808
Test name
Test status
Simulation time 523337924 ps
CPU time 1.87 seconds
Started Mar 31 12:24:13 PM PDT 24
Finished Mar 31 12:24:16 PM PDT 24
Peak memory 201592 kb
Host smart-e6652a0f-c4c1-4513-ac4f-8670dd70280b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061954832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.4061954832
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2097893771
Short name T807
Test name
Test status
Simulation time 371080736 ps
CPU time 1.42 seconds
Started Mar 31 12:24:17 PM PDT 24
Finished Mar 31 12:24:20 PM PDT 24
Peak memory 201580 kb
Host smart-53292bdd-08ad-49b1-b4dd-b06094ef5233
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097893771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2097893771
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2554826383
Short name T116
Test name
Test status
Simulation time 1284553856 ps
CPU time 2.29 seconds
Started Mar 31 12:23:59 PM PDT 24
Finished Mar 31 12:24:02 PM PDT 24
Peak memory 201728 kb
Host smart-d9a495cb-317f-4e93-84ec-c85db53b3b45
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554826383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.2554826383
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1563395513
Short name T119
Test name
Test status
Simulation time 9827444940 ps
CPU time 8.88 seconds
Started Mar 31 12:24:06 PM PDT 24
Finished Mar 31 12:24:14 PM PDT 24
Peak memory 201832 kb
Host smart-248fe1dd-63cf-4c83-bf40-e72914d12881
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563395513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1563395513
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.256461032
Short name T858
Test name
Test status
Simulation time 1120022981 ps
CPU time 1.46 seconds
Started Mar 31 12:24:11 PM PDT 24
Finished Mar 31 12:24:13 PM PDT 24
Peak memory 201548 kb
Host smart-31de0953-e5b5-4c17-8ab4-273f5ab1f200
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256461032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_re
set.256461032
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.3150133280
Short name T844
Test name
Test status
Simulation time 793700665 ps
CPU time 1.08 seconds
Started Mar 31 12:24:15 PM PDT 24
Finished Mar 31 12:24:16 PM PDT 24
Peak memory 201592 kb
Host smart-8545e076-3abb-46a5-92d8-1494d7a7a40e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150133280 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.3150133280
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1347393737
Short name T882
Test name
Test status
Simulation time 554838380 ps
CPU time 1.95 seconds
Started Mar 31 12:23:58 PM PDT 24
Finished Mar 31 12:24:00 PM PDT 24
Peak memory 201600 kb
Host smart-c1a8e233-7f58-46eb-8ed9-9848c6a55ec7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347393737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1347393737
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2725131575
Short name T917
Test name
Test status
Simulation time 483010486 ps
CPU time 1.53 seconds
Started Mar 31 12:24:02 PM PDT 24
Finished Mar 31 12:24:03 PM PDT 24
Peak memory 201576 kb
Host smart-458e449e-0ae2-49b0-8b6f-57638d18059a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725131575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2725131575
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1486281577
Short name T822
Test name
Test status
Simulation time 4581288721 ps
CPU time 11.15 seconds
Started Mar 31 12:24:10 PM PDT 24
Finished Mar 31 12:24:21 PM PDT 24
Peak memory 201852 kb
Host smart-14c987db-3d51-403e-8e87-83d0918286a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486281577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1486281577
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.98144853
Short name T871
Test name
Test status
Simulation time 515291790 ps
CPU time 3.67 seconds
Started Mar 31 12:24:09 PM PDT 24
Finished Mar 31 12:24:13 PM PDT 24
Peak memory 201832 kb
Host smart-a5ab40a1-8592-4046-aba7-314f9107a973
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98144853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.98144853
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3320587160
Short name T75
Test name
Test status
Simulation time 9232159732 ps
CPU time 3.88 seconds
Started Mar 31 12:24:01 PM PDT 24
Finished Mar 31 12:24:05 PM PDT 24
Peak memory 201864 kb
Host smart-0df13acd-5f0a-491f-9822-219b398f2a00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320587160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3320587160
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1457632394
Short name T888
Test name
Test status
Simulation time 420966190 ps
CPU time 1.11 seconds
Started Mar 31 12:24:18 PM PDT 24
Finished Mar 31 12:24:21 PM PDT 24
Peak memory 201560 kb
Host smart-ec3c2d95-ab16-4984-aff8-5f03105b13ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457632394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1457632394
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.627898547
Short name T867
Test name
Test status
Simulation time 369800179 ps
CPU time 0.77 seconds
Started Mar 31 12:24:12 PM PDT 24
Finished Mar 31 12:24:13 PM PDT 24
Peak memory 201584 kb
Host smart-3371b59d-c446-4a60-a452-a21ebdfd40ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627898547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.627898547
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2832834187
Short name T883
Test name
Test status
Simulation time 332870980 ps
CPU time 1.4 seconds
Started Mar 31 12:24:24 PM PDT 24
Finished Mar 31 12:24:26 PM PDT 24
Peak memory 201852 kb
Host smart-3d194094-85ba-4cc5-97a6-248964084ba0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832834187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2832834187
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.39044375
Short name T811
Test name
Test status
Simulation time 423852059 ps
CPU time 0.86 seconds
Started Mar 31 12:24:08 PM PDT 24
Finished Mar 31 12:24:09 PM PDT 24
Peak memory 201584 kb
Host smart-55c05fff-c79a-4189-908c-1aeef9d7f51b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39044375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.39044375
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.1568027586
Short name T833
Test name
Test status
Simulation time 541272433 ps
CPU time 1.25 seconds
Started Mar 31 12:24:14 PM PDT 24
Finished Mar 31 12:24:16 PM PDT 24
Peak memory 201916 kb
Host smart-a5a272f9-b8fc-425c-9fe1-07078db56b71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568027586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.1568027586
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3780384753
Short name T874
Test name
Test status
Simulation time 373577358 ps
CPU time 0.82 seconds
Started Mar 31 12:24:20 PM PDT 24
Finished Mar 31 12:24:22 PM PDT 24
Peak memory 201560 kb
Host smart-b2eaeeb8-1664-4a03-8510-cd099d409b2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780384753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.3780384753
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1337606293
Short name T862
Test name
Test status
Simulation time 496044305 ps
CPU time 1.75 seconds
Started Mar 31 12:24:24 PM PDT 24
Finished Mar 31 12:24:26 PM PDT 24
Peak memory 201588 kb
Host smart-076fa1d3-fc4a-4ffb-810c-418b3b490657
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337606293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.1337606293
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.193975179
Short name T881
Test name
Test status
Simulation time 321273249 ps
CPU time 0.85 seconds
Started Mar 31 12:24:06 PM PDT 24
Finished Mar 31 12:24:07 PM PDT 24
Peak memory 201580 kb
Host smart-d561f2af-7fe0-4253-919a-797eac25d6f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193975179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.193975179
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3255943957
Short name T806
Test name
Test status
Simulation time 430540370 ps
CPU time 1.52 seconds
Started Mar 31 12:24:18 PM PDT 24
Finished Mar 31 12:24:21 PM PDT 24
Peak memory 201608 kb
Host smart-527d599c-3d37-4826-9188-5943f196f13c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255943957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3255943957
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2661067694
Short name T851
Test name
Test status
Simulation time 458540294 ps
CPU time 1.16 seconds
Started Mar 31 12:24:17 PM PDT 24
Finished Mar 31 12:24:21 PM PDT 24
Peak memory 201600 kb
Host smart-df12f1a9-36ff-4e44-8a21-6672b808fd7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661067694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2661067694
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2793871587
Short name T78
Test name
Test status
Simulation time 700163554 ps
CPU time 1.38 seconds
Started Mar 31 12:24:10 PM PDT 24
Finished Mar 31 12:24:12 PM PDT 24
Peak memory 201592 kb
Host smart-060d9502-8a5e-4fcb-9646-60334963ac23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793871587 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2793871587
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1527615949
Short name T120
Test name
Test status
Simulation time 465543488 ps
CPU time 1.67 seconds
Started Mar 31 12:24:13 PM PDT 24
Finished Mar 31 12:24:15 PM PDT 24
Peak memory 201600 kb
Host smart-54e6d8ae-9759-4ae9-8c8c-ee8b0401a616
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527615949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.1527615949
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3958486503
Short name T864
Test name
Test status
Simulation time 430514495 ps
CPU time 1.56 seconds
Started Mar 31 12:24:56 PM PDT 24
Finished Mar 31 12:24:58 PM PDT 24
Peak memory 201404 kb
Host smart-3e6ae257-1cd1-4c33-8e87-3b7b7178af75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958486503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3958486503
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3790239113
Short name T893
Test name
Test status
Simulation time 2859113664 ps
CPU time 3.33 seconds
Started Mar 31 12:24:15 PM PDT 24
Finished Mar 31 12:24:19 PM PDT 24
Peak memory 201588 kb
Host smart-68e2d192-707d-48c0-906a-968de67c2a66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790239113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3790239113
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1469358075
Short name T866
Test name
Test status
Simulation time 715716016 ps
CPU time 1.94 seconds
Started Mar 31 12:24:12 PM PDT 24
Finished Mar 31 12:24:14 PM PDT 24
Peak memory 201852 kb
Host smart-42116c1e-c79a-4aa3-9971-6394d4cfd401
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469358075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1469358075
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3784232485
Short name T843
Test name
Test status
Simulation time 4248374328 ps
CPU time 3.87 seconds
Started Mar 31 12:23:58 PM PDT 24
Finished Mar 31 12:24:02 PM PDT 24
Peak memory 201824 kb
Host smart-15f1bdcf-8a7a-4791-a7b6-4450f80fbf56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784232485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3784232485
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1538326586
Short name T812
Test name
Test status
Simulation time 507638994 ps
CPU time 1.32 seconds
Started Mar 31 12:24:03 PM PDT 24
Finished Mar 31 12:24:05 PM PDT 24
Peak memory 201636 kb
Host smart-91feba26-2eae-4339-a7d0-63dc25a578e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538326586 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1538326586
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.2707681637
Short name T115
Test name
Test status
Simulation time 402995983 ps
CPU time 1.23 seconds
Started Mar 31 12:24:15 PM PDT 24
Finished Mar 31 12:24:17 PM PDT 24
Peak memory 201584 kb
Host smart-f53584d9-9491-49d9-a29b-c85f347a8253
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707681637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.2707681637
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3820666015
Short name T804
Test name
Test status
Simulation time 366509320 ps
CPU time 1.07 seconds
Started Mar 31 12:24:54 PM PDT 24
Finished Mar 31 12:24:56 PM PDT 24
Peak memory 200728 kb
Host smart-5c688690-4221-4077-9760-019e883c3809
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820666015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3820666015
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.313954605
Short name T870
Test name
Test status
Simulation time 4468875364 ps
CPU time 5.14 seconds
Started Mar 31 12:24:14 PM PDT 24
Finished Mar 31 12:24:20 PM PDT 24
Peak memory 201864 kb
Host smart-64b1800e-43b5-4ff7-9485-26f9784dd612
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313954605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ct
rl_same_csr_outstanding.313954605
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.547204601
Short name T904
Test name
Test status
Simulation time 595100917 ps
CPU time 2.15 seconds
Started Mar 31 12:23:56 PM PDT 24
Finished Mar 31 12:23:58 PM PDT 24
Peak memory 201836 kb
Host smart-bb7415bf-25e9-424e-9102-ef4b223a56f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547204601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.547204601
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1892914243
Short name T834
Test name
Test status
Simulation time 8696755600 ps
CPU time 13.2 seconds
Started Mar 31 12:24:07 PM PDT 24
Finished Mar 31 12:24:20 PM PDT 24
Peak memory 201864 kb
Host smart-34b254d6-b5c8-493c-8779-c627b48e136a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892914243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1892914243
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.4050859346
Short name T814
Test name
Test status
Simulation time 539355553 ps
CPU time 1.2 seconds
Started Mar 31 12:24:06 PM PDT 24
Finished Mar 31 12:24:07 PM PDT 24
Peak memory 201648 kb
Host smart-b75d7a52-55d6-423f-abdd-e0c766b428a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050859346 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.4050859346
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1025864783
Short name T892
Test name
Test status
Simulation time 378460024 ps
CPU time 0.99 seconds
Started Mar 31 12:24:58 PM PDT 24
Finished Mar 31 12:24:59 PM PDT 24
Peak memory 201584 kb
Host smart-daa87757-c777-4fcd-9c2d-8286b6dcdd10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025864783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1025864783
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2520091039
Short name T901
Test name
Test status
Simulation time 476394573 ps
CPU time 1.73 seconds
Started Mar 31 12:24:59 PM PDT 24
Finished Mar 31 12:25:01 PM PDT 24
Peak memory 201592 kb
Host smart-e8fb8fe9-ed22-48bb-ad0b-78e43913300b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520091039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2520091039
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.982350689
Short name T906
Test name
Test status
Simulation time 4479359626 ps
CPU time 12.06 seconds
Started Mar 31 12:24:00 PM PDT 24
Finished Mar 31 12:24:12 PM PDT 24
Peak memory 201804 kb
Host smart-d0a9e38e-5be3-4d3e-99ce-528a96a4f077
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982350689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ct
rl_same_csr_outstanding.982350689
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.674267301
Short name T86
Test name
Test status
Simulation time 1329447279 ps
CPU time 1.65 seconds
Started Mar 31 12:24:11 PM PDT 24
Finished Mar 31 12:24:13 PM PDT 24
Peak memory 201852 kb
Host smart-3358c46a-f8c4-4794-b8dc-b7c461172aa4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674267301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.674267301
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1166544586
Short name T73
Test name
Test status
Simulation time 4332373880 ps
CPU time 3.85 seconds
Started Mar 31 12:24:58 PM PDT 24
Finished Mar 31 12:25:02 PM PDT 24
Peak memory 201820 kb
Host smart-b01a9cfe-f3e7-49eb-a79f-9d0ee7fea35c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166544586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1166544586
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.153959351
Short name T95
Test name
Test status
Simulation time 330226245 ps
CPU time 1.63 seconds
Started Mar 31 12:24:05 PM PDT 24
Finished Mar 31 12:24:07 PM PDT 24
Peak memory 201620 kb
Host smart-c03ffc01-27d3-4eef-9638-ec5b54235c89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153959351 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.153959351
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.1286380565
Short name T133
Test name
Test status
Simulation time 342351810 ps
CPU time 1.21 seconds
Started Mar 31 12:24:13 PM PDT 24
Finished Mar 31 12:24:15 PM PDT 24
Peak memory 201604 kb
Host smart-f600f471-999a-4d80-b5a2-2222c40e74e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286380565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.1286380565
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.4144221347
Short name T895
Test name
Test status
Simulation time 378500748 ps
CPU time 0.84 seconds
Started Mar 31 12:24:13 PM PDT 24
Finished Mar 31 12:24:15 PM PDT 24
Peak memory 201608 kb
Host smart-2666ba22-f1b4-4531-a5ff-6f4cd917cad5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144221347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.4144221347
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.894211313
Short name T887
Test name
Test status
Simulation time 2415898980 ps
CPU time 3.54 seconds
Started Mar 31 12:24:01 PM PDT 24
Finished Mar 31 12:24:04 PM PDT 24
Peak memory 201628 kb
Host smart-9694ec6d-44a3-47be-849a-c0763368c27f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894211313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ct
rl_same_csr_outstanding.894211313
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2002088731
Short name T891
Test name
Test status
Simulation time 555161360 ps
CPU time 2.01 seconds
Started Mar 31 12:24:58 PM PDT 24
Finished Mar 31 12:25:00 PM PDT 24
Peak memory 201904 kb
Host smart-6970b6dd-84ca-42e7-9bde-ec6360252c41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002088731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2002088731
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.4017067912
Short name T324
Test name
Test status
Simulation time 8341743749 ps
CPU time 21.96 seconds
Started Mar 31 12:24:07 PM PDT 24
Finished Mar 31 12:24:29 PM PDT 24
Peak memory 201812 kb
Host smart-467c5474-6a22-4840-824d-0fe3253c9066
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017067912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.4017067912
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.4207257345
Short name T896
Test name
Test status
Simulation time 753145158 ps
CPU time 1.08 seconds
Started Mar 31 12:24:01 PM PDT 24
Finished Mar 31 12:24:03 PM PDT 24
Peak memory 201656 kb
Host smart-09bb7920-92e3-429b-9c1b-6c5490f3ece5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207257345 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.4207257345
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.936582854
Short name T132
Test name
Test status
Simulation time 329190960 ps
CPU time 1.58 seconds
Started Mar 31 12:24:11 PM PDT 24
Finished Mar 31 12:24:13 PM PDT 24
Peak memory 201560 kb
Host smart-ffb9c93b-8373-4921-a6cd-0e006ed55537
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936582854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.936582854
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.791697672
Short name T845
Test name
Test status
Simulation time 410525131 ps
CPU time 1.01 seconds
Started Mar 31 12:24:17 PM PDT 24
Finished Mar 31 12:24:20 PM PDT 24
Peak memory 201616 kb
Host smart-6ac495da-c881-4b73-83db-ccbcf8ab708e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791697672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.791697672
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.911219802
Short name T70
Test name
Test status
Simulation time 4953082214 ps
CPU time 3.27 seconds
Started Mar 31 12:24:12 PM PDT 24
Finished Mar 31 12:24:15 PM PDT 24
Peak memory 201856 kb
Host smart-234ed055-97e2-4e47-bd3b-8341f6c52158
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911219802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ct
rl_same_csr_outstanding.911219802
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2108041730
Short name T850
Test name
Test status
Simulation time 2177598329 ps
CPU time 2.92 seconds
Started Mar 31 12:24:13 PM PDT 24
Finished Mar 31 12:24:16 PM PDT 24
Peak memory 211180 kb
Host smart-bceb1c5a-4780-45a0-95ee-a733174fa800
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108041730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2108041730
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3100947604
Short name T88
Test name
Test status
Simulation time 8450025260 ps
CPU time 21.93 seconds
Started Mar 31 12:24:05 PM PDT 24
Finished Mar 31 12:24:27 PM PDT 24
Peak memory 201932 kb
Host smart-a241511c-52bc-4dc8-be56-7bd19f3c077f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100947604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3100947604
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1497649942
Short name T782
Test name
Test status
Simulation time 393113375 ps
CPU time 1.49 seconds
Started Mar 31 12:39:52 PM PDT 24
Finished Mar 31 12:39:53 PM PDT 24
Peak memory 201424 kb
Host smart-06ee05a7-3ae0-4a37-abaa-432c9ced53a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497649942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1497649942
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2930800787
Short name T252
Test name
Test status
Simulation time 167430309624 ps
CPU time 62.05 seconds
Started Mar 31 12:39:57 PM PDT 24
Finished Mar 31 12:40:59 PM PDT 24
Peak memory 201812 kb
Host smart-b6ab9566-5010-4baa-920e-cbd986162c73
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930800787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2930800787
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.3458438003
Short name T43
Test name
Test status
Simulation time 576792552934 ps
CPU time 1368.03 seconds
Started Mar 31 12:39:49 PM PDT 24
Finished Mar 31 01:02:38 PM PDT 24
Peak memory 201880 kb
Host smart-00a581a8-5853-4022-9342-5a73dfe33057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458438003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3458438003
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3041438889
Short name T453
Test name
Test status
Simulation time 493515232545 ps
CPU time 902.5 seconds
Started Mar 31 12:39:49 PM PDT 24
Finished Mar 31 12:54:51 PM PDT 24
Peak memory 201852 kb
Host smart-d41cbb94-a4c6-4502-866e-740178c13e2f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041438889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.3041438889
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2508959295
Short name T613
Test name
Test status
Simulation time 325326322351 ps
CPU time 389.67 seconds
Started Mar 31 12:39:50 PM PDT 24
Finished Mar 31 12:46:20 PM PDT 24
Peak memory 201896 kb
Host smart-4cbf0792-41c2-443b-b4bd-bf4c03c59f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508959295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2508959295
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.4149145713
Short name T441
Test name
Test status
Simulation time 166198924251 ps
CPU time 368.81 seconds
Started Mar 31 12:39:55 PM PDT 24
Finished Mar 31 12:46:04 PM PDT 24
Peak memory 201816 kb
Host smart-9b3518be-cfea-4cbb-92a7-5c21794dbd91
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149145713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.4149145713
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.2416486921
Short name T310
Test name
Test status
Simulation time 366673686897 ps
CPU time 173.97 seconds
Started Mar 31 12:39:58 PM PDT 24
Finished Mar 31 12:42:52 PM PDT 24
Peak memory 201880 kb
Host smart-1f73b63f-33cc-4f36-b033-db3c16e176d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416486921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.2416486921
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.648705977
Short name T515
Test name
Test status
Simulation time 397832694640 ps
CPU time 108.92 seconds
Started Mar 31 12:39:54 PM PDT 24
Finished Mar 31 12:41:43 PM PDT 24
Peak memory 202044 kb
Host smart-38642f3e-c3cf-4ba0-899b-fbfc6d490d13
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648705977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.a
dc_ctrl_filters_wakeup_fixed.648705977
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2980105411
Short name T456
Test name
Test status
Simulation time 63863430446 ps
CPU time 365.66 seconds
Started Mar 31 12:39:51 PM PDT 24
Finished Mar 31 12:45:57 PM PDT 24
Peak memory 202248 kb
Host smart-2bb4ef13-493c-4664-9943-f134ad9d6960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980105411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2980105411
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3523159810
Short name T470
Test name
Test status
Simulation time 26819842624 ps
CPU time 16.04 seconds
Started Mar 31 12:39:53 PM PDT 24
Finished Mar 31 12:40:09 PM PDT 24
Peak memory 201520 kb
Host smart-d15c525d-eb03-4eb4-a0bd-b39602d73ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523159810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3523159810
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.775462736
Short name T399
Test name
Test status
Simulation time 4279391334 ps
CPU time 10.04 seconds
Started Mar 31 12:39:55 PM PDT 24
Finished Mar 31 12:40:05 PM PDT 24
Peak memory 201620 kb
Host smart-d100f250-bc65-4ce2-a563-0d024c8faa03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775462736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.775462736
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1615407671
Short name T94
Test name
Test status
Simulation time 8261617922 ps
CPU time 5.04 seconds
Started Mar 31 12:39:52 PM PDT 24
Finished Mar 31 12:39:57 PM PDT 24
Peak memory 218484 kb
Host smart-93bb1b1c-85f2-4060-ad35-25dc55d6724a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615407671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1615407671
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.841546496
Short name T372
Test name
Test status
Simulation time 5676362875 ps
CPU time 2.07 seconds
Started Mar 31 12:39:53 PM PDT 24
Finished Mar 31 12:39:56 PM PDT 24
Peak memory 201552 kb
Host smart-01e54398-bb00-45e2-a4e7-2d0b7ea7df1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841546496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.841546496
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2805342682
Short name T39
Test name
Test status
Simulation time 373118405797 ps
CPU time 852.1 seconds
Started Mar 31 12:40:00 PM PDT 24
Finished Mar 31 12:54:12 PM PDT 24
Peak memory 202084 kb
Host smart-62e17b8a-c749-48cb-8b49-3eeb2c0bec8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805342682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2805342682
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.3774717230
Short name T724
Test name
Test status
Simulation time 67141330495 ps
CPU time 145.74 seconds
Started Mar 31 12:39:58 PM PDT 24
Finished Mar 31 12:42:24 PM PDT 24
Peak memory 210288 kb
Host smart-a3a89e85-831d-4535-baa3-e30ddda7ef21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774717230 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.3774717230
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3564663295
Short name T448
Test name
Test status
Simulation time 547434063 ps
CPU time 0.95 seconds
Started Mar 31 12:39:59 PM PDT 24
Finished Mar 31 12:40:00 PM PDT 24
Peak memory 201580 kb
Host smart-a5dc9dd0-5e30-42df-8b9d-946ffcaaded5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564663295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3564663295
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.4119652886
Short name T222
Test name
Test status
Simulation time 351242381188 ps
CPU time 172.1 seconds
Started Mar 31 12:40:02 PM PDT 24
Finished Mar 31 12:42:55 PM PDT 24
Peak memory 201796 kb
Host smart-5b5ec932-c4b9-4646-8ec9-e3a69e59225b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119652886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.4119652886
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1483898945
Short name T231
Test name
Test status
Simulation time 484985503218 ps
CPU time 1045.47 seconds
Started Mar 31 12:40:03 PM PDT 24
Finished Mar 31 12:57:28 PM PDT 24
Peak memory 201880 kb
Host smart-cc213ef7-7821-42ba-951e-fca3472f0803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483898945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1483898945
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1410985535
Short name T341
Test name
Test status
Simulation time 164916445860 ps
CPU time 368.86 seconds
Started Mar 31 12:40:02 PM PDT 24
Finished Mar 31 12:46:11 PM PDT 24
Peak memory 201912 kb
Host smart-755ec469-9489-4e6f-a21e-6d96704dd58e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410985535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1410985535
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2446044989
Short name T168
Test name
Test status
Simulation time 499481546677 ps
CPU time 288.98 seconds
Started Mar 31 12:39:58 PM PDT 24
Finished Mar 31 12:44:47 PM PDT 24
Peak memory 201832 kb
Host smart-e20aae40-cbbe-493a-8350-493fcde50eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446044989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2446044989
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1461305900
Short name T400
Test name
Test status
Simulation time 333524753821 ps
CPU time 429.13 seconds
Started Mar 31 12:39:58 PM PDT 24
Finished Mar 31 12:47:07 PM PDT 24
Peak memory 201812 kb
Host smart-84d4e30d-4c0c-4480-8bfb-c96fe77a1dfe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461305900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1461305900
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.1710875687
Short name T800
Test name
Test status
Simulation time 363236927958 ps
CPU time 227.8 seconds
Started Mar 31 12:40:05 PM PDT 24
Finished Mar 31 12:43:53 PM PDT 24
Peak memory 201964 kb
Host smart-6a0376fc-37df-4796-9a9a-9ed5e4fd2eb8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710875687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.1710875687
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.928052565
Short name T525
Test name
Test status
Simulation time 400620933651 ps
CPU time 213.34 seconds
Started Mar 31 12:40:06 PM PDT 24
Finished Mar 31 12:43:40 PM PDT 24
Peak memory 201784 kb
Host smart-57cef47b-e135-444f-83f3-a12a0c272daa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928052565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.a
dc_ctrl_filters_wakeup_fixed.928052565
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.931442004
Short name T726
Test name
Test status
Simulation time 138508535740 ps
CPU time 491.41 seconds
Started Mar 31 12:39:59 PM PDT 24
Finished Mar 31 12:48:11 PM PDT 24
Peak memory 202180 kb
Host smart-1a61d53c-b262-4580-a47e-afbc83530757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931442004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.931442004
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1199116849
Short name T588
Test name
Test status
Simulation time 24641895057 ps
CPU time 15.79 seconds
Started Mar 31 12:40:12 PM PDT 24
Finished Mar 31 12:40:28 PM PDT 24
Peak memory 201616 kb
Host smart-5d9c3ef3-dc56-43d2-a453-033c24eae3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199116849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1199116849
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.576153630
Short name T600
Test name
Test status
Simulation time 3177415399 ps
CPU time 4.3 seconds
Started Mar 31 12:40:04 PM PDT 24
Finished Mar 31 12:40:09 PM PDT 24
Peak memory 201620 kb
Host smart-c9296734-2893-4e12-bda0-55328523c7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576153630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.576153630
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.20632086
Short name T467
Test name
Test status
Simulation time 5672880100 ps
CPU time 1.83 seconds
Started Mar 31 12:40:03 PM PDT 24
Finished Mar 31 12:40:05 PM PDT 24
Peak memory 201608 kb
Host smart-718a3248-6e64-4655-858d-e1ada6cf74b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20632086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.20632086
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.906043264
Short name T706
Test name
Test status
Simulation time 388573809255 ps
CPU time 229.19 seconds
Started Mar 31 12:40:06 PM PDT 24
Finished Mar 31 12:43:56 PM PDT 24
Peak memory 201792 kb
Host smart-cdc43f4b-90d3-4bec-b3ca-d89e6424ad37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906043264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.906043264
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.894196195
Short name T589
Test name
Test status
Simulation time 86151967613 ps
CPU time 147.1 seconds
Started Mar 31 12:40:01 PM PDT 24
Finished Mar 31 12:42:29 PM PDT 24
Peak memory 210500 kb
Host smart-b79f6bf0-51ca-47cc-a0a0-92b2d326abac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894196195 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.894196195
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.4112744533
Short name T636
Test name
Test status
Simulation time 446008533 ps
CPU time 1.78 seconds
Started Mar 31 12:40:13 PM PDT 24
Finished Mar 31 12:40:16 PM PDT 24
Peak memory 201568 kb
Host smart-e0b584e5-20b6-44ec-a404-c2aae405d2c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112744533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.4112744533
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.2547189906
Short name T134
Test name
Test status
Simulation time 342805295354 ps
CPU time 589.93 seconds
Started Mar 31 12:40:15 PM PDT 24
Finished Mar 31 12:50:06 PM PDT 24
Peak memory 201488 kb
Host smart-b33ee7c7-a541-4f61-b3d7-825d53b52e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547189906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.2547189906
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.224428035
Short name T461
Test name
Test status
Simulation time 164352637666 ps
CPU time 360.75 seconds
Started Mar 31 12:40:02 PM PDT 24
Finished Mar 31 12:46:04 PM PDT 24
Peak memory 201860 kb
Host smart-d9f19664-ba71-4cba-9bf1-b5d2574a57ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224428035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.224428035
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3497842024
Short name T11
Test name
Test status
Simulation time 331868588823 ps
CPU time 573.44 seconds
Started Mar 31 12:40:01 PM PDT 24
Finished Mar 31 12:49:35 PM PDT 24
Peak memory 202116 kb
Host smart-64eadb73-2a4e-4d0a-b7b7-5dc3730b9432
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497842024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.3497842024
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2782213049
Short name T366
Test name
Test status
Simulation time 163536718331 ps
CPU time 53.08 seconds
Started Mar 31 12:40:01 PM PDT 24
Finished Mar 31 12:40:55 PM PDT 24
Peak memory 201816 kb
Host smart-aa08d98f-7461-4959-b132-bfac3c5573ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782213049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2782213049
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.2875391543
Short name T569
Test name
Test status
Simulation time 492417055162 ps
CPU time 320.77 seconds
Started Mar 31 12:40:06 PM PDT 24
Finished Mar 31 12:45:28 PM PDT 24
Peak memory 202056 kb
Host smart-97290a8b-33bc-4356-b336-ac67147c21bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875391543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.2875391543
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.2700513467
Short name T638
Test name
Test status
Simulation time 193998477118 ps
CPU time 188 seconds
Started Mar 31 12:40:09 PM PDT 24
Finished Mar 31 12:43:18 PM PDT 24
Peak memory 201904 kb
Host smart-79ec9025-4252-4a8f-a97a-c91dfc78a68e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700513467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.2700513467
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.1893533024
Short name T395
Test name
Test status
Simulation time 408631560229 ps
CPU time 210.64 seconds
Started Mar 31 12:40:00 PM PDT 24
Finished Mar 31 12:43:31 PM PDT 24
Peak memory 201824 kb
Host smart-a80dc7a7-9e65-4bdf-b95e-5aa56c7b44ed
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893533024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.1893533024
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1416285917
Short name T592
Test name
Test status
Simulation time 80595254977 ps
CPU time 414.01 seconds
Started Mar 31 12:40:13 PM PDT 24
Finished Mar 31 12:47:08 PM PDT 24
Peak memory 202244 kb
Host smart-e1e73642-e4a5-476b-837d-cb356c35dfe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416285917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1416285917
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2521279112
Short name T627
Test name
Test status
Simulation time 25544974489 ps
CPU time 55.57 seconds
Started Mar 31 12:40:11 PM PDT 24
Finished Mar 31 12:41:08 PM PDT 24
Peak memory 201688 kb
Host smart-922cfe07-d927-424f-886d-22f16f780f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521279112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2521279112
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2604952650
Short name T359
Test name
Test status
Simulation time 3323913085 ps
CPU time 2.88 seconds
Started Mar 31 12:40:14 PM PDT 24
Finished Mar 31 12:40:17 PM PDT 24
Peak memory 201684 kb
Host smart-859f5341-1e7d-4aba-a24d-cd7108d95adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604952650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2604952650
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.690334168
Short name T414
Test name
Test status
Simulation time 5573231118 ps
CPU time 3.93 seconds
Started Mar 31 12:40:06 PM PDT 24
Finished Mar 31 12:40:10 PM PDT 24
Peak memory 201640 kb
Host smart-e2588f97-58d7-499c-851d-9a6d20b79051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690334168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.690334168
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.2824372964
Short name T639
Test name
Test status
Simulation time 512170236 ps
CPU time 1.8 seconds
Started Mar 31 12:40:15 PM PDT 24
Finished Mar 31 12:40:18 PM PDT 24
Peak memory 201284 kb
Host smart-454d737d-796b-42b7-ac84-5c02d782d5b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824372964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.2824372964
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3893231183
Short name T779
Test name
Test status
Simulation time 168086769221 ps
CPU time 94.35 seconds
Started Mar 31 12:40:18 PM PDT 24
Finished Mar 31 12:41:52 PM PDT 24
Peak memory 201960 kb
Host smart-48d0a8fb-0557-4367-93d8-3fba33d4be7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893231183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3893231183
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1640320207
Short name T98
Test name
Test status
Simulation time 325754454792 ps
CPU time 210.17 seconds
Started Mar 31 12:40:06 PM PDT 24
Finished Mar 31 12:43:37 PM PDT 24
Peak memory 201924 kb
Host smart-236d22e5-127c-4300-b8a0-19ea61483395
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640320207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1640320207
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.2876335235
Short name T492
Test name
Test status
Simulation time 159505065226 ps
CPU time 365.33 seconds
Started Mar 31 12:40:06 PM PDT 24
Finished Mar 31 12:46:11 PM PDT 24
Peak memory 201820 kb
Host smart-64a07272-8006-4d5e-bb81-cb336419455a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876335235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.2876335235
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1110645257
Short name T734
Test name
Test status
Simulation time 483084830488 ps
CPU time 589.12 seconds
Started Mar 31 12:40:03 PM PDT 24
Finished Mar 31 12:49:52 PM PDT 24
Peak memory 201868 kb
Host smart-1b72157d-552b-45eb-8ca7-9d6f78df2173
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110645257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.1110645257
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2925246551
Short name T304
Test name
Test status
Simulation time 566942096679 ps
CPU time 372.63 seconds
Started Mar 31 12:40:03 PM PDT 24
Finished Mar 31 12:46:16 PM PDT 24
Peak memory 201880 kb
Host smart-fcea53de-1a67-4768-9e1d-e48be6884461
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925246551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2925246551
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.2699622065
Short name T370
Test name
Test status
Simulation time 402438278817 ps
CPU time 757.24 seconds
Started Mar 31 12:40:06 PM PDT 24
Finished Mar 31 12:52:44 PM PDT 24
Peak memory 201788 kb
Host smart-9ca17906-293f-4164-83de-68ac33981fce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699622065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.2699622065
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3826986874
Short name T377
Test name
Test status
Simulation time 107616796634 ps
CPU time 363.46 seconds
Started Mar 31 12:40:15 PM PDT 24
Finished Mar 31 12:46:19 PM PDT 24
Peak memory 202136 kb
Host smart-1e9a4f15-648a-4319-af64-cfba2fe6b471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826986874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3826986874
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.1544130551
Short name T623
Test name
Test status
Simulation time 29789608575 ps
CPU time 65.73 seconds
Started Mar 31 12:40:03 PM PDT 24
Finished Mar 31 12:41:09 PM PDT 24
Peak memory 201604 kb
Host smart-7836cdcf-5b63-44fc-ab49-e9a7ca17fb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544130551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.1544130551
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.794425893
Short name T578
Test name
Test status
Simulation time 4069361219 ps
CPU time 3.5 seconds
Started Mar 31 12:40:12 PM PDT 24
Finished Mar 31 12:40:16 PM PDT 24
Peak memory 201664 kb
Host smart-83419363-0496-4439-94a9-3e6f7249d3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794425893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.794425893
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.1731823009
Short name T565
Test name
Test status
Simulation time 5835824614 ps
CPU time 14.31 seconds
Started Mar 31 12:40:12 PM PDT 24
Finished Mar 31 12:40:28 PM PDT 24
Peak memory 201572 kb
Host smart-875fb9c3-4618-4b1a-81f9-ebfb1b3f654e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731823009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.1731823009
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.4144508566
Short name T647
Test name
Test status
Simulation time 111620937277 ps
CPU time 373.56 seconds
Started Mar 31 12:40:08 PM PDT 24
Finished Mar 31 12:46:21 PM PDT 24
Peak memory 202028 kb
Host smart-2d4681c0-08b7-4078-b82d-9e3549c9b279
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144508566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.4144508566
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3126584804
Short name T291
Test name
Test status
Simulation time 39922660122 ps
CPU time 30.09 seconds
Started Mar 31 12:40:08 PM PDT 24
Finished Mar 31 12:40:38 PM PDT 24
Peak memory 210576 kb
Host smart-de9fa788-7d8f-4dca-bfe9-a374e62fc312
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126584804 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3126584804
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3402139090
Short name T616
Test name
Test status
Simulation time 301039922 ps
CPU time 0.99 seconds
Started Mar 31 12:40:11 PM PDT 24
Finished Mar 31 12:40:13 PM PDT 24
Peak memory 201548 kb
Host smart-92d95f24-5b51-499b-ada9-7b947fcfd3b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402139090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3402139090
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.623525092
Short name T590
Test name
Test status
Simulation time 198019428098 ps
CPU time 108.02 seconds
Started Mar 31 12:40:09 PM PDT 24
Finished Mar 31 12:41:58 PM PDT 24
Peak memory 201880 kb
Host smart-fd74c39e-4bb2-41df-85d1-0ca4b9e4d368
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623525092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.623525092
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3360347680
Short name T320
Test name
Test status
Simulation time 361665562686 ps
CPU time 268.18 seconds
Started Mar 31 12:40:08 PM PDT 24
Finished Mar 31 12:44:36 PM PDT 24
Peak memory 201880 kb
Host smart-dadf1aba-31e6-46c2-bc8f-d19cd4478062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360347680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3360347680
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.1897736174
Short name T675
Test name
Test status
Simulation time 496572757869 ps
CPU time 306.96 seconds
Started Mar 31 12:40:02 PM PDT 24
Finished Mar 31 12:45:09 PM PDT 24
Peak memory 201844 kb
Host smart-ccefc763-2e78-4b15-ba28-63f436ef4781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897736174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1897736174
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.847862554
Short name T536
Test name
Test status
Simulation time 170538614832 ps
CPU time 152.19 seconds
Started Mar 31 12:40:05 PM PDT 24
Finished Mar 31 12:42:38 PM PDT 24
Peak memory 201764 kb
Host smart-5dcd6254-ccca-43ac-b5d6-7da4a67d6ed2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=847862554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrup
t_fixed.847862554
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.1141401658
Short name T47
Test name
Test status
Simulation time 494355404947 ps
CPU time 946.52 seconds
Started Mar 31 12:39:59 PM PDT 24
Finished Mar 31 12:55:46 PM PDT 24
Peak memory 201912 kb
Host smart-075fc890-8589-4699-ab91-b1c062ad6280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141401658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.1141401658
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3338496363
Short name T436
Test name
Test status
Simulation time 168652216448 ps
CPU time 403.42 seconds
Started Mar 31 12:40:08 PM PDT 24
Finished Mar 31 12:46:52 PM PDT 24
Peak memory 201796 kb
Host smart-b3f6af43-3ecf-4c78-bc6e-f92f2d16707f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338496363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.3338496363
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.3782622115
Short name T45
Test name
Test status
Simulation time 174974756609 ps
CPU time 388.76 seconds
Started Mar 31 12:40:09 PM PDT 24
Finished Mar 31 12:46:38 PM PDT 24
Peak memory 201872 kb
Host smart-a73f6915-333e-4ad7-9f9b-bcc620b5eb8f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782622115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.3782622115
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3463834611
Short name T450
Test name
Test status
Simulation time 211656367312 ps
CPU time 38.26 seconds
Started Mar 31 12:40:12 PM PDT 24
Finished Mar 31 12:40:51 PM PDT 24
Peak memory 201844 kb
Host smart-00a19073-48e9-4cd7-964f-50d8bbede07e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463834611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.3463834611
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.3618851855
Short name T100
Test name
Test status
Simulation time 105397083901 ps
CPU time 548.07 seconds
Started Mar 31 12:40:08 PM PDT 24
Finished Mar 31 12:49:16 PM PDT 24
Peak memory 202100 kb
Host smart-3a57874a-10f4-4d6c-aebf-8a8091f6d9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618851855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3618851855
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3948337330
Short name T338
Test name
Test status
Simulation time 44342116515 ps
CPU time 96.74 seconds
Started Mar 31 12:40:01 PM PDT 24
Finished Mar 31 12:41:38 PM PDT 24
Peak memory 201584 kb
Host smart-e093f109-56ed-4bb4-af9a-d1e7b2a40ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948337330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3948337330
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2602955520
Short name T493
Test name
Test status
Simulation time 4178402195 ps
CPU time 3.57 seconds
Started Mar 31 12:40:02 PM PDT 24
Finished Mar 31 12:40:05 PM PDT 24
Peak memory 201932 kb
Host smart-8a7c0764-0033-4dfd-a2c5-459b09df2899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602955520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2602955520
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.871281377
Short name T651
Test name
Test status
Simulation time 6033983224 ps
CPU time 6.74 seconds
Started Mar 31 12:40:08 PM PDT 24
Finished Mar 31 12:40:15 PM PDT 24
Peak memory 201680 kb
Host smart-3042b6ba-d537-40b9-bfeb-5f8d0dc23077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871281377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.871281377
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.948514240
Short name T214
Test name
Test status
Simulation time 177207618617 ps
CPU time 209.49 seconds
Started Mar 31 12:40:06 PM PDT 24
Finished Mar 31 12:43:35 PM PDT 24
Peak memory 201884 kb
Host smart-ed12bc1e-d393-469e-b5c8-aa3f6b2e629b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948514240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all.
948514240
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.3521626853
Short name T539
Test name
Test status
Simulation time 185538084901 ps
CPU time 461.59 seconds
Started Mar 31 12:40:07 PM PDT 24
Finished Mar 31 12:47:49 PM PDT 24
Peak memory 210440 kb
Host smart-a95c576d-bece-48aa-800f-721eea5945e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521626853 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.3521626853
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.4044352332
Short name T545
Test name
Test status
Simulation time 537210624 ps
CPU time 0.99 seconds
Started Mar 31 12:40:10 PM PDT 24
Finished Mar 31 12:40:11 PM PDT 24
Peak memory 201500 kb
Host smart-d405a681-4326-490d-af05-7f603e25b090
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044352332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.4044352332
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3897296813
Short name T249
Test name
Test status
Simulation time 327372954107 ps
CPU time 768.85 seconds
Started Mar 31 12:40:15 PM PDT 24
Finished Mar 31 12:53:05 PM PDT 24
Peak memory 201908 kb
Host smart-937f1bb1-8d68-4c8d-ab58-0d7a674574af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897296813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3897296813
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1556981225
Short name T725
Test name
Test status
Simulation time 329774699227 ps
CPU time 806.65 seconds
Started Mar 31 12:40:10 PM PDT 24
Finished Mar 31 12:53:37 PM PDT 24
Peak memory 201820 kb
Host smart-9e985055-da05-427b-9c54-27a0ca6f7dbf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556981225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1556981225
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.494363675
Short name T408
Test name
Test status
Simulation time 164906073001 ps
CPU time 197.77 seconds
Started Mar 31 12:40:00 PM PDT 24
Finished Mar 31 12:43:18 PM PDT 24
Peak memory 201812 kb
Host smart-1a21e2b5-a4a5-4c9b-9882-599a6e7cd472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494363675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.494363675
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3364086360
Short name T631
Test name
Test status
Simulation time 166300049706 ps
CPU time 383.72 seconds
Started Mar 31 12:40:11 PM PDT 24
Finished Mar 31 12:46:36 PM PDT 24
Peak memory 201796 kb
Host smart-1c089492-bde2-47ad-a1ad-206efaa38dcf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364086360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3364086360
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.4238599067
Short name T224
Test name
Test status
Simulation time 182728570053 ps
CPU time 325.67 seconds
Started Mar 31 12:40:15 PM PDT 24
Finished Mar 31 12:45:42 PM PDT 24
Peak memory 201840 kb
Host smart-f5bfa4a3-c246-4ad6-984f-52ac4b04a73c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238599067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.4238599067
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.1126609024
Short name T519
Test name
Test status
Simulation time 123006249295 ps
CPU time 500.49 seconds
Started Mar 31 12:40:17 PM PDT 24
Finished Mar 31 12:48:37 PM PDT 24
Peak memory 202112 kb
Host smart-7d62b764-ce4f-4505-b831-6b14286e0329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126609024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.1126609024
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3719226920
Short name T454
Test name
Test status
Simulation time 26453272880 ps
CPU time 30.45 seconds
Started Mar 31 12:40:09 PM PDT 24
Finished Mar 31 12:40:41 PM PDT 24
Peak memory 201676 kb
Host smart-221fcd18-b30c-48df-9f51-501143b6d884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719226920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3719226920
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2224646224
Short name T446
Test name
Test status
Simulation time 3526621807 ps
CPU time 6.12 seconds
Started Mar 31 12:40:09 PM PDT 24
Finished Mar 31 12:40:15 PM PDT 24
Peak memory 201696 kb
Host smart-c393cebb-cf46-407a-a09c-539f0376f48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224646224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2224646224
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2619912401
Short name T499
Test name
Test status
Simulation time 6059313773 ps
CPU time 14.55 seconds
Started Mar 31 12:40:11 PM PDT 24
Finished Mar 31 12:40:27 PM PDT 24
Peak memory 201632 kb
Host smart-9a231d79-e34b-4b19-ab20-5af1e7e604c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619912401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2619912401
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.2394239402
Short name T625
Test name
Test status
Simulation time 106755039620 ps
CPU time 555.46 seconds
Started Mar 31 12:40:14 PM PDT 24
Finished Mar 31 12:49:30 PM PDT 24
Peak memory 202260 kb
Host smart-929d6551-1717-4ef2-abd2-d91f5aa7570e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394239402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.2394239402
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.392754855
Short name T682
Test name
Test status
Simulation time 57654908123 ps
CPU time 62.44 seconds
Started Mar 31 12:40:22 PM PDT 24
Finished Mar 31 12:41:25 PM PDT 24
Peak memory 211224 kb
Host smart-f5da07f9-c27f-4ef5-8b15-5ee3ad97373c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392754855 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.392754855
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.4035843235
Short name T287
Test name
Test status
Simulation time 326550691233 ps
CPU time 237.61 seconds
Started Mar 31 12:40:12 PM PDT 24
Finished Mar 31 12:44:11 PM PDT 24
Peak memory 201820 kb
Host smart-a1bca279-65fe-4dca-9d33-4d33d6453b24
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035843235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.4035843235
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.362888533
Short name T220
Test name
Test status
Simulation time 497599157390 ps
CPU time 1135.97 seconds
Started Mar 31 12:40:18 PM PDT 24
Finished Mar 31 12:59:14 PM PDT 24
Peak memory 201896 kb
Host smart-6a05d493-73ff-4b69-89f4-012c7ec8a028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362888533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.362888533
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.523697931
Short name T711
Test name
Test status
Simulation time 323739390702 ps
CPU time 348.98 seconds
Started Mar 31 12:40:12 PM PDT 24
Finished Mar 31 12:46:02 PM PDT 24
Peak memory 201864 kb
Host smart-bbb20844-aa1a-41b5-8d83-ac24756673b7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=523697931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrup
t_fixed.523697931
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.2766184959
Short name T206
Test name
Test status
Simulation time 333087507902 ps
CPU time 522.61 seconds
Started Mar 31 12:40:12 PM PDT 24
Finished Mar 31 12:48:56 PM PDT 24
Peak memory 201832 kb
Host smart-4b1facd6-aa29-4e1e-a64a-871ea5ddbf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766184959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2766184959
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.3984364097
Short name T508
Test name
Test status
Simulation time 489430713472 ps
CPU time 80.65 seconds
Started Mar 31 12:40:12 PM PDT 24
Finished Mar 31 12:41:34 PM PDT 24
Peak memory 201868 kb
Host smart-52b74a6d-cbcc-49cc-9af3-9a2b61dc770f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984364097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.3984364097
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.535434623
Short name T180
Test name
Test status
Simulation time 335328732338 ps
CPU time 123.76 seconds
Started Mar 31 12:40:08 PM PDT 24
Finished Mar 31 12:42:12 PM PDT 24
Peak memory 201884 kb
Host smart-544b7a03-77e9-4928-a15b-c09a1b206f16
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535434623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_
wakeup.535434623
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.4194215120
Short name T507
Test name
Test status
Simulation time 595221407504 ps
CPU time 906.49 seconds
Started Mar 31 12:40:09 PM PDT 24
Finished Mar 31 12:55:17 PM PDT 24
Peak memory 201804 kb
Host smart-83e90dc4-39d1-4b4c-ae38-ee228b577762
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194215120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.4194215120
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.2724438951
Short name T189
Test name
Test status
Simulation time 27413969795 ps
CPU time 60.12 seconds
Started Mar 31 12:40:10 PM PDT 24
Finished Mar 31 12:41:11 PM PDT 24
Peak memory 201708 kb
Host smart-c5129f67-a6f7-4bf1-b473-244d315c2a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724438951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2724438951
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.2610631614
Short name T355
Test name
Test status
Simulation time 3432138754 ps
CPU time 2.73 seconds
Started Mar 31 12:40:12 PM PDT 24
Finished Mar 31 12:40:16 PM PDT 24
Peak memory 201632 kb
Host smart-4a797f1e-f631-49f4-8be5-24add7bcc644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610631614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.2610631614
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.4034958982
Short name T398
Test name
Test status
Simulation time 6003907638 ps
CPU time 4.04 seconds
Started Mar 31 12:40:09 PM PDT 24
Finished Mar 31 12:40:14 PM PDT 24
Peak memory 201688 kb
Host smart-a52a62fe-0263-4924-ab94-616679f3b936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034958982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.4034958982
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3121344348
Short name T312
Test name
Test status
Simulation time 326250695049 ps
CPU time 371.14 seconds
Started Mar 31 12:40:21 PM PDT 24
Finished Mar 31 12:46:32 PM PDT 24
Peak memory 201820 kb
Host smart-4aa62883-a23b-4f8d-a434-89e6a7655072
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121344348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3121344348
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2803112933
Short name T713
Test name
Test status
Simulation time 203556155086 ps
CPU time 102.62 seconds
Started Mar 31 12:40:09 PM PDT 24
Finished Mar 31 12:41:53 PM PDT 24
Peak memory 210256 kb
Host smart-cde85a05-c097-495c-adf4-17ac09b8e391
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803112933 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.2803112933
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1012671878
Short name T538
Test name
Test status
Simulation time 358870776 ps
CPU time 1.06 seconds
Started Mar 31 12:40:17 PM PDT 24
Finished Mar 31 12:40:18 PM PDT 24
Peak memory 201440 kb
Host smart-8ff2ef06-ea43-4398-9666-8f2f19a73e97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012671878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1012671878
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.4112303722
Short name T256
Test name
Test status
Simulation time 327153682051 ps
CPU time 453.64 seconds
Started Mar 31 12:40:08 PM PDT 24
Finished Mar 31 12:47:42 PM PDT 24
Peak memory 201872 kb
Host smart-eb4e7acf-4ba9-4edd-a944-69625f5004e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112303722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.4112303722
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.3056813379
Short name T165
Test name
Test status
Simulation time 551236949062 ps
CPU time 336.26 seconds
Started Mar 31 12:40:11 PM PDT 24
Finished Mar 31 12:45:49 PM PDT 24
Peak memory 201848 kb
Host smart-1e6e1e79-5876-456e-8287-fccab5995dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056813379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.3056813379
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1684722898
Short name T267
Test name
Test status
Simulation time 328454741592 ps
CPU time 756.23 seconds
Started Mar 31 12:40:12 PM PDT 24
Finished Mar 31 12:52:49 PM PDT 24
Peak memory 201904 kb
Host smart-31946d24-b2d2-40bf-b652-183ba7ed8d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684722898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1684722898
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.1099575605
Short name T681
Test name
Test status
Simulation time 158419710207 ps
CPU time 74.28 seconds
Started Mar 31 12:40:09 PM PDT 24
Finished Mar 31 12:41:25 PM PDT 24
Peak memory 201824 kb
Host smart-e59d0a20-6e40-43c1-9b2e-7ab9022446b3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099575605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.1099575605
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3174661549
Short name T770
Test name
Test status
Simulation time 334933459348 ps
CPU time 386.6 seconds
Started Mar 31 12:40:08 PM PDT 24
Finished Mar 31 12:46:36 PM PDT 24
Peak memory 201800 kb
Host smart-5b6957fa-f403-4c05-a5bf-7ce09d19d4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174661549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3174661549
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1682473272
Short name T560
Test name
Test status
Simulation time 489663134818 ps
CPU time 101.56 seconds
Started Mar 31 12:40:19 PM PDT 24
Finished Mar 31 12:42:01 PM PDT 24
Peak memory 201860 kb
Host smart-89379c98-d750-42bd-9e21-c9529a7d9045
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682473272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1682473272
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3902532949
Short name T350
Test name
Test status
Simulation time 215210495012 ps
CPU time 176.47 seconds
Started Mar 31 12:40:18 PM PDT 24
Finished Mar 31 12:43:14 PM PDT 24
Peak memory 201964 kb
Host smart-54b2d0f3-27c3-46fc-9b1d-9ace00c45393
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902532949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3902532949
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3584943774
Short name T562
Test name
Test status
Simulation time 108475134960 ps
CPU time 342.42 seconds
Started Mar 31 12:40:19 PM PDT 24
Finished Mar 31 12:46:01 PM PDT 24
Peak memory 201880 kb
Host smart-3131e9f4-b948-4a08-bc64-2b1699dc3533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584943774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3584943774
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1961247062
Short name T534
Test name
Test status
Simulation time 22802979608 ps
CPU time 47.52 seconds
Started Mar 31 12:40:32 PM PDT 24
Finished Mar 31 12:41:20 PM PDT 24
Peak memory 201696 kb
Host smart-4560137d-f430-45ed-8dac-9235d7174cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961247062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1961247062
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.3823476807
Short name T410
Test name
Test status
Simulation time 4084072984 ps
CPU time 1.4 seconds
Started Mar 31 12:40:16 PM PDT 24
Finished Mar 31 12:40:17 PM PDT 24
Peak memory 201628 kb
Host smart-bd234bf7-8796-4c3a-9e28-488983238293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823476807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.3823476807
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.2808585047
Short name T763
Test name
Test status
Simulation time 5979386758 ps
CPU time 15.7 seconds
Started Mar 31 12:40:09 PM PDT 24
Finished Mar 31 12:40:25 PM PDT 24
Peak memory 201700 kb
Host smart-710793ed-b1a9-405c-9880-685becd1a023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808585047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2808585047
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1958884198
Short name T479
Test name
Test status
Simulation time 253477661514 ps
CPU time 579.39 seconds
Started Mar 31 12:40:17 PM PDT 24
Finished Mar 31 12:49:56 PM PDT 24
Peak memory 201960 kb
Host smart-a953ba28-5617-4886-904b-a96a73cef5f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958884198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1958884198
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.11711657
Short name T689
Test name
Test status
Simulation time 57874231921 ps
CPU time 137.49 seconds
Started Mar 31 12:40:20 PM PDT 24
Finished Mar 31 12:42:37 PM PDT 24
Peak memory 217852 kb
Host smart-58e3a03f-0bf3-4bcf-b511-75ff0f96a911
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11711657 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.11711657
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.2053811620
Short name T611
Test name
Test status
Simulation time 465339303 ps
CPU time 1.48 seconds
Started Mar 31 12:40:21 PM PDT 24
Finished Mar 31 12:40:23 PM PDT 24
Peak memory 201584 kb
Host smart-37748b21-03c2-4d7d-8600-263ebdde42e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053811620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.2053811620
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2131081927
Short name T71
Test name
Test status
Simulation time 158799797443 ps
CPU time 208.99 seconds
Started Mar 31 12:40:15 PM PDT 24
Finished Mar 31 12:43:45 PM PDT 24
Peak memory 201936 kb
Host smart-e410a35a-c869-4a3c-8f8b-4e59be345889
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131081927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2131081927
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1150549376
Short name T263
Test name
Test status
Simulation time 171420193368 ps
CPU time 108.93 seconds
Started Mar 31 12:40:17 PM PDT 24
Finished Mar 31 12:42:06 PM PDT 24
Peak memory 201792 kb
Host smart-56c2e3e2-7945-4b51-9777-4b789046f794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150549376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1150549376
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1243697564
Short name T216
Test name
Test status
Simulation time 325398206548 ps
CPU time 202.12 seconds
Started Mar 31 12:40:17 PM PDT 24
Finished Mar 31 12:43:39 PM PDT 24
Peak memory 201724 kb
Host smart-1e4f5b47-ef96-497c-818a-28367b05e7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243697564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1243697564
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2261560895
Short name T58
Test name
Test status
Simulation time 164061634117 ps
CPU time 365.78 seconds
Started Mar 31 12:40:15 PM PDT 24
Finished Mar 31 12:46:22 PM PDT 24
Peak memory 201872 kb
Host smart-8909d9ee-d0de-4a95-9d96-8b051da67a6a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261560895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2261560895
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2345440995
Short name T574
Test name
Test status
Simulation time 481250745927 ps
CPU time 1110.74 seconds
Started Mar 31 12:40:15 PM PDT 24
Finished Mar 31 12:58:47 PM PDT 24
Peak memory 201804 kb
Host smart-b473a148-5597-4142-9b96-ee6067e34673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345440995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2345440995
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.824807660
Short name T382
Test name
Test status
Simulation time 164262611425 ps
CPU time 373.97 seconds
Started Mar 31 12:40:13 PM PDT 24
Finished Mar 31 12:46:28 PM PDT 24
Peak memory 201868 kb
Host smart-17fd259f-ffcd-44f4-af6a-140726e59f2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=824807660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixe
d.824807660
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1086972967
Short name T56
Test name
Test status
Simulation time 371690482009 ps
CPU time 933.64 seconds
Started Mar 31 12:40:15 PM PDT 24
Finished Mar 31 12:55:50 PM PDT 24
Peak memory 201976 kb
Host smart-dc82bfd0-c3dc-4b5e-9567-bf9c952f4a82
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086972967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1086972967
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2395939980
Short name T378
Test name
Test status
Simulation time 197996295831 ps
CPU time 89.63 seconds
Started Mar 31 12:40:18 PM PDT 24
Finished Mar 31 12:41:48 PM PDT 24
Peak memory 201780 kb
Host smart-76527a48-e812-4b1d-9f0c-9e9483b8f12f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395939980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.2395939980
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.4199704649
Short name T426
Test name
Test status
Simulation time 110135841206 ps
CPU time 424.91 seconds
Started Mar 31 12:40:22 PM PDT 24
Finished Mar 31 12:47:27 PM PDT 24
Peak memory 202176 kb
Host smart-40325938-d944-48e6-bcdb-c12966043fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199704649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.4199704649
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1588866007
Short name T506
Test name
Test status
Simulation time 24048890449 ps
CPU time 29.16 seconds
Started Mar 31 12:40:20 PM PDT 24
Finished Mar 31 12:40:50 PM PDT 24
Peak memory 201636 kb
Host smart-4d2d109d-0e05-44d2-8e2a-df910835df62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588866007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1588866007
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.780854153
Short name T732
Test name
Test status
Simulation time 4835706537 ps
CPU time 2.13 seconds
Started Mar 31 12:40:15 PM PDT 24
Finished Mar 31 12:40:18 PM PDT 24
Peak memory 201704 kb
Host smart-4125124d-dd09-4b2e-9f38-552bb7d3b01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780854153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.780854153
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3317785508
Short name T110
Test name
Test status
Simulation time 5828846156 ps
CPU time 6.94 seconds
Started Mar 31 12:40:19 PM PDT 24
Finished Mar 31 12:40:26 PM PDT 24
Peak memory 201256 kb
Host smart-56b5105b-583e-4a43-8d50-ca59632cb304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317785508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3317785508
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3971773255
Short name T678
Test name
Test status
Simulation time 103268213065 ps
CPU time 91.97 seconds
Started Mar 31 12:40:22 PM PDT 24
Finished Mar 31 12:41:54 PM PDT 24
Peak memory 210132 kb
Host smart-7f585de3-750e-4d4b-a95d-f74a848aca82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971773255 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3971773255
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2494740537
Short name T727
Test name
Test status
Simulation time 305842064 ps
CPU time 1.34 seconds
Started Mar 31 12:40:28 PM PDT 24
Finished Mar 31 12:40:29 PM PDT 24
Peak memory 201548 kb
Host smart-bfdbc81e-9623-4d4e-b938-5134ef232918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494740537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2494740537
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1318951817
Short name T292
Test name
Test status
Simulation time 163308905340 ps
CPU time 70.23 seconds
Started Mar 31 12:40:28 PM PDT 24
Finished Mar 31 12:41:38 PM PDT 24
Peak memory 201944 kb
Host smart-ccd1e22f-caa5-4d62-9bcd-475ae1e861df
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318951817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1318951817
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.2817061282
Short name T761
Test name
Test status
Simulation time 355632027067 ps
CPU time 884.34 seconds
Started Mar 31 12:40:22 PM PDT 24
Finished Mar 31 12:55:07 PM PDT 24
Peak memory 201792 kb
Host smart-1a505447-dd95-43e7-b574-f21842e2559f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817061282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.2817061282
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.173932092
Short name T511
Test name
Test status
Simulation time 495656352309 ps
CPU time 287.82 seconds
Started Mar 31 12:40:26 PM PDT 24
Finished Mar 31 12:45:14 PM PDT 24
Peak memory 201852 kb
Host smart-92512ca3-8889-42c8-b0a0-d3cdb4ef86df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=173932092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrup
t_fixed.173932092
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.301201711
Short name T296
Test name
Test status
Simulation time 332354349807 ps
CPU time 397.69 seconds
Started Mar 31 12:40:26 PM PDT 24
Finished Mar 31 12:47:05 PM PDT 24
Peak memory 201964 kb
Host smart-129e5b4c-282a-453a-a263-c76f75355244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301201711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.301201711
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1614695599
Short name T368
Test name
Test status
Simulation time 483580877316 ps
CPU time 1119.24 seconds
Started Mar 31 12:40:25 PM PDT 24
Finished Mar 31 12:59:04 PM PDT 24
Peak memory 201836 kb
Host smart-d5300cc6-4716-4d1e-bcac-a2c6e323a003
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614695599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.1614695599
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.1078684266
Short name T568
Test name
Test status
Simulation time 404621373287 ps
CPU time 452.93 seconds
Started Mar 31 12:40:26 PM PDT 24
Finished Mar 31 12:48:00 PM PDT 24
Peak memory 201888 kb
Host smart-0cd03486-e04c-49a3-8635-b1814a7aa5ab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078684266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.1078684266
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.183417807
Short name T353
Test name
Test status
Simulation time 68396977137 ps
CPU time 206.76 seconds
Started Mar 31 12:40:31 PM PDT 24
Finished Mar 31 12:43:58 PM PDT 24
Peak memory 202144 kb
Host smart-28fa7f80-d55d-4a09-8da7-842167ceb0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183417807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.183417807
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3308221083
Short name T674
Test name
Test status
Simulation time 30666953502 ps
CPU time 73.33 seconds
Started Mar 31 12:40:32 PM PDT 24
Finished Mar 31 12:41:45 PM PDT 24
Peak memory 201624 kb
Host smart-05d22ef2-68d1-48d3-b01c-28282b0c6a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308221083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3308221083
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2299476045
Short name T188
Test name
Test status
Simulation time 5177464442 ps
CPU time 7.3 seconds
Started Mar 31 12:40:33 PM PDT 24
Finished Mar 31 12:40:40 PM PDT 24
Peak memory 201684 kb
Host smart-2c1a1a4d-273d-415c-91cf-6fb44c914dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299476045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2299476045
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3690218944
Short name T610
Test name
Test status
Simulation time 6122871154 ps
CPU time 4.2 seconds
Started Mar 31 12:40:23 PM PDT 24
Finished Mar 31 12:40:28 PM PDT 24
Peak memory 201696 kb
Host smart-6f7de9b6-cd50-4dcd-a9d5-96239394a1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690218944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3690218944
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.3247974652
Short name T227
Test name
Test status
Simulation time 342318953157 ps
CPU time 844.74 seconds
Started Mar 31 12:40:25 PM PDT 24
Finished Mar 31 12:54:30 PM PDT 24
Peak memory 201912 kb
Host smart-32efdae9-997c-45c6-a546-ca270c381ccf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247974652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.3247974652
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.3184112767
Short name T104
Test name
Test status
Simulation time 189616253428 ps
CPU time 152.43 seconds
Started Mar 31 12:40:23 PM PDT 24
Finished Mar 31 12:42:56 PM PDT 24
Peak memory 218580 kb
Host smart-7d21e445-1507-4ee9-98c9-4099a6bfbc99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184112767 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.3184112767
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.3854291786
Short name T742
Test name
Test status
Simulation time 535850737 ps
CPU time 0.96 seconds
Started Mar 31 12:40:30 PM PDT 24
Finished Mar 31 12:40:31 PM PDT 24
Peak memory 201592 kb
Host smart-42d18b9a-486e-49ec-9369-4fce56da7817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854291786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.3854291786
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2343204784
Short name T225
Test name
Test status
Simulation time 329075552842 ps
CPU time 193.76 seconds
Started Mar 31 12:40:32 PM PDT 24
Finished Mar 31 12:43:45 PM PDT 24
Peak memory 201940 kb
Host smart-1d7aea43-d442-41e3-a8e9-d1799cd6c6bc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343204784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2343204784
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2114858852
Short name T663
Test name
Test status
Simulation time 378568465921 ps
CPU time 225.42 seconds
Started Mar 31 12:40:29 PM PDT 24
Finished Mar 31 12:44:15 PM PDT 24
Peak memory 201868 kb
Host smart-bd23e594-95a9-457d-83ab-f01bb1287fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114858852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2114858852
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2194808951
Short name T112
Test name
Test status
Simulation time 322611018073 ps
CPU time 375.1 seconds
Started Mar 31 12:40:32 PM PDT 24
Finished Mar 31 12:46:47 PM PDT 24
Peak memory 201784 kb
Host smart-1f0f32bc-5c99-4488-bd1d-36a50be13944
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194808951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.2194808951
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.879975690
Short name T151
Test name
Test status
Simulation time 160494907747 ps
CPU time 352.15 seconds
Started Mar 31 12:40:20 PM PDT 24
Finished Mar 31 12:46:12 PM PDT 24
Peak memory 201868 kb
Host smart-889f8830-29e5-4908-9e9b-dbca50dc15f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879975690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.879975690
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.105271847
Short name T599
Test name
Test status
Simulation time 331687508497 ps
CPU time 199.47 seconds
Started Mar 31 12:40:24 PM PDT 24
Finished Mar 31 12:43:43 PM PDT 24
Peak memory 201864 kb
Host smart-27da7522-923e-45ed-95af-ab1277782564
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=105271847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixe
d.105271847
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.3172589545
Short name T789
Test name
Test status
Simulation time 198829237312 ps
CPU time 456.69 seconds
Started Mar 31 12:40:26 PM PDT 24
Finished Mar 31 12:48:03 PM PDT 24
Peak memory 201816 kb
Host smart-a8cecd9b-1b90-467d-abcb-7bf18fd004ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172589545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.3172589545
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.4270320277
Short name T680
Test name
Test status
Simulation time 193769900457 ps
CPU time 465.47 seconds
Started Mar 31 12:40:26 PM PDT 24
Finished Mar 31 12:48:13 PM PDT 24
Peak memory 201792 kb
Host smart-842977ba-e536-4325-a2c5-2aaf50c19c1a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270320277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.4270320277
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.1320475422
Short name T783
Test name
Test status
Simulation time 34855446756 ps
CPU time 41.97 seconds
Started Mar 31 12:40:28 PM PDT 24
Finished Mar 31 12:41:11 PM PDT 24
Peak memory 201688 kb
Host smart-d8070ec4-f058-4d9a-ab5f-bfcc3c2b8418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320475422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1320475422
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1888120435
Short name T420
Test name
Test status
Simulation time 4862451261 ps
CPU time 7.33 seconds
Started Mar 31 12:40:31 PM PDT 24
Finished Mar 31 12:40:38 PM PDT 24
Peak memory 201688 kb
Host smart-121a856a-7464-4d2e-823f-aed25601a2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888120435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1888120435
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.4274506289
Short name T30
Test name
Test status
Simulation time 5706016469 ps
CPU time 13.65 seconds
Started Mar 31 12:40:26 PM PDT 24
Finished Mar 31 12:40:40 PM PDT 24
Peak memory 201624 kb
Host smart-8328de96-7d42-496d-b735-31b96b14eee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274506289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.4274506289
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1459443558
Short name T61
Test name
Test status
Simulation time 457915785 ps
CPU time 1.21 seconds
Started Mar 31 12:40:29 PM PDT 24
Finished Mar 31 12:40:31 PM PDT 24
Peak memory 201608 kb
Host smart-56bb992c-f60a-4781-8b57-712fd12d4a00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459443558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1459443558
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2134248458
Short name T253
Test name
Test status
Simulation time 162874950812 ps
CPU time 99.52 seconds
Started Mar 31 12:40:30 PM PDT 24
Finished Mar 31 12:42:09 PM PDT 24
Peak memory 201872 kb
Host smart-bb83c1b0-7e5a-43b1-af82-adcbb49aabf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134248458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2134248458
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.1990725620
Short name T391
Test name
Test status
Simulation time 489350980923 ps
CPU time 531.33 seconds
Started Mar 31 12:40:35 PM PDT 24
Finished Mar 31 12:49:27 PM PDT 24
Peak memory 201796 kb
Host smart-e7adaa23-79d6-4c9b-beae-7199393dd4a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990725620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.1990725620
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.4165985736
Short name T301
Test name
Test status
Simulation time 489185467927 ps
CPU time 417.09 seconds
Started Mar 31 12:40:38 PM PDT 24
Finished Mar 31 12:47:36 PM PDT 24
Peak memory 201908 kb
Host smart-0683285e-19c4-4a2a-971f-ed3914001d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165985736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.4165985736
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1564791029
Short name T773
Test name
Test status
Simulation time 493560537962 ps
CPU time 361.71 seconds
Started Mar 31 12:40:29 PM PDT 24
Finished Mar 31 12:46:31 PM PDT 24
Peak memory 201780 kb
Host smart-bc8b5705-3726-42a6-b26b-221766b733cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564791029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1564791029
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2492609497
Short name T544
Test name
Test status
Simulation time 382600153927 ps
CPU time 73.91 seconds
Started Mar 31 12:40:29 PM PDT 24
Finished Mar 31 12:41:43 PM PDT 24
Peak memory 201972 kb
Host smart-dd50eddc-4021-408b-b7ea-e213f70bbc4a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492609497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2492609497
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1712478069
Short name T411
Test name
Test status
Simulation time 619633369361 ps
CPU time 165.79 seconds
Started Mar 31 12:40:29 PM PDT 24
Finished Mar 31 12:43:15 PM PDT 24
Peak memory 201884 kb
Host smart-7706643d-b403-4363-b71a-6ae55e5945a5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712478069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1712478069
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.521254495
Short name T692
Test name
Test status
Simulation time 111012011419 ps
CPU time 555.92 seconds
Started Mar 31 12:40:40 PM PDT 24
Finished Mar 31 12:49:56 PM PDT 24
Peak memory 202080 kb
Host smart-64f10c7a-593f-4729-85d8-1428e539f810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521254495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.521254495
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.131767312
Short name T480
Test name
Test status
Simulation time 25974009378 ps
CPU time 17.67 seconds
Started Mar 31 12:40:27 PM PDT 24
Finished Mar 31 12:40:45 PM PDT 24
Peak memory 201684 kb
Host smart-fcb4cace-d25e-4a91-a1df-2a859e0877a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131767312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.131767312
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.2770827413
Short name T672
Test name
Test status
Simulation time 4926706215 ps
CPU time 4.7 seconds
Started Mar 31 12:40:32 PM PDT 24
Finished Mar 31 12:40:36 PM PDT 24
Peak memory 201704 kb
Host smart-11e8aa7e-8bb5-450b-afc1-8f510f7ef8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770827413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.2770827413
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1844160119
Short name T695
Test name
Test status
Simulation time 5962868075 ps
CPU time 13.02 seconds
Started Mar 31 12:40:29 PM PDT 24
Finished Mar 31 12:40:42 PM PDT 24
Peak memory 201584 kb
Host smart-219c6147-c128-4b60-8f9a-3fa751454dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844160119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1844160119
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.2889244515
Short name T254
Test name
Test status
Simulation time 291462771074 ps
CPU time 595.85 seconds
Started Mar 31 12:40:29 PM PDT 24
Finished Mar 31 12:50:25 PM PDT 24
Peak memory 212480 kb
Host smart-4ee1f4e7-89c0-4edd-a919-eaac3b0b75dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889244515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.2889244515
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1683239566
Short name T50
Test name
Test status
Simulation time 144401696127 ps
CPU time 95.74 seconds
Started Mar 31 12:40:28 PM PDT 24
Finished Mar 31 12:42:04 PM PDT 24
Peak memory 210220 kb
Host smart-15f64c42-e59e-461f-9657-9fd8d2d378ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683239566 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1683239566
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3585798292
Short name T371
Test name
Test status
Simulation time 408971692 ps
CPU time 0.92 seconds
Started Mar 31 12:39:54 PM PDT 24
Finished Mar 31 12:39:55 PM PDT 24
Peak memory 201480 kb
Host smart-bf924ede-fb37-4fa6-b2f6-ba1fc22a42db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585798292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3585798292
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.1929844683
Short name T764
Test name
Test status
Simulation time 378852582188 ps
CPU time 523.7 seconds
Started Mar 31 12:40:11 PM PDT 24
Finished Mar 31 12:48:56 PM PDT 24
Peak memory 201876 kb
Host smart-de89874b-8642-4c54-b7b5-220f77ff0825
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929844683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.1929844683
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.4118415748
Short name T505
Test name
Test status
Simulation time 163291129498 ps
CPU time 177.2 seconds
Started Mar 31 12:40:01 PM PDT 24
Finished Mar 31 12:42:58 PM PDT 24
Peak memory 201816 kb
Host smart-d88e6b93-0fc5-4a5d-8411-434c56da1e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118415748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.4118415748
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.634806789
Short name T602
Test name
Test status
Simulation time 322523806020 ps
CPU time 351.39 seconds
Started Mar 31 12:40:10 PM PDT 24
Finished Mar 31 12:46:02 PM PDT 24
Peak memory 201884 kb
Host smart-47756993-464e-4db8-bc01-1e391f5b15ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634806789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.634806789
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3910965770
Short name T146
Test name
Test status
Simulation time 160257237033 ps
CPU time 46.14 seconds
Started Mar 31 12:39:58 PM PDT 24
Finished Mar 31 12:40:44 PM PDT 24
Peak memory 201828 kb
Host smart-f7b0d660-9650-4cc1-b662-7515375bf32e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910965770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3910965770
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.2624106685
Short name T640
Test name
Test status
Simulation time 165132422627 ps
CPU time 410.87 seconds
Started Mar 31 12:40:06 PM PDT 24
Finished Mar 31 12:46:57 PM PDT 24
Peak memory 201924 kb
Host smart-479a2118-a910-4092-837c-5e51914c6a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624106685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2624106685
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1430265874
Short name T523
Test name
Test status
Simulation time 164451596449 ps
CPU time 395.45 seconds
Started Mar 31 12:40:08 PM PDT 24
Finished Mar 31 12:46:45 PM PDT 24
Peak memory 201852 kb
Host smart-e065fb52-6cd8-43f6-a04d-4aba51311878
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430265874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1430265874
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1389741628
Short name T698
Test name
Test status
Simulation time 600355311106 ps
CPU time 1447.52 seconds
Started Mar 31 12:39:56 PM PDT 24
Finished Mar 31 01:04:04 PM PDT 24
Peak memory 201876 kb
Host smart-2c2c836b-2b99-478b-8cb7-8c29914a15d3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389741628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.1389741628
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1387157031
Short name T194
Test name
Test status
Simulation time 123076845951 ps
CPU time 522.96 seconds
Started Mar 31 12:40:08 PM PDT 24
Finished Mar 31 12:48:51 PM PDT 24
Peak memory 202180 kb
Host smart-d4dff724-ed89-471d-9d45-fb18c2b6e769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387157031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1387157031
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.493788442
Short name T667
Test name
Test status
Simulation time 32490993815 ps
CPU time 15.9 seconds
Started Mar 31 12:40:10 PM PDT 24
Finished Mar 31 12:40:27 PM PDT 24
Peak memory 201684 kb
Host smart-258f9554-80d4-43b2-86fc-a6fd6a6dc6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493788442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.493788442
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.4071798658
Short name T528
Test name
Test status
Simulation time 3224774013 ps
CPU time 8.26 seconds
Started Mar 31 12:39:59 PM PDT 24
Finished Mar 31 12:40:07 PM PDT 24
Peak memory 201584 kb
Host smart-2abfddaa-f5a6-41a3-b0d2-69dc42d47313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071798658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.4071798658
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3366408160
Short name T80
Test name
Test status
Simulation time 4392331939 ps
CPU time 3.34 seconds
Started Mar 31 12:40:12 PM PDT 24
Finished Mar 31 12:40:16 PM PDT 24
Peak memory 217268 kb
Host smart-b4ca4c3d-3f07-45ea-a3d0-9ddeeaa05d27
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366408160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3366408160
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.1003636508
Short name T753
Test name
Test status
Simulation time 5948645341 ps
CPU time 4.54 seconds
Started Mar 31 12:39:58 PM PDT 24
Finished Mar 31 12:40:02 PM PDT 24
Peak memory 201660 kb
Host smart-86add6fd-5476-4684-8aa7-1e75ac24e037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003636508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.1003636508
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.3465728278
Short name T690
Test name
Test status
Simulation time 26514034726 ps
CPU time 62.26 seconds
Started Mar 31 12:39:56 PM PDT 24
Finished Mar 31 12:40:59 PM PDT 24
Peak memory 201700 kb
Host smart-84be3ea3-0b01-458e-942b-b88f33685fb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465728278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
3465728278
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1792476530
Short name T601
Test name
Test status
Simulation time 496813992 ps
CPU time 0.7 seconds
Started Mar 31 12:40:29 PM PDT 24
Finished Mar 31 12:40:30 PM PDT 24
Peak memory 201448 kb
Host smart-83beec09-e0b1-47f2-8f6d-7ad1bf7b0e6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792476530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1792476530
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.2228573281
Short name T313
Test name
Test status
Simulation time 336805437104 ps
CPU time 502.93 seconds
Started Mar 31 12:40:30 PM PDT 24
Finished Mar 31 12:48:53 PM PDT 24
Peak memory 201892 kb
Host smart-c6c9beab-2b5e-40c8-bc39-ee35e54a7227
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228573281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.2228573281
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2876350211
Short name T6
Test name
Test status
Simulation time 160311042486 ps
CPU time 192.96 seconds
Started Mar 31 12:40:35 PM PDT 24
Finished Mar 31 12:43:48 PM PDT 24
Peak memory 201812 kb
Host smart-f72bfa2f-f9db-49fc-bcde-6cf690f20115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876350211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2876350211
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.3680498875
Short name T702
Test name
Test status
Simulation time 166550585351 ps
CPU time 410.44 seconds
Started Mar 31 12:40:32 PM PDT 24
Finished Mar 31 12:47:23 PM PDT 24
Peak memory 201860 kb
Host smart-67607004-80e3-4a02-877d-eb4639d52073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680498875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3680498875
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2072450683
Short name T617
Test name
Test status
Simulation time 330077552087 ps
CPU time 720.61 seconds
Started Mar 31 12:40:29 PM PDT 24
Finished Mar 31 12:52:30 PM PDT 24
Peak memory 201868 kb
Host smart-8a09abe3-af9c-4220-8209-017cba176fe3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072450683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2072450683
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3396524673
Short name T309
Test name
Test status
Simulation time 495596717568 ps
CPU time 315.25 seconds
Started Mar 31 12:40:35 PM PDT 24
Finished Mar 31 12:45:50 PM PDT 24
Peak memory 201848 kb
Host smart-e0f2c14c-3500-4fdb-b002-da45161c868c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396524673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3396524673
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2857569806
Short name T445
Test name
Test status
Simulation time 325330840274 ps
CPU time 746.09 seconds
Started Mar 31 12:40:31 PM PDT 24
Finished Mar 31 12:52:58 PM PDT 24
Peak memory 201772 kb
Host smart-cdc5eaf2-ecba-416e-b32d-6a24b5638f2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857569806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2857569806
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.16389734
Short name T212
Test name
Test status
Simulation time 343675284875 ps
CPU time 224.9 seconds
Started Mar 31 12:40:28 PM PDT 24
Finished Mar 31 12:44:13 PM PDT 24
Peak memory 201932 kb
Host smart-64ccbf0a-9876-41bf-bf26-93955fab57ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16389734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_w
akeup.16389734
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2896905721
Short name T358
Test name
Test status
Simulation time 594955706069 ps
CPU time 115.3 seconds
Started Mar 31 12:40:35 PM PDT 24
Finished Mar 31 12:42:30 PM PDT 24
Peak memory 201820 kb
Host smart-15593b90-000e-444e-9baf-2df5cbda820d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896905721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2896905721
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3813798315
Short name T786
Test name
Test status
Simulation time 103344782299 ps
CPU time 345.3 seconds
Started Mar 31 12:40:29 PM PDT 24
Finished Mar 31 12:46:15 PM PDT 24
Peak memory 202064 kb
Host smart-dfb3e6f7-66f8-45db-8927-b81c2f55cb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813798315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3813798315
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.2432147381
Short name T413
Test name
Test status
Simulation time 41074269435 ps
CPU time 53.15 seconds
Started Mar 31 12:40:27 PM PDT 24
Finished Mar 31 12:41:20 PM PDT 24
Peak memory 201616 kb
Host smart-1feeb896-be65-439a-a318-460da874ebdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432147381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.2432147381
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1389556607
Short name T138
Test name
Test status
Simulation time 4361792390 ps
CPU time 11.29 seconds
Started Mar 31 12:40:29 PM PDT 24
Finished Mar 31 12:40:40 PM PDT 24
Peak memory 201680 kb
Host smart-81ddf5d6-4b9c-45b7-9c06-ac96da7f7d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389556607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1389556607
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1714775412
Short name T733
Test name
Test status
Simulation time 5784982233 ps
CPU time 4.12 seconds
Started Mar 31 12:40:30 PM PDT 24
Finished Mar 31 12:40:35 PM PDT 24
Peak memory 201680 kb
Host smart-4f9219cc-1973-425f-9186-f87aebe6f2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714775412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1714775412
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.2321062822
Short name T709
Test name
Test status
Simulation time 360234779997 ps
CPU time 814.11 seconds
Started Mar 31 12:40:28 PM PDT 24
Finished Mar 31 12:54:03 PM PDT 24
Peak memory 201852 kb
Host smart-3c37e05f-4bd6-487a-9ce3-ea331ccedec0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321062822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.2321062822
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.3453177512
Short name T494
Test name
Test status
Simulation time 90002844786 ps
CPU time 56.25 seconds
Started Mar 31 12:40:28 PM PDT 24
Finished Mar 31 12:41:24 PM PDT 24
Peak memory 212560 kb
Host smart-f024cdbf-1bc8-499d-a0ae-aeb7d4b9fe0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453177512 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.3453177512
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.78835626
Short name T490
Test name
Test status
Simulation time 282569139 ps
CPU time 1.24 seconds
Started Mar 31 12:40:34 PM PDT 24
Finished Mar 31 12:40:35 PM PDT 24
Peak memory 201552 kb
Host smart-c27444c5-93a5-402e-8fde-13354cfdbe0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78835626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.78835626
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.456950132
Short name T759
Test name
Test status
Simulation time 485952215536 ps
CPU time 363.65 seconds
Started Mar 31 12:40:38 PM PDT 24
Finished Mar 31 12:46:42 PM PDT 24
Peak memory 201876 kb
Host smart-3bd0d650-c5a2-4ac2-9cf0-0cfd28b18873
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456950132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gati
ng.456950132
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1880771512
Short name T700
Test name
Test status
Simulation time 391065018996 ps
CPU time 829.99 seconds
Started Mar 31 12:40:46 PM PDT 24
Finished Mar 31 12:54:37 PM PDT 24
Peak memory 201860 kb
Host smart-b9afe0b7-afff-4afd-8e32-35c8cf31a470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880771512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1880771512
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.3495987262
Short name T259
Test name
Test status
Simulation time 166532886961 ps
CPU time 169 seconds
Started Mar 31 12:40:33 PM PDT 24
Finished Mar 31 12:43:22 PM PDT 24
Peak memory 201956 kb
Host smart-ce4db462-6c4a-4108-b0c9-b81b9e474317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495987262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.3495987262
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3988237237
Short name T397
Test name
Test status
Simulation time 322096915208 ps
CPU time 737.31 seconds
Started Mar 31 12:40:39 PM PDT 24
Finished Mar 31 12:52:57 PM PDT 24
Peak memory 201820 kb
Host smart-2006421a-080e-478b-952f-c2403d35e8c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988237237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3988237237
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2693047400
Short name T547
Test name
Test status
Simulation time 326686150488 ps
CPU time 154.06 seconds
Started Mar 31 12:40:38 PM PDT 24
Finished Mar 31 12:43:13 PM PDT 24
Peak memory 201864 kb
Host smart-8a5250c9-3e99-43f3-9444-4862af5017c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693047400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2693047400
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1666206871
Short name T473
Test name
Test status
Simulation time 495577190634 ps
CPU time 1086.87 seconds
Started Mar 31 12:40:31 PM PDT 24
Finished Mar 31 12:58:38 PM PDT 24
Peak memory 201856 kb
Host smart-8b8af795-5a76-49c5-ae34-3a2731a0c997
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666206871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1666206871
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3456412197
Short name T96
Test name
Test status
Simulation time 287169671798 ps
CPU time 628.06 seconds
Started Mar 31 12:40:41 PM PDT 24
Finished Mar 31 12:51:09 PM PDT 24
Peak memory 201896 kb
Host smart-4378bb63-0e1b-49b7-8215-802213a8e4f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456412197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.3456412197
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.338094880
Short name T361
Test name
Test status
Simulation time 595961127377 ps
CPU time 374.11 seconds
Started Mar 31 12:40:35 PM PDT 24
Finished Mar 31 12:46:50 PM PDT 24
Peak memory 201780 kb
Host smart-1ed4450f-9ad9-484e-8e44-d5fa772b795f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338094880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.338094880
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.266770645
Short name T688
Test name
Test status
Simulation time 74307438422 ps
CPU time 260.69 seconds
Started Mar 31 12:40:46 PM PDT 24
Finished Mar 31 12:45:07 PM PDT 24
Peak memory 202136 kb
Host smart-5de892c9-cc29-4221-b203-aea7419871ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266770645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.266770645
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.676690385
Short name T509
Test name
Test status
Simulation time 22007545703 ps
CPU time 31.9 seconds
Started Mar 31 12:40:39 PM PDT 24
Finished Mar 31 12:41:12 PM PDT 24
Peak memory 201700 kb
Host smart-2653e30f-73e9-42db-accd-eede4c9319f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676690385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.676690385
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1858416359
Short name T793
Test name
Test status
Simulation time 3104947222 ps
CPU time 7.58 seconds
Started Mar 31 12:40:40 PM PDT 24
Finished Mar 31 12:40:48 PM PDT 24
Peak memory 201620 kb
Host smart-19d89ccc-56d1-4a28-9378-3e21e4822d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858416359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1858416359
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2729302180
Short name T489
Test name
Test status
Simulation time 5816560088 ps
CPU time 15.37 seconds
Started Mar 31 12:40:41 PM PDT 24
Finished Mar 31 12:40:56 PM PDT 24
Peak memory 201628 kb
Host smart-bdc3639f-6e50-40ed-afe1-791184b1c5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729302180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2729302180
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1328873790
Short name T785
Test name
Test status
Simulation time 326730621313 ps
CPU time 134.79 seconds
Started Mar 31 12:40:37 PM PDT 24
Finished Mar 31 12:42:52 PM PDT 24
Peak memory 201876 kb
Host smart-fe5c17a3-5a02-4548-9557-bde835e3af27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328873790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1328873790
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.2321687063
Short name T19
Test name
Test status
Simulation time 67935645317 ps
CPU time 129.42 seconds
Started Mar 31 12:40:38 PM PDT 24
Finished Mar 31 12:42:47 PM PDT 24
Peak memory 210220 kb
Host smart-0bb17ce7-484b-4232-ba89-d2d28a8734c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321687063 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.2321687063
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.1760811705
Short name T751
Test name
Test status
Simulation time 416371680 ps
CPU time 1.53 seconds
Started Mar 31 12:40:40 PM PDT 24
Finished Mar 31 12:40:42 PM PDT 24
Peak memory 201564 kb
Host smart-d7fa7b71-60aa-4606-9f23-b44a8da91a36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760811705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1760811705
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.3213706105
Short name T530
Test name
Test status
Simulation time 382203208610 ps
CPU time 234.03 seconds
Started Mar 31 12:40:36 PM PDT 24
Finished Mar 31 12:44:31 PM PDT 24
Peak memory 201988 kb
Host smart-ad23e5a4-3803-4fdd-97c2-460435251dc4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213706105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.3213706105
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2199430310
Short name T179
Test name
Test status
Simulation time 558725793654 ps
CPU time 155.68 seconds
Started Mar 31 12:40:36 PM PDT 24
Finished Mar 31 12:43:12 PM PDT 24
Peak memory 201840 kb
Host smart-210903f2-512a-4ac8-a9b5-6623a993cd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199430310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2199430310
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.782589805
Short name T156
Test name
Test status
Simulation time 328334563463 ps
CPU time 570.58 seconds
Started Mar 31 12:40:35 PM PDT 24
Finished Mar 31 12:50:06 PM PDT 24
Peak memory 201860 kb
Host smart-71f4f01b-4aa7-4c60-8e9d-749426d106ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782589805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.782589805
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1889604459
Short name T517
Test name
Test status
Simulation time 169661112045 ps
CPU time 106.44 seconds
Started Mar 31 12:40:37 PM PDT 24
Finished Mar 31 12:42:24 PM PDT 24
Peak memory 201884 kb
Host smart-8ebdc003-3184-4443-a9e7-e3d9db110b92
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889604459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1889604459
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3542043752
Short name T624
Test name
Test status
Simulation time 502528383009 ps
CPU time 118.92 seconds
Started Mar 31 12:40:42 PM PDT 24
Finished Mar 31 12:42:41 PM PDT 24
Peak memory 201868 kb
Host smart-77208ba3-c5ac-4a88-8770-51e07191fc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542043752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3542043752
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2265419374
Short name T762
Test name
Test status
Simulation time 165963756612 ps
CPU time 374.92 seconds
Started Mar 31 12:40:37 PM PDT 24
Finished Mar 31 12:46:52 PM PDT 24
Peak memory 201868 kb
Host smart-56027e43-d370-4e9e-9ee1-04dd667906d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265419374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2265419374
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.423309640
Short name T656
Test name
Test status
Simulation time 170884746229 ps
CPU time 102.49 seconds
Started Mar 31 12:40:41 PM PDT 24
Finished Mar 31 12:42:23 PM PDT 24
Peak memory 201900 kb
Host smart-36f96f09-60cb-4368-aa96-ba9b3ecc8586
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423309640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_
wakeup.423309640
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1729616098
Short name T521
Test name
Test status
Simulation time 208161154012 ps
CPU time 114.96 seconds
Started Mar 31 12:40:39 PM PDT 24
Finished Mar 31 12:42:35 PM PDT 24
Peak memory 201852 kb
Host smart-8359b8a3-dd53-4243-b892-36ebcfa2c09f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729616098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1729616098
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.644682709
Short name T205
Test name
Test status
Simulation time 122624615666 ps
CPU time 449.67 seconds
Started Mar 31 12:40:41 PM PDT 24
Finished Mar 31 12:48:12 PM PDT 24
Peak memory 202236 kb
Host smart-47744a14-a9bb-42a0-aba0-af3445a341a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644682709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.644682709
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3936774580
Short name T343
Test name
Test status
Simulation time 40089215427 ps
CPU time 24.76 seconds
Started Mar 31 12:40:39 PM PDT 24
Finished Mar 31 12:41:04 PM PDT 24
Peak memory 201624 kb
Host smart-79653452-5040-4f64-98b3-2f4f54108db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936774580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3936774580
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.2394761737
Short name T432
Test name
Test status
Simulation time 3979485453 ps
CPU time 9.87 seconds
Started Mar 31 12:40:38 PM PDT 24
Finished Mar 31 12:40:48 PM PDT 24
Peak memory 201684 kb
Host smart-a4b2e1f5-74c5-40cc-a346-d725a95d5ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394761737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.2394761737
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3975537802
Short name T190
Test name
Test status
Simulation time 5602799579 ps
CPU time 13 seconds
Started Mar 31 12:40:39 PM PDT 24
Finished Mar 31 12:40:53 PM PDT 24
Peak memory 201672 kb
Host smart-421f991f-e6ad-463f-a9d1-ba692c9532ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975537802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3975537802
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.546127237
Short name T757
Test name
Test status
Simulation time 9849441959 ps
CPU time 6.53 seconds
Started Mar 31 12:40:45 PM PDT 24
Finished Mar 31 12:40:52 PM PDT 24
Peak memory 201632 kb
Host smart-53a9b15f-d74f-4085-82d0-9bf00ea13bfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546127237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.
546127237
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3612881514
Short name T768
Test name
Test status
Simulation time 752081559837 ps
CPU time 95.96 seconds
Started Mar 31 12:40:37 PM PDT 24
Finished Mar 31 12:42:14 PM PDT 24
Peak memory 210168 kb
Host smart-a742a6d7-1d1c-4d74-acea-4ee0769d3777
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612881514 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.3612881514
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.282197585
Short name T468
Test name
Test status
Simulation time 505510178 ps
CPU time 0.77 seconds
Started Mar 31 12:40:47 PM PDT 24
Finished Mar 31 12:40:48 PM PDT 24
Peak memory 201568 kb
Host smart-5c5627f9-d820-465d-bc6a-6506858b4d3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282197585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.282197585
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.4259269030
Short name T514
Test name
Test status
Simulation time 493339756114 ps
CPU time 1186.32 seconds
Started Mar 31 12:40:36 PM PDT 24
Finished Mar 31 01:00:22 PM PDT 24
Peak memory 201792 kb
Host smart-1ad6c766-af19-406f-ae6d-0d6a75cb64a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259269030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.4259269030
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.124542271
Short name T177
Test name
Test status
Simulation time 320409817668 ps
CPU time 185.35 seconds
Started Mar 31 12:40:41 PM PDT 24
Finished Mar 31 12:43:46 PM PDT 24
Peak memory 201884 kb
Host smart-29e249d5-b028-400c-a6ae-a2564173cb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124542271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.124542271
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.685889166
Short name T364
Test name
Test status
Simulation time 486858542675 ps
CPU time 208.72 seconds
Started Mar 31 12:40:36 PM PDT 24
Finished Mar 31 12:44:05 PM PDT 24
Peak memory 201824 kb
Host smart-3d6351d0-871f-458f-a6af-7efd9c359e0d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=685889166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.685889166
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3919307175
Short name T2
Test name
Test status
Simulation time 509458965921 ps
CPU time 316.72 seconds
Started Mar 31 12:40:40 PM PDT 24
Finished Mar 31 12:45:58 PM PDT 24
Peak memory 201860 kb
Host smart-20ecfef2-dd87-4f79-b773-b0bbff85e842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919307175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3919307175
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1211491728
Short name T746
Test name
Test status
Simulation time 163096146250 ps
CPU time 121.89 seconds
Started Mar 31 12:40:39 PM PDT 24
Finished Mar 31 12:42:42 PM PDT 24
Peak memory 201816 kb
Host smart-defb89da-fffe-479f-95b2-5280d717adaa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211491728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1211491728
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1943272429
Short name T178
Test name
Test status
Simulation time 438714899521 ps
CPU time 263.44 seconds
Started Mar 31 12:40:36 PM PDT 24
Finished Mar 31 12:44:59 PM PDT 24
Peak memory 201828 kb
Host smart-e4b28d84-bb4d-4d28-8dec-0b20094fc81a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943272429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1943272429
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.803778041
Short name T743
Test name
Test status
Simulation time 596761077752 ps
CPU time 722.5 seconds
Started Mar 31 12:40:39 PM PDT 24
Finished Mar 31 12:52:42 PM PDT 24
Peak memory 201852 kb
Host smart-fb96c38b-53d0-4f5b-ba3e-b55e7be54f75
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803778041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.803778041
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2565311974
Short name T429
Test name
Test status
Simulation time 112496523557 ps
CPU time 455.24 seconds
Started Mar 31 12:40:46 PM PDT 24
Finished Mar 31 12:48:22 PM PDT 24
Peak memory 202036 kb
Host smart-8ce47619-5b02-4039-9bef-1e77a0cd3d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565311974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2565311974
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.2805872242
Short name T608
Test name
Test status
Simulation time 43921140975 ps
CPU time 103.2 seconds
Started Mar 31 12:40:51 PM PDT 24
Finished Mar 31 12:42:34 PM PDT 24
Peak memory 201620 kb
Host smart-ddd8b912-576e-4f3d-9e45-cc64b4fa19f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805872242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.2805872242
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3371130727
Short name T577
Test name
Test status
Simulation time 5129782087 ps
CPU time 11.96 seconds
Started Mar 31 12:40:36 PM PDT 24
Finished Mar 31 12:40:49 PM PDT 24
Peak memory 201632 kb
Host smart-828a790e-129c-41c1-b0ba-c2afb750cf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371130727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3371130727
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.3721553486
Short name T451
Test name
Test status
Simulation time 6029296139 ps
CPU time 3.04 seconds
Started Mar 31 12:40:41 PM PDT 24
Finished Mar 31 12:40:45 PM PDT 24
Peak memory 201620 kb
Host smart-a9eecbab-f482-4cd4-942a-4bbb91d4443e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721553486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.3721553486
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.3830722666
Short name T696
Test name
Test status
Simulation time 415236273 ps
CPU time 0.87 seconds
Started Mar 31 12:40:45 PM PDT 24
Finished Mar 31 12:40:47 PM PDT 24
Peak memory 201524 kb
Host smart-9ebf3091-1c67-420b-9779-edc343ea6969
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830722666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3830722666
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.1267128492
Short name T586
Test name
Test status
Simulation time 484560569710 ps
CPU time 288.13 seconds
Started Mar 31 12:40:47 PM PDT 24
Finished Mar 31 12:45:36 PM PDT 24
Peak memory 201772 kb
Host smart-ff88064b-6e8c-4cc2-a67e-370e27566f0d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267128492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.1267128492
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.1126153779
Short name T187
Test name
Test status
Simulation time 332456250261 ps
CPU time 206.35 seconds
Started Mar 31 12:40:44 PM PDT 24
Finished Mar 31 12:44:10 PM PDT 24
Peak memory 201800 kb
Host smart-ba2e7cff-5698-479a-885f-a3105d3cd106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126153779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1126153779
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.3999957128
Short name T510
Test name
Test status
Simulation time 158809065245 ps
CPU time 370.96 seconds
Started Mar 31 12:40:47 PM PDT 24
Finished Mar 31 12:46:59 PM PDT 24
Peak memory 201736 kb
Host smart-440dfa67-2ea5-4637-8a76-baf88c921ce1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999957128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.3999957128
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.2457010700
Short name T603
Test name
Test status
Simulation time 588664618979 ps
CPU time 389.49 seconds
Started Mar 31 12:40:50 PM PDT 24
Finished Mar 31 12:47:20 PM PDT 24
Peak memory 201888 kb
Host smart-da36a439-a6b2-474a-9674-3097f134cf5c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457010700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.2457010700
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3337189098
Short name T686
Test name
Test status
Simulation time 117040595523 ps
CPU time 589.41 seconds
Started Mar 31 12:40:52 PM PDT 24
Finished Mar 31 12:50:41 PM PDT 24
Peak memory 202112 kb
Host smart-533ddca0-a104-43a9-b351-4ca6bb5976de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337189098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3337189098
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.2479481032
Short name T481
Test name
Test status
Simulation time 38768096555 ps
CPU time 29.87 seconds
Started Mar 31 12:40:45 PM PDT 24
Finished Mar 31 12:41:15 PM PDT 24
Peak memory 201636 kb
Host smart-1128316e-80f8-470e-9334-126e524e8c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479481032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.2479481032
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2987465365
Short name T749
Test name
Test status
Simulation time 4935692908 ps
CPU time 3.83 seconds
Started Mar 31 12:40:51 PM PDT 24
Finished Mar 31 12:40:55 PM PDT 24
Peak memory 201696 kb
Host smart-ca3a3fc1-9751-4f70-8e32-f7799cad1fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987465365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2987465365
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.3612675130
Short name T645
Test name
Test status
Simulation time 5818351888 ps
CPU time 7.76 seconds
Started Mar 31 12:40:44 PM PDT 24
Finished Mar 31 12:40:53 PM PDT 24
Peak memory 201656 kb
Host smart-d3db4313-b1fb-4bbd-880f-b6294f706472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612675130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3612675130
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.239075419
Short name T424
Test name
Test status
Simulation time 9395798623 ps
CPU time 11.57 seconds
Started Mar 31 12:40:42 PM PDT 24
Finished Mar 31 12:40:54 PM PDT 24
Peak memory 201720 kb
Host smart-3c03b562-e4c5-47a6-aaf7-d4995fac68f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239075419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
239075419
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3051020904
Short name T276
Test name
Test status
Simulation time 12947118112 ps
CPU time 36.88 seconds
Started Mar 31 12:40:43 PM PDT 24
Finished Mar 31 12:41:20 PM PDT 24
Peak memory 210468 kb
Host smart-470f8e75-bbfc-40fc-b2e7-386979dff05e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051020904 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3051020904
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1724288645
Short name T503
Test name
Test status
Simulation time 507458618 ps
CPU time 0.9 seconds
Started Mar 31 12:40:50 PM PDT 24
Finished Mar 31 12:40:51 PM PDT 24
Peak memory 201544 kb
Host smart-e4680ca5-5e36-4226-b1f6-45c63e97a3ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724288645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1724288645
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.4113703442
Short name T182
Test name
Test status
Simulation time 332402420822 ps
CPU time 162.94 seconds
Started Mar 31 12:40:50 PM PDT 24
Finished Mar 31 12:43:33 PM PDT 24
Peak memory 201824 kb
Host smart-eccfafc5-f8e2-4973-a64e-613cb610e164
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113703442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.4113703442
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.386850908
Short name T612
Test name
Test status
Simulation time 332083442515 ps
CPU time 817.99 seconds
Started Mar 31 12:40:44 PM PDT 24
Finished Mar 31 12:54:22 PM PDT 24
Peak memory 201880 kb
Host smart-1ebc6e3f-7d0f-4b29-ad94-1652cc657255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386850908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.386850908
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.4213958813
Short name T553
Test name
Test status
Simulation time 328907862441 ps
CPU time 210.64 seconds
Started Mar 31 12:40:44 PM PDT 24
Finished Mar 31 12:44:15 PM PDT 24
Peak memory 201824 kb
Host smart-d74d74fc-404f-492d-bac1-07fa2f94b3fd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213958813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.4213958813
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.535999575
Short name T352
Test name
Test status
Simulation time 163940961810 ps
CPU time 88.59 seconds
Started Mar 31 12:40:46 PM PDT 24
Finished Mar 31 12:42:15 PM PDT 24
Peak memory 201852 kb
Host smart-eb48a476-36c1-40e5-9cb6-d73191b0f668
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=535999575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixe
d.535999575
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.1453853015
Short name T552
Test name
Test status
Simulation time 373645704826 ps
CPU time 561.76 seconds
Started Mar 31 12:40:52 PM PDT 24
Finished Mar 31 12:50:13 PM PDT 24
Peak memory 201820 kb
Host smart-05203409-63e7-4730-bb4d-3fee0ab79829
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453853015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.1453853015
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1349270435
Short name T754
Test name
Test status
Simulation time 194393626328 ps
CPU time 39.94 seconds
Started Mar 31 12:40:43 PM PDT 24
Finished Mar 31 12:41:23 PM PDT 24
Peak memory 201832 kb
Host smart-576694ee-041d-4755-9a35-86f6cacb90f0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349270435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1349270435
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2465824201
Short name T327
Test name
Test status
Simulation time 128795524636 ps
CPU time 542.02 seconds
Started Mar 31 12:40:49 PM PDT 24
Finished Mar 31 12:49:51 PM PDT 24
Peak memory 202248 kb
Host smart-2ef8db71-997f-43fe-9dd4-166294e07fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465824201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2465824201
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1454122133
Short name T662
Test name
Test status
Simulation time 24919798029 ps
CPU time 13.98 seconds
Started Mar 31 12:40:44 PM PDT 24
Finished Mar 31 12:40:59 PM PDT 24
Peak memory 201580 kb
Host smart-64285579-8868-4b0b-83ab-ba37bf46ced4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454122133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1454122133
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.131510148
Short name T136
Test name
Test status
Simulation time 2800247232 ps
CPU time 3.91 seconds
Started Mar 31 12:40:50 PM PDT 24
Finished Mar 31 12:40:54 PM PDT 24
Peak memory 201664 kb
Host smart-8d22387b-4329-4538-bc2b-068aec99bd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131510148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.131510148
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3995601979
Short name T790
Test name
Test status
Simulation time 5964066175 ps
CPU time 7.36 seconds
Started Mar 31 12:40:43 PM PDT 24
Finished Mar 31 12:40:51 PM PDT 24
Peak memory 201688 kb
Host smart-9a3ce7e7-bb11-485a-b6ba-a2caebd7189b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995601979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3995601979
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1676423098
Short name T777
Test name
Test status
Simulation time 15343079177 ps
CPU time 38.34 seconds
Started Mar 31 12:40:52 PM PDT 24
Finished Mar 31 12:41:30 PM PDT 24
Peak memory 201864 kb
Host smart-1c750689-e689-4da4-8a75-817a5dd446df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676423098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1676423098
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.3593844370
Short name T716
Test name
Test status
Simulation time 278793095410 ps
CPU time 255.6 seconds
Started Mar 31 12:40:52 PM PDT 24
Finished Mar 31 12:45:07 PM PDT 24
Peak memory 218616 kb
Host smart-a025143c-7a8f-4e8a-9620-41ec1ee8b820
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593844370 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.3593844370
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.354166314
Short name T418
Test name
Test status
Simulation time 456351061 ps
CPU time 0.84 seconds
Started Mar 31 12:40:51 PM PDT 24
Finished Mar 31 12:40:52 PM PDT 24
Peak memory 201576 kb
Host smart-19373d7a-2a2a-46ed-8c7a-25fadce5eeb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354166314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.354166314
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3644549471
Short name T226
Test name
Test status
Simulation time 350523823623 ps
CPU time 232.18 seconds
Started Mar 31 12:40:53 PM PDT 24
Finished Mar 31 12:44:46 PM PDT 24
Peak memory 201896 kb
Host smart-a3b042f2-f541-473b-a6d4-4365d6393333
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644549471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3644549471
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.425392444
Short name T308
Test name
Test status
Simulation time 504846796523 ps
CPU time 305.09 seconds
Started Mar 31 12:40:52 PM PDT 24
Finished Mar 31 12:45:58 PM PDT 24
Peak memory 201948 kb
Host smart-c4d0e734-16b6-4675-a321-37492c28188b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425392444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.425392444
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3239757842
Short name T357
Test name
Test status
Simulation time 487026616343 ps
CPU time 291.12 seconds
Started Mar 31 12:40:49 PM PDT 24
Finished Mar 31 12:45:41 PM PDT 24
Peak memory 201756 kb
Host smart-992374d1-9bb2-4430-9137-5bc87242faf6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239757842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3239757842
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3485466256
Short name T164
Test name
Test status
Simulation time 494155632574 ps
CPU time 284.21 seconds
Started Mar 31 12:40:48 PM PDT 24
Finished Mar 31 12:45:33 PM PDT 24
Peak memory 201940 kb
Host smart-936c5d75-b76f-4a7b-b2f2-de870f086e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485466256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3485466256
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.3866943494
Short name T483
Test name
Test status
Simulation time 335774976584 ps
CPU time 726.39 seconds
Started Mar 31 12:40:50 PM PDT 24
Finished Mar 31 12:52:56 PM PDT 24
Peak memory 201824 kb
Host smart-1c74bb49-ae11-4901-8fd2-4594c6464fee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866943494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.3866943494
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3112140037
Short name T386
Test name
Test status
Simulation time 171053273256 ps
CPU time 174.54 seconds
Started Mar 31 12:40:51 PM PDT 24
Finished Mar 31 12:43:45 PM PDT 24
Peak memory 201888 kb
Host smart-c7f23b4b-02f6-43f4-bc9f-49d01d322c76
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112140037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3112140037
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3684887210
Short name T670
Test name
Test status
Simulation time 422366231887 ps
CPU time 803.3 seconds
Started Mar 31 12:40:50 PM PDT 24
Finished Mar 31 12:54:14 PM PDT 24
Peak memory 201868 kb
Host smart-e91bcf0a-58f7-4412-adcf-6eae806a3173
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684887210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3684887210
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1950273860
Short name T392
Test name
Test status
Simulation time 75312340748 ps
CPU time 267.74 seconds
Started Mar 31 12:40:52 PM PDT 24
Finished Mar 31 12:45:20 PM PDT 24
Peak memory 202256 kb
Host smart-d6db42ef-e5b5-4e14-b2e5-70e20df40ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950273860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1950273860
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3421389098
Short name T614
Test name
Test status
Simulation time 24417558343 ps
CPU time 29.43 seconds
Started Mar 31 12:40:53 PM PDT 24
Finished Mar 31 12:41:23 PM PDT 24
Peak memory 201704 kb
Host smart-44208641-a298-41f4-8505-cd93fc5408bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421389098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3421389098
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.196848754
Short name T606
Test name
Test status
Simulation time 3465481221 ps
CPU time 2.23 seconds
Started Mar 31 12:40:52 PM PDT 24
Finished Mar 31 12:40:54 PM PDT 24
Peak memory 201692 kb
Host smart-b3077358-f85d-411f-aa62-c889c71b0a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196848754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.196848754
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2229024972
Short name T703
Test name
Test status
Simulation time 5997055262 ps
CPU time 13.12 seconds
Started Mar 31 12:40:50 PM PDT 24
Finished Mar 31 12:41:03 PM PDT 24
Peak memory 201656 kb
Host smart-6fc2e455-6887-4e6c-b530-2d107ef0d751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229024972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2229024972
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.623369061
Short name T791
Test name
Test status
Simulation time 106690635882 ps
CPU time 533.17 seconds
Started Mar 31 12:40:48 PM PDT 24
Finished Mar 31 12:49:42 PM PDT 24
Peak memory 202188 kb
Host smart-e098ec9c-a6fe-413a-9010-cd28ef303cf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623369061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.
623369061
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1294436232
Short name T449
Test name
Test status
Simulation time 447191225 ps
CPU time 0.82 seconds
Started Mar 31 12:40:56 PM PDT 24
Finished Mar 31 12:40:57 PM PDT 24
Peak memory 201500 kb
Host smart-98ff7281-71f3-425a-9227-082046bc6378
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294436232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1294436232
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.2667160848
Short name T714
Test name
Test status
Simulation time 535619603881 ps
CPU time 431.42 seconds
Started Mar 31 12:40:52 PM PDT 24
Finished Mar 31 12:48:03 PM PDT 24
Peak memory 201864 kb
Host smart-6a654546-ad3d-406b-8341-2e6019410f24
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667160848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.2667160848
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.3570086842
Short name T295
Test name
Test status
Simulation time 340403413979 ps
CPU time 389.96 seconds
Started Mar 31 12:40:50 PM PDT 24
Finished Mar 31 12:47:21 PM PDT 24
Peak memory 201888 kb
Host smart-d5d1443b-1c5b-4736-b9e2-80bbab560269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570086842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3570086842
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.823348797
Short name T176
Test name
Test status
Simulation time 487024564409 ps
CPU time 286.8 seconds
Started Mar 31 12:40:51 PM PDT 24
Finished Mar 31 12:45:38 PM PDT 24
Peak memory 201780 kb
Host smart-33a494d9-592b-430b-bba1-a2e596c6e92c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=823348797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.823348797
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.456487465
Short name T303
Test name
Test status
Simulation time 332967809119 ps
CPU time 748.36 seconds
Started Mar 31 12:40:55 PM PDT 24
Finished Mar 31 12:53:23 PM PDT 24
Peak memory 201952 kb
Host smart-4c6ed555-7926-46e8-95d6-1991083be0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456487465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.456487465
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.1368504436
Short name T475
Test name
Test status
Simulation time 161829870626 ps
CPU time 102.98 seconds
Started Mar 31 12:40:49 PM PDT 24
Finished Mar 31 12:42:32 PM PDT 24
Peak memory 201896 kb
Host smart-75e93443-b500-4f82-b7cb-a9d9326d9ebe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368504436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.1368504436
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.767440938
Short name T478
Test name
Test status
Simulation time 181600057352 ps
CPU time 59.35 seconds
Started Mar 31 12:40:53 PM PDT 24
Finished Mar 31 12:41:52 PM PDT 24
Peak memory 201912 kb
Host smart-bb6bd0c2-35b3-4d36-8f4e-3d6c1839f972
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767440938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_
wakeup.767440938
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2676918605
Short name T376
Test name
Test status
Simulation time 201042172547 ps
CPU time 120.72 seconds
Started Mar 31 12:40:49 PM PDT 24
Finished Mar 31 12:42:50 PM PDT 24
Peak memory 201820 kb
Host smart-7bf95bd6-f4f1-4099-8f88-9b4d6f1cab95
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676918605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2676918605
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.3590763046
Short name T707
Test name
Test status
Simulation time 115600268880 ps
CPU time 649.39 seconds
Started Mar 31 12:40:58 PM PDT 24
Finished Mar 31 12:51:48 PM PDT 24
Peak memory 202236 kb
Host smart-d10c7fd6-b107-4699-be1d-3c360950293f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590763046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.3590763046
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.3107939718
Short name T393
Test name
Test status
Simulation time 41976952553 ps
CPU time 26.36 seconds
Started Mar 31 12:40:57 PM PDT 24
Finished Mar 31 12:41:24 PM PDT 24
Peak memory 201652 kb
Host smart-4be16441-4909-4dd4-ac9d-70146ab388e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107939718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3107939718
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.3918111198
Short name T447
Test name
Test status
Simulation time 3947361248 ps
CPU time 2.99 seconds
Started Mar 31 12:40:57 PM PDT 24
Finished Mar 31 12:41:00 PM PDT 24
Peak memory 201644 kb
Host smart-7f4f5bec-fd74-44cf-90b0-fc3f2dc48bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918111198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.3918111198
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2739970540
Short name T704
Test name
Test status
Simulation time 5637936620 ps
CPU time 14.9 seconds
Started Mar 31 12:40:52 PM PDT 24
Finished Mar 31 12:41:07 PM PDT 24
Peak memory 201664 kb
Host smart-e5826089-de92-494c-b1bf-f003383e6fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739970540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2739970540
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.2510214951
Short name T772
Test name
Test status
Simulation time 327174632853 ps
CPU time 770.4 seconds
Started Mar 31 12:40:57 PM PDT 24
Finished Mar 31 12:53:47 PM PDT 24
Peak memory 201872 kb
Host smart-3c0c3ebf-dcf3-4968-ba52-fb949892813a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510214951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.2510214951
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.276250178
Short name T255
Test name
Test status
Simulation time 368584538292 ps
CPU time 402.78 seconds
Started Mar 31 12:40:56 PM PDT 24
Finished Mar 31 12:47:39 PM PDT 24
Peak memory 210532 kb
Host smart-24bcf09c-053d-4680-9778-402f2d5c1e62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276250178 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.276250178
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.3150720320
Short name T529
Test name
Test status
Simulation time 541422808 ps
CPU time 0.88 seconds
Started Mar 31 12:41:02 PM PDT 24
Finished Mar 31 12:41:03 PM PDT 24
Peak memory 201464 kb
Host smart-efdbb371-07d7-49d0-bb61-47c8b352b9e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150720320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.3150720320
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.775531921
Short name T541
Test name
Test status
Simulation time 349267971674 ps
CPU time 390.27 seconds
Started Mar 31 12:40:53 PM PDT 24
Finished Mar 31 12:47:24 PM PDT 24
Peak memory 201824 kb
Host smart-cf443f9b-3dc1-45bb-bdac-a04987a53d1c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775531921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gati
ng.775531921
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.368092641
Short name T316
Test name
Test status
Simulation time 516884131638 ps
CPU time 219.65 seconds
Started Mar 31 12:40:59 PM PDT 24
Finished Mar 31 12:44:39 PM PDT 24
Peak memory 201812 kb
Host smart-2049d5f0-3156-471b-95d1-24bfa2a3a3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368092641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.368092641
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.760271720
Short name T321
Test name
Test status
Simulation time 324603914559 ps
CPU time 364.49 seconds
Started Mar 31 12:40:54 PM PDT 24
Finished Mar 31 12:46:59 PM PDT 24
Peak memory 201800 kb
Host smart-6168a7d5-333f-4bb0-aeb4-b049fae0a707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760271720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.760271720
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1278776807
Short name T794
Test name
Test status
Simulation time 163555126238 ps
CPU time 390.65 seconds
Started Mar 31 12:40:57 PM PDT 24
Finished Mar 31 12:47:28 PM PDT 24
Peak memory 201712 kb
Host smart-9a36e770-96dc-4fc6-9095-97f44d361984
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278776807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1278776807
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.4242906091
Short name T723
Test name
Test status
Simulation time 332605430687 ps
CPU time 188.58 seconds
Started Mar 31 12:40:57 PM PDT 24
Finished Mar 31 12:44:05 PM PDT 24
Peak memory 201796 kb
Host smart-ed59485c-a429-469b-b2f6-f3080189943b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242906091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.4242906091
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.814418396
Short name T693
Test name
Test status
Simulation time 323713667494 ps
CPU time 761.02 seconds
Started Mar 31 12:40:57 PM PDT 24
Finished Mar 31 12:53:38 PM PDT 24
Peak memory 201752 kb
Host smart-0638b994-011c-4891-bcce-29f762b68e1e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=814418396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe
d.814418396
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.941501615
Short name T373
Test name
Test status
Simulation time 407472972327 ps
CPU time 927.33 seconds
Started Mar 31 12:40:58 PM PDT 24
Finished Mar 31 12:56:26 PM PDT 24
Peak memory 201852 kb
Host smart-db0bec22-9c11-48f4-b3e1-cbb9c9202955
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941501615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.941501615
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3247085858
Short name T195
Test name
Test status
Simulation time 99815576762 ps
CPU time 446.53 seconds
Started Mar 31 12:41:05 PM PDT 24
Finished Mar 31 12:48:31 PM PDT 24
Peak memory 202100 kb
Host smart-bdbb7e89-9c99-422c-8979-b5c953e1c5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247085858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3247085858
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.852328092
Short name T642
Test name
Test status
Simulation time 38689864026 ps
CPU time 42.28 seconds
Started Mar 31 12:41:02 PM PDT 24
Finished Mar 31 12:41:44 PM PDT 24
Peak memory 201672 kb
Host smart-93f78847-7cda-4dc4-8117-bcf548fa5c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852328092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.852328092
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.4193402753
Short name T351
Test name
Test status
Simulation time 4100057551 ps
CPU time 10.67 seconds
Started Mar 31 12:41:02 PM PDT 24
Finished Mar 31 12:41:13 PM PDT 24
Peak memory 201700 kb
Host smart-e95acccc-90ef-408b-9840-458ce588c8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193402753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.4193402753
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.3854940354
Short name T767
Test name
Test status
Simulation time 5785446662 ps
CPU time 4.72 seconds
Started Mar 31 12:40:57 PM PDT 24
Finished Mar 31 12:41:02 PM PDT 24
Peak memory 201716 kb
Host smart-43dcb3d9-d9af-488e-9c2b-7f787c504b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854940354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.3854940354
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1659605113
Short name T745
Test name
Test status
Simulation time 25579643230 ps
CPU time 62.51 seconds
Started Mar 31 12:41:02 PM PDT 24
Finished Mar 31 12:42:05 PM PDT 24
Peak memory 211292 kb
Host smart-91733df9-28d4-4423-b0e5-b7f9eb3f2645
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659605113 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1659605113
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.608879930
Short name T717
Test name
Test status
Simulation time 511079777 ps
CPU time 1.77 seconds
Started Mar 31 12:41:09 PM PDT 24
Finished Mar 31 12:41:11 PM PDT 24
Peak memory 201604 kb
Host smart-53e4f4f3-0ccc-4aba-a5d9-6e84864eb9af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608879930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.608879930
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.1981899754
Short name T228
Test name
Test status
Simulation time 166879340893 ps
CPU time 355.8 seconds
Started Mar 31 12:41:04 PM PDT 24
Finished Mar 31 12:47:00 PM PDT 24
Peak memory 201868 kb
Host smart-bdf69385-9fee-47c6-9792-67a60ff5b782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981899754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.1981899754
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.494995971
Short name T31
Test name
Test status
Simulation time 323946060789 ps
CPU time 748.23 seconds
Started Mar 31 12:41:05 PM PDT 24
Finished Mar 31 12:53:33 PM PDT 24
Peak memory 201816 kb
Host smart-615ddeb5-e5bc-4196-af3e-476414443765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494995971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.494995971
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.507647384
Short name T738
Test name
Test status
Simulation time 326058914205 ps
CPU time 189.07 seconds
Started Mar 31 12:41:03 PM PDT 24
Finished Mar 31 12:44:12 PM PDT 24
Peak memory 201868 kb
Host smart-2d9057a7-e485-4693-933d-01a06ba7a926
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=507647384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrup
t_fixed.507647384
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3344484795
Short name T641
Test name
Test status
Simulation time 492359222835 ps
CPU time 306.95 seconds
Started Mar 31 12:41:01 PM PDT 24
Finished Mar 31 12:46:09 PM PDT 24
Peak memory 201912 kb
Host smart-9790eb48-1fca-454b-a4cf-31dc9653bd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344484795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3344484795
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.2449593392
Short name T482
Test name
Test status
Simulation time 495380206353 ps
CPU time 271.4 seconds
Started Mar 31 12:41:03 PM PDT 24
Finished Mar 31 12:45:35 PM PDT 24
Peak memory 201792 kb
Host smart-b14a9fa0-7f19-4071-af97-d6dec02e41ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449593392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.2449593392
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.2207183279
Short name T598
Test name
Test status
Simulation time 395976216391 ps
CPU time 932.69 seconds
Started Mar 31 12:41:05 PM PDT 24
Finished Mar 31 12:56:38 PM PDT 24
Peak memory 201888 kb
Host smart-597a753d-2d10-4166-b5a4-5eb9ef627d5d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207183279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.2207183279
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1485017093
Short name T442
Test name
Test status
Simulation time 589683301289 ps
CPU time 443.01 seconds
Started Mar 31 12:41:04 PM PDT 24
Finished Mar 31 12:48:27 PM PDT 24
Peak memory 201872 kb
Host smart-96daeaeb-52dd-4d48-acae-9e9e5b49062b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485017093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.1485017093
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1413343672
Short name T655
Test name
Test status
Simulation time 111732717795 ps
CPU time 355.42 seconds
Started Mar 31 12:41:08 PM PDT 24
Finished Mar 31 12:47:03 PM PDT 24
Peak memory 202232 kb
Host smart-924d0956-0e25-4a6e-aac2-7da78a37afe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413343672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1413343672
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.992713998
Short name T363
Test name
Test status
Simulation time 44277675392 ps
CPU time 24.87 seconds
Started Mar 31 12:41:05 PM PDT 24
Finished Mar 31 12:41:30 PM PDT 24
Peak memory 201688 kb
Host smart-02a6a493-aaf1-4409-8544-82a203350932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992713998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.992713998
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.2558413004
Short name T685
Test name
Test status
Simulation time 2712333399 ps
CPU time 6.7 seconds
Started Mar 31 12:41:02 PM PDT 24
Finished Mar 31 12:41:09 PM PDT 24
Peak memory 201684 kb
Host smart-c6c4edfa-a339-4255-a4f4-3c2202fb11d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558413004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.2558413004
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1283030597
Short name T739
Test name
Test status
Simulation time 5986512627 ps
CPU time 7.53 seconds
Started Mar 31 12:41:05 PM PDT 24
Finished Mar 31 12:41:12 PM PDT 24
Peak memory 201700 kb
Host smart-18073d14-74c2-4246-832d-162d4f2d2171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283030597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1283030597
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3625270196
Short name T580
Test name
Test status
Simulation time 334415566283 ps
CPU time 814.07 seconds
Started Mar 31 12:41:10 PM PDT 24
Finished Mar 31 12:54:44 PM PDT 24
Peak memory 210292 kb
Host smart-67555d06-351c-411f-9fd7-72f030495684
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625270196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3625270196
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2875760880
Short name T111
Test name
Test status
Simulation time 346282399204 ps
CPU time 163.07 seconds
Started Mar 31 12:41:08 PM PDT 24
Finished Mar 31 12:43:51 PM PDT 24
Peak memory 218708 kb
Host smart-257f03d4-14e9-4cd1-bee8-badae3a3a975
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875760880 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2875760880
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3083192124
Short name T401
Test name
Test status
Simulation time 536141184 ps
CPU time 0.78 seconds
Started Mar 31 12:40:00 PM PDT 24
Finished Mar 31 12:40:01 PM PDT 24
Peak memory 201528 kb
Host smart-fd24991d-c590-4354-adec-083850763fc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083192124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3083192124
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.389558568
Short name T718
Test name
Test status
Simulation time 499026575321 ps
CPU time 94.41 seconds
Started Mar 31 12:40:06 PM PDT 24
Finished Mar 31 12:41:40 PM PDT 24
Peak memory 201804 kb
Host smart-24f15482-3876-45d0-aa3d-827b8aba354f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389558568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gatin
g.389558568
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3285807620
Short name T657
Test name
Test status
Simulation time 167721008330 ps
CPU time 104.53 seconds
Started Mar 31 12:40:11 PM PDT 24
Finished Mar 31 12:41:56 PM PDT 24
Peak memory 201176 kb
Host smart-e12776e1-fb5a-47a4-980b-1462bc574773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285807620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3285807620
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.537653321
Short name T388
Test name
Test status
Simulation time 157978121007 ps
CPU time 376.8 seconds
Started Mar 31 12:40:00 PM PDT 24
Finished Mar 31 12:46:17 PM PDT 24
Peak memory 201796 kb
Host smart-db1b48d4-0f2d-4164-af4c-f296850e6caa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=537653321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt
_fixed.537653321
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.2244013183
Short name T443
Test name
Test status
Simulation time 164023770351 ps
CPU time 381.33 seconds
Started Mar 31 12:40:00 PM PDT 24
Finished Mar 31 12:46:22 PM PDT 24
Peak memory 201764 kb
Host smart-2a364cc8-cf57-4da5-a981-d569ade551c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244013183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.2244013183
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3109659610
Short name T349
Test name
Test status
Simulation time 328055825425 ps
CPU time 790.87 seconds
Started Mar 31 12:40:03 PM PDT 24
Finished Mar 31 12:53:14 PM PDT 24
Peak memory 201880 kb
Host smart-06b5b7d9-4fcd-4614-99a0-981e702670a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109659610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3109659610
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.262301054
Short name T618
Test name
Test status
Simulation time 578449879995 ps
CPU time 343.03 seconds
Started Mar 31 12:39:57 PM PDT 24
Finished Mar 31 12:45:40 PM PDT 24
Peak memory 201860 kb
Host smart-1afa5bae-e3ad-45e1-b5f1-902bb867c132
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262301054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_w
akeup.262301054
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1643573631
Short name T367
Test name
Test status
Simulation time 201719567061 ps
CPU time 238.34 seconds
Started Mar 31 12:40:04 PM PDT 24
Finished Mar 31 12:44:03 PM PDT 24
Peak memory 201796 kb
Host smart-873795b7-8920-45a1-8e4c-50e5b548fcdf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643573631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1643573631
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1871101483
Short name T646
Test name
Test status
Simulation time 145181592687 ps
CPU time 482.73 seconds
Started Mar 31 12:40:00 PM PDT 24
Finished Mar 31 12:48:03 PM PDT 24
Peak memory 202244 kb
Host smart-52273152-93d5-4291-bef6-7b052e3326f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871101483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1871101483
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3154947337
Short name T337
Test name
Test status
Simulation time 31045146722 ps
CPU time 65.64 seconds
Started Mar 31 12:40:02 PM PDT 24
Finished Mar 31 12:41:08 PM PDT 24
Peak memory 201616 kb
Host smart-c836471a-9d98-4eb5-8672-6948a7a559f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154947337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3154947337
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3374438928
Short name T433
Test name
Test status
Simulation time 5417871989 ps
CPU time 3.93 seconds
Started Mar 31 12:40:02 PM PDT 24
Finished Mar 31 12:40:06 PM PDT 24
Peak memory 201684 kb
Host smart-6a5dcda3-a51e-43e0-a67a-3e7e653a501f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374438928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3374438928
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3612908920
Short name T81
Test name
Test status
Simulation time 7964749550 ps
CPU time 5.28 seconds
Started Mar 31 12:40:05 PM PDT 24
Finished Mar 31 12:40:10 PM PDT 24
Peak memory 218452 kb
Host smart-d5fde850-d2b7-4da2-88c1-12f7809f54c8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612908920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3612908920
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.797257465
Short name T425
Test name
Test status
Simulation time 5730798899 ps
CPU time 7.32 seconds
Started Mar 31 12:40:11 PM PDT 24
Finished Mar 31 12:40:20 PM PDT 24
Peak memory 201620 kb
Host smart-e5c92dd4-9134-4e3e-9049-7ba177c41f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797257465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.797257465
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3689111596
Short name T67
Test name
Test status
Simulation time 191150254139 ps
CPU time 590.83 seconds
Started Mar 31 12:39:57 PM PDT 24
Finished Mar 31 12:49:48 PM PDT 24
Peak memory 202196 kb
Host smart-7d902ed6-fca8-4554-b230-c1c70e2f37c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689111596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3689111596
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.3396797268
Short name T52
Test name
Test status
Simulation time 21660469798 ps
CPU time 46.96 seconds
Started Mar 31 12:40:07 PM PDT 24
Finished Mar 31 12:40:54 PM PDT 24
Peak memory 202016 kb
Host smart-5734cead-8f21-4c4a-abf3-2006210ede9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396797268 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.3396797268
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.543140946
Short name T669
Test name
Test status
Simulation time 495839499 ps
CPU time 0.93 seconds
Started Mar 31 12:41:20 PM PDT 24
Finished Mar 31 12:41:21 PM PDT 24
Peak memory 201540 kb
Host smart-8ea7d781-e19c-4be4-b9fd-a6c1993d6fb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543140946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.543140946
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.240829137
Short name T661
Test name
Test status
Simulation time 509278038950 ps
CPU time 356.6 seconds
Started Mar 31 12:41:18 PM PDT 24
Finished Mar 31 12:47:14 PM PDT 24
Peak memory 201852 kb
Host smart-2ceb46fd-62b3-4197-b7ae-2103f93897eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240829137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.240829137
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1028875649
Short name T792
Test name
Test status
Simulation time 322631018555 ps
CPU time 396.31 seconds
Started Mar 31 12:41:17 PM PDT 24
Finished Mar 31 12:47:54 PM PDT 24
Peak memory 201796 kb
Host smart-8c5e971b-a0a1-444b-9872-e90dada9ab79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028875649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1028875649
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3486746830
Short name T407
Test name
Test status
Simulation time 497443576337 ps
CPU time 294.26 seconds
Started Mar 31 12:41:18 PM PDT 24
Finished Mar 31 12:46:12 PM PDT 24
Peak memory 201828 kb
Host smart-795d3e6e-8af7-498b-9ac9-5bce07693719
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486746830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3486746830
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2517951891
Short name T532
Test name
Test status
Simulation time 492847683438 ps
CPU time 546.92 seconds
Started Mar 31 12:41:09 PM PDT 24
Finished Mar 31 12:50:16 PM PDT 24
Peak memory 201864 kb
Host smart-5b6b83db-b49d-4453-8a5a-652d21783b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517951891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2517951891
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2660905901
Short name T46
Test name
Test status
Simulation time 167470023473 ps
CPU time 207.68 seconds
Started Mar 31 12:41:08 PM PDT 24
Finished Mar 31 12:44:35 PM PDT 24
Peak memory 201720 kb
Host smart-49ef7d9b-27c5-456e-9a8f-95b317ba3219
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660905901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2660905901
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3284099667
Short name T175
Test name
Test status
Simulation time 404074697321 ps
CPU time 648.31 seconds
Started Mar 31 12:41:16 PM PDT 24
Finished Mar 31 12:52:05 PM PDT 24
Peak memory 201888 kb
Host smart-cbdd5eec-5c78-4bf8-9570-c35f718002c2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284099667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3284099667
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1929304935
Short name T653
Test name
Test status
Simulation time 87918533569 ps
CPU time 303.32 seconds
Started Mar 31 12:41:17 PM PDT 24
Finished Mar 31 12:46:21 PM PDT 24
Peak memory 202176 kb
Host smart-d864415b-4aec-4df4-9559-6ac7dea7a471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929304935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1929304935
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2101270997
Short name T729
Test name
Test status
Simulation time 25813702655 ps
CPU time 60.66 seconds
Started Mar 31 12:41:15 PM PDT 24
Finished Mar 31 12:42:16 PM PDT 24
Peak memory 201664 kb
Host smart-aea653fe-30b2-41c2-88e7-8bd6ce8497c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101270997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2101270997
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.185335040
Short name T137
Test name
Test status
Simulation time 4901546026 ps
CPU time 12.85 seconds
Started Mar 31 12:41:15 PM PDT 24
Finished Mar 31 12:41:28 PM PDT 24
Peak memory 201676 kb
Host smart-6605ca97-54ca-414c-bd32-214ad15a5d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185335040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.185335040
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.161972650
Short name T527
Test name
Test status
Simulation time 6057404222 ps
CPU time 2.22 seconds
Started Mar 31 12:41:07 PM PDT 24
Finished Mar 31 12:41:10 PM PDT 24
Peak memory 201696 kb
Host smart-bd6950ca-8fa1-4ffc-bcbc-efb3206952bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161972650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.161972650
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.2752802783
Short name T37
Test name
Test status
Simulation time 352330670982 ps
CPU time 66.24 seconds
Started Mar 31 12:41:18 PM PDT 24
Finished Mar 31 12:42:24 PM PDT 24
Peak memory 201940 kb
Host smart-95202376-5c48-4bba-9a18-0267598bccb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752802783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.2752802783
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2155680320
Short name T53
Test name
Test status
Simulation time 49819331201 ps
CPU time 120.16 seconds
Started Mar 31 12:41:14 PM PDT 24
Finished Mar 31 12:43:14 PM PDT 24
Peak memory 210220 kb
Host smart-c204f3d3-f555-46bc-b3d7-d2360456b9bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155680320 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2155680320
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.4264792402
Short name T596
Test name
Test status
Simulation time 468371193 ps
CPU time 1.62 seconds
Started Mar 31 12:41:25 PM PDT 24
Finished Mar 31 12:41:26 PM PDT 24
Peak memory 201580 kb
Host smart-021ba977-cb13-47f3-9cb5-0483fefff5c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264792402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.4264792402
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1169045413
Short name T213
Test name
Test status
Simulation time 178941209790 ps
CPU time 366.21 seconds
Started Mar 31 12:41:25 PM PDT 24
Finished Mar 31 12:47:31 PM PDT 24
Peak memory 201864 kb
Host smart-90830a83-4193-4c6b-91fa-80bafced24cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169045413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1169045413
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.925072382
Short name T796
Test name
Test status
Simulation time 495514230564 ps
CPU time 1167.22 seconds
Started Mar 31 12:41:21 PM PDT 24
Finished Mar 31 01:00:48 PM PDT 24
Peak memory 201952 kb
Host smart-cb19e4c7-f69b-4868-a948-3fbe9a8f21bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925072382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.925072382
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.4091173105
Short name T403
Test name
Test status
Simulation time 320119828494 ps
CPU time 744.7 seconds
Started Mar 31 12:41:23 PM PDT 24
Finished Mar 31 12:53:48 PM PDT 24
Peak memory 201944 kb
Host smart-a828df98-1aee-402e-9277-bd60cae1ff12
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091173105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.4091173105
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2389695995
Short name T281
Test name
Test status
Simulation time 567322668790 ps
CPU time 1283.35 seconds
Started Mar 31 12:41:22 PM PDT 24
Finished Mar 31 01:02:45 PM PDT 24
Peak memory 201864 kb
Host smart-5d0c1dda-8bb5-4e37-9217-12fb9972f359
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389695995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2389695995
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1631571276
Short name T427
Test name
Test status
Simulation time 389214058740 ps
CPU time 630.29 seconds
Started Mar 31 12:41:21 PM PDT 24
Finished Mar 31 12:51:51 PM PDT 24
Peak memory 201852 kb
Host smart-2f81b2ec-d140-4a87-bb3d-84ff81753cdf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631571276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1631571276
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.330490548
Short name T113
Test name
Test status
Simulation time 38928591496 ps
CPU time 7.41 seconds
Started Mar 31 12:41:23 PM PDT 24
Finished Mar 31 12:41:31 PM PDT 24
Peak memory 201624 kb
Host smart-55a08e26-b4cb-4781-8979-fa6647f6a1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330490548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.330490548
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.2644568305
Short name T585
Test name
Test status
Simulation time 3805394344 ps
CPU time 5.09 seconds
Started Mar 31 12:41:24 PM PDT 24
Finished Mar 31 12:41:29 PM PDT 24
Peak memory 201680 kb
Host smart-3209c327-a96f-4574-a1a4-21329c1fe858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644568305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.2644568305
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3465271633
Short name T57
Test name
Test status
Simulation time 6124798527 ps
CPU time 1.42 seconds
Started Mar 31 12:41:20 PM PDT 24
Finished Mar 31 12:41:22 PM PDT 24
Peak memory 201624 kb
Host smart-8c59f815-752d-4174-9840-4b4eb67faba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465271633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3465271633
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.640759274
Short name T16
Test name
Test status
Simulation time 62702882425 ps
CPU time 104.68 seconds
Started Mar 31 12:41:28 PM PDT 24
Finished Mar 31 12:43:12 PM PDT 24
Peak memory 210552 kb
Host smart-a624a305-3464-416f-b5bf-24cd57976c1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640759274 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.640759274
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.44902674
Short name T715
Test name
Test status
Simulation time 373165044 ps
CPU time 0.81 seconds
Started Mar 31 12:41:27 PM PDT 24
Finished Mar 31 12:41:28 PM PDT 24
Peak memory 201504 kb
Host smart-a918f960-0919-447f-a48f-472b822632e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44902674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.44902674
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2335470040
Short name T728
Test name
Test status
Simulation time 516402414316 ps
CPU time 1243.23 seconds
Started Mar 31 12:41:27 PM PDT 24
Finished Mar 31 01:02:11 PM PDT 24
Peak memory 201840 kb
Host smart-a99aab82-c71f-4a51-84d2-a627c220b252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335470040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2335470040
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.415320099
Short name T571
Test name
Test status
Simulation time 329430139747 ps
CPU time 199.92 seconds
Started Mar 31 12:41:26 PM PDT 24
Finished Mar 31 12:44:46 PM PDT 24
Peak memory 201932 kb
Host smart-2ff995ed-f85c-455c-802f-280ba2b5b28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415320099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.415320099
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.216346916
Short name T755
Test name
Test status
Simulation time 170642026999 ps
CPU time 206.14 seconds
Started Mar 31 12:41:27 PM PDT 24
Finished Mar 31 12:44:53 PM PDT 24
Peak memory 201868 kb
Host smart-29f8968d-d736-4a6c-af65-26270974db29
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=216346916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrup
t_fixed.216346916
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2179813406
Short name T8
Test name
Test status
Simulation time 165494775088 ps
CPU time 94.38 seconds
Started Mar 31 12:41:27 PM PDT 24
Finished Mar 31 12:43:01 PM PDT 24
Peak memory 201948 kb
Host smart-a7120fdf-e0c7-43c9-a0ca-1513d71558df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179813406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2179813406
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1617568260
Short name T385
Test name
Test status
Simulation time 327003763881 ps
CPU time 54.08 seconds
Started Mar 31 12:41:29 PM PDT 24
Finished Mar 31 12:42:24 PM PDT 24
Peak memory 201832 kb
Host smart-a33f4a4d-30b6-4ee2-b72e-7930cc30f7a9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617568260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1617568260
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.2979246590
Short name T495
Test name
Test status
Simulation time 198377355217 ps
CPU time 111.45 seconds
Started Mar 31 12:41:27 PM PDT 24
Finished Mar 31 12:43:18 PM PDT 24
Peak memory 201848 kb
Host smart-8cbf978d-259d-4257-acc5-55ac69354170
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979246590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.2979246590
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.589740072
Short name T622
Test name
Test status
Simulation time 202589494924 ps
CPU time 127.96 seconds
Started Mar 31 12:41:27 PM PDT 24
Finished Mar 31 12:43:35 PM PDT 24
Peak memory 201864 kb
Host smart-324dcdd8-5a1f-4e2f-8db9-dae899f2bf91
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589740072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
adc_ctrl_filters_wakeup_fixed.589740072
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2414256562
Short name T404
Test name
Test status
Simulation time 33063947539 ps
CPU time 73.58 seconds
Started Mar 31 12:41:27 PM PDT 24
Finished Mar 31 12:42:40 PM PDT 24
Peak memory 201604 kb
Host smart-ab736d4c-e5c4-466c-a8b5-e9c2c28610bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414256562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2414256562
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.4060131771
Short name T465
Test name
Test status
Simulation time 3278184748 ps
CPU time 7.96 seconds
Started Mar 31 12:41:28 PM PDT 24
Finished Mar 31 12:41:36 PM PDT 24
Peak memory 201640 kb
Host smart-f0827c6f-49a7-4d85-84ba-384e8208b328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060131771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.4060131771
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.3990716052
Short name T485
Test name
Test status
Simulation time 6144780025 ps
CPU time 9.07 seconds
Started Mar 31 12:41:26 PM PDT 24
Finished Mar 31 12:41:35 PM PDT 24
Peak memory 201640 kb
Host smart-b2b3bdd7-7e5b-44ad-97a5-206ea3154516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990716052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.3990716052
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2723552723
Short name T34
Test name
Test status
Simulation time 539684655306 ps
CPU time 1234.58 seconds
Started Mar 31 12:41:26 PM PDT 24
Finished Mar 31 01:02:00 PM PDT 24
Peak memory 201932 kb
Host smart-efac1ac8-c4b8-4a70-b9bf-6c5e9832cda6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723552723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2723552723
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.2864832544
Short name T522
Test name
Test status
Simulation time 424442281 ps
CPU time 0.97 seconds
Started Mar 31 12:41:39 PM PDT 24
Finished Mar 31 12:41:41 PM PDT 24
Peak memory 201520 kb
Host smart-a7404192-157b-4cca-9631-8c29bc49f683
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864832544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.2864832544
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3205287258
Short name T245
Test name
Test status
Simulation time 167909198847 ps
CPU time 389.81 seconds
Started Mar 31 12:41:32 PM PDT 24
Finished Mar 31 12:48:03 PM PDT 24
Peak memory 201952 kb
Host smart-7faaf68f-1686-4b4a-b873-2cf699d5ee6e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205287258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3205287258
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1608121961
Short name T684
Test name
Test status
Simulation time 337485528257 ps
CPU time 863.33 seconds
Started Mar 31 12:41:34 PM PDT 24
Finished Mar 31 12:55:58 PM PDT 24
Peak memory 201876 kb
Host smart-783c2573-1f70-4dcc-8d51-1ae552b1426e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608121961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1608121961
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1404977733
Short name T719
Test name
Test status
Simulation time 163625767917 ps
CPU time 398.31 seconds
Started Mar 31 12:41:33 PM PDT 24
Finished Mar 31 12:48:11 PM PDT 24
Peak memory 201812 kb
Host smart-65d593ab-54eb-464c-b851-ae0f35bf19d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404977733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1404977733
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.513848378
Short name T412
Test name
Test status
Simulation time 324240439989 ps
CPU time 697.88 seconds
Started Mar 31 12:41:35 PM PDT 24
Finished Mar 31 12:53:13 PM PDT 24
Peak memory 201744 kb
Host smart-bfa08a7e-d0de-4592-96d1-10d5fa34c47c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=513848378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.513848378
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.106790436
Short name T621
Test name
Test status
Simulation time 166316182080 ps
CPU time 46.28 seconds
Started Mar 31 12:41:26 PM PDT 24
Finished Mar 31 12:42:12 PM PDT 24
Peak memory 201892 kb
Host smart-5d820c51-0cbf-4185-bdf3-0ad6a467eef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106790436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.106790436
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.4218114790
Short name T665
Test name
Test status
Simulation time 171143842631 ps
CPU time 99.84 seconds
Started Mar 31 12:41:32 PM PDT 24
Finished Mar 31 12:43:12 PM PDT 24
Peak memory 201856 kb
Host smart-25197023-9628-4b1c-8fe6-43b38b518207
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218114790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.4218114790
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3500310225
Short name T59
Test name
Test status
Simulation time 173573420518 ps
CPU time 99.85 seconds
Started Mar 31 12:41:32 PM PDT 24
Finished Mar 31 12:43:12 PM PDT 24
Peak memory 201968 kb
Host smart-b90d9ecb-c40c-4252-87b6-7eff7a352792
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500310225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3500310225
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.2821176246
Short name T362
Test name
Test status
Simulation time 210078081766 ps
CPU time 492.2 seconds
Started Mar 31 12:41:33 PM PDT 24
Finished Mar 31 12:49:45 PM PDT 24
Peak memory 201800 kb
Host smart-054658a7-5490-40ad-9f23-50da5ae02bcf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821176246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.2821176246
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.659622770
Short name T199
Test name
Test status
Simulation time 76476228053 ps
CPU time 301.24 seconds
Started Mar 31 12:41:32 PM PDT 24
Finished Mar 31 12:46:33 PM PDT 24
Peak memory 202136 kb
Host smart-af46e046-bd3c-4ee2-ad95-08fd1a6ec086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659622770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.659622770
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3701608630
Short name T500
Test name
Test status
Simulation time 23169771331 ps
CPU time 28.42 seconds
Started Mar 31 12:41:34 PM PDT 24
Finished Mar 31 12:42:03 PM PDT 24
Peak memory 201640 kb
Host smart-48aa380d-6423-4448-ae16-6d529e9808c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701608630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3701608630
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.4013722282
Short name T766
Test name
Test status
Simulation time 2752475880 ps
CPU time 1.91 seconds
Started Mar 31 12:41:32 PM PDT 24
Finished Mar 31 12:41:35 PM PDT 24
Peak memory 201704 kb
Host smart-a4d87a8f-35c4-483f-8cf4-ff513274fd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013722282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.4013722282
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.450587124
Short name T533
Test name
Test status
Simulation time 5859310644 ps
CPU time 13.06 seconds
Started Mar 31 12:41:29 PM PDT 24
Finished Mar 31 12:41:42 PM PDT 24
Peak memory 201660 kb
Host smart-94b15e92-d3c1-4995-ac71-cba306dd1d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450587124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.450587124
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.3863887217
Short name T159
Test name
Test status
Simulation time 285277851850 ps
CPU time 655.95 seconds
Started Mar 31 12:41:38 PM PDT 24
Finished Mar 31 12:52:34 PM PDT 24
Peak memory 210476 kb
Host smart-a21982d6-7148-44d8-a89e-5b271ec9a6e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863887217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.3863887217
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.856484629
Short name T297
Test name
Test status
Simulation time 61301260801 ps
CPU time 167.31 seconds
Started Mar 31 12:41:34 PM PDT 24
Finished Mar 31 12:44:21 PM PDT 24
Peak memory 210556 kb
Host smart-087c7500-a2e4-48e7-84e4-b304484b8dc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856484629 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.856484629
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3357906911
Short name T422
Test name
Test status
Simulation time 459574160 ps
CPU time 0.83 seconds
Started Mar 31 12:41:47 PM PDT 24
Finished Mar 31 12:41:48 PM PDT 24
Peak memory 201512 kb
Host smart-d738bdb5-3810-4978-95a8-f46750a1c4ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357906911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3357906911
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.190545121
Short name T262
Test name
Test status
Simulation time 328862340892 ps
CPU time 691.64 seconds
Started Mar 31 12:41:39 PM PDT 24
Finished Mar 31 12:53:11 PM PDT 24
Peak memory 201892 kb
Host smart-2e7eeec8-46a1-4588-924f-769500d6da40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190545121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.190545121
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1629982739
Short name T417
Test name
Test status
Simulation time 498481179110 ps
CPU time 298.71 seconds
Started Mar 31 12:41:38 PM PDT 24
Finished Mar 31 12:46:37 PM PDT 24
Peak memory 201820 kb
Host smart-5738c2d5-2bce-4467-88a2-a75e3a00e145
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629982739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1629982739
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.650283859
Short name T380
Test name
Test status
Simulation time 166263739885 ps
CPU time 48.87 seconds
Started Mar 31 12:41:41 PM PDT 24
Finished Mar 31 12:42:30 PM PDT 24
Peak memory 201876 kb
Host smart-ea2c8873-ed0b-45c7-8ee2-7d2c08a8e179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650283859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.650283859
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.2126091049
Short name T531
Test name
Test status
Simulation time 328122592676 ps
CPU time 106.59 seconds
Started Mar 31 12:41:39 PM PDT 24
Finished Mar 31 12:43:26 PM PDT 24
Peak memory 201740 kb
Host smart-58d2c8b6-672c-4517-8d04-9179c3110ede
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126091049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.2126091049
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.3089018635
Short name T440
Test name
Test status
Simulation time 355071802230 ps
CPU time 237.1 seconds
Started Mar 31 12:41:40 PM PDT 24
Finished Mar 31 12:45:38 PM PDT 24
Peak memory 201900 kb
Host smart-d668390a-3a6d-4200-9f3b-1fe18492e632
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089018635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.3089018635
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.4136553727
Short name T145
Test name
Test status
Simulation time 195398107024 ps
CPU time 71.3 seconds
Started Mar 31 12:41:50 PM PDT 24
Finished Mar 31 12:43:01 PM PDT 24
Peak memory 201896 kb
Host smart-701bfda9-15fa-4a3c-9b57-b1e330974cb7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136553727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.4136553727
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3679709917
Short name T3
Test name
Test status
Simulation time 91748520438 ps
CPU time 470.24 seconds
Started Mar 31 12:41:45 PM PDT 24
Finished Mar 31 12:49:36 PM PDT 24
Peak memory 202180 kb
Host smart-38ced595-4e4a-453a-870c-ad123836c702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679709917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3679709917
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3063446760
Short name T374
Test name
Test status
Simulation time 41943922164 ps
CPU time 106.4 seconds
Started Mar 31 12:41:45 PM PDT 24
Finished Mar 31 12:43:32 PM PDT 24
Peak memory 201544 kb
Host smart-0e77b37b-f384-4faf-9136-797ed6efc401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063446760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3063446760
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.2266708835
Short name T416
Test name
Test status
Simulation time 3428074921 ps
CPU time 2.3 seconds
Started Mar 31 12:41:46 PM PDT 24
Finished Mar 31 12:41:48 PM PDT 24
Peak memory 201676 kb
Host smart-65848226-91ef-4192-8610-ed2363fe2bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266708835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.2266708835
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.3442304752
Short name T44
Test name
Test status
Simulation time 5678949925 ps
CPU time 13.29 seconds
Started Mar 31 12:41:41 PM PDT 24
Finished Mar 31 12:41:54 PM PDT 24
Peak memory 201644 kb
Host smart-ff68957b-c479-4412-b7a9-f3c46841a4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442304752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3442304752
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.526790016
Short name T36
Test name
Test status
Simulation time 32554985740 ps
CPU time 18.5 seconds
Started Mar 31 12:41:49 PM PDT 24
Finished Mar 31 12:42:08 PM PDT 24
Peak memory 201684 kb
Host smart-1ebb07b7-3811-4679-977c-dfb1a325838f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526790016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.
526790016
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.3954051836
Short name T102
Test name
Test status
Simulation time 344275675 ps
CPU time 0.98 seconds
Started Mar 31 12:41:51 PM PDT 24
Finished Mar 31 12:41:52 PM PDT 24
Peak memory 201588 kb
Host smart-68bdde1e-0832-4484-bbe8-78a0ee1032f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954051836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.3954051836
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2976346977
Short name T535
Test name
Test status
Simulation time 158952018049 ps
CPU time 380.37 seconds
Started Mar 31 12:41:53 PM PDT 24
Finished Mar 31 12:48:13 PM PDT 24
Peak memory 201860 kb
Host smart-19e39129-159a-4676-b1a7-d8e919a120ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976346977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2976346977
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3929624401
Short name T172
Test name
Test status
Simulation time 492250705044 ps
CPU time 164.51 seconds
Started Mar 31 12:41:45 PM PDT 24
Finished Mar 31 12:44:30 PM PDT 24
Peak memory 201884 kb
Host smart-17220c84-0f3f-4658-abe3-26b6f0e1d2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929624401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3929624401
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2736087120
Short name T564
Test name
Test status
Simulation time 331389845926 ps
CPU time 392.5 seconds
Started Mar 31 12:41:47 PM PDT 24
Finished Mar 31 12:48:20 PM PDT 24
Peak memory 201868 kb
Host smart-065c9ddf-0adc-4a89-9757-7cc70380d25d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736087120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.2736087120
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.2849134392
Short name T737
Test name
Test status
Simulation time 499446951929 ps
CPU time 1266.24 seconds
Started Mar 31 12:41:49 PM PDT 24
Finished Mar 31 01:02:55 PM PDT 24
Peak memory 201964 kb
Host smart-905a8e20-c9ae-42fa-9db1-21420a2211cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849134392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2849134392
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.4130398731
Short name T365
Test name
Test status
Simulation time 320039331478 ps
CPU time 217.48 seconds
Started Mar 31 12:41:45 PM PDT 24
Finished Mar 31 12:45:23 PM PDT 24
Peak memory 201776 kb
Host smart-86d16157-c8c5-48f1-af8d-bea6443e29bf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130398731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.4130398731
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2760412245
Short name T484
Test name
Test status
Simulation time 533758640256 ps
CPU time 1232.16 seconds
Started Mar 31 12:41:53 PM PDT 24
Finished Mar 31 01:02:25 PM PDT 24
Peak memory 201880 kb
Host smart-f9ea51f8-0bac-469f-aea2-88bea734b338
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760412245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2760412245
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.4069175145
Short name T679
Test name
Test status
Simulation time 596170178179 ps
CPU time 1394.07 seconds
Started Mar 31 12:41:55 PM PDT 24
Finished Mar 31 01:05:09 PM PDT 24
Peak memory 201872 kb
Host smart-d1f6a2e4-d10c-44ba-8edc-cf390edccacb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069175145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.4069175145
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.4139489861
Short name T101
Test name
Test status
Simulation time 133133488153 ps
CPU time 480.2 seconds
Started Mar 31 12:41:52 PM PDT 24
Finished Mar 31 12:49:53 PM PDT 24
Peak memory 202224 kb
Host smart-f3fc7f6b-05c4-4675-8cca-35add46e2a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139489861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.4139489861
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.330300739
Short name T330
Test name
Test status
Simulation time 43890238161 ps
CPU time 25.75 seconds
Started Mar 31 12:41:51 PM PDT 24
Finished Mar 31 12:42:16 PM PDT 24
Peak memory 201700 kb
Host smart-aa692bff-3299-4f8f-97c0-a876573070aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330300739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.330300739
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.2825574968
Short name T654
Test name
Test status
Simulation time 4737723358 ps
CPU time 1.29 seconds
Started Mar 31 12:41:53 PM PDT 24
Finished Mar 31 12:41:54 PM PDT 24
Peak memory 201676 kb
Host smart-36f22cf5-3f25-4456-9371-ec884f2c698f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825574968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.2825574968
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2695139808
Short name T780
Test name
Test status
Simulation time 6066496949 ps
CPU time 14.99 seconds
Started Mar 31 12:41:43 PM PDT 24
Finished Mar 31 12:41:59 PM PDT 24
Peak memory 201700 kb
Host smart-850eff03-c86a-4cbe-83d8-c225d188010e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695139808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2695139808
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.2931903209
Short name T736
Test name
Test status
Simulation time 355978035074 ps
CPU time 89.01 seconds
Started Mar 31 12:41:51 PM PDT 24
Finished Mar 31 12:43:20 PM PDT 24
Peak memory 201860 kb
Host smart-57a98d53-5d52-4230-8260-5d37c349b553
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931903209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.2931903209
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1123924980
Short name T769
Test name
Test status
Simulation time 217602338842 ps
CPU time 142.17 seconds
Started Mar 31 12:41:53 PM PDT 24
Finished Mar 31 12:44:16 PM PDT 24
Peak memory 210484 kb
Host smart-6ccc6a66-4ebf-49d6-9e8b-87f53c549aa0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123924980 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1123924980
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2666481041
Short name T799
Test name
Test status
Simulation time 480317635 ps
CPU time 1.12 seconds
Started Mar 31 12:42:07 PM PDT 24
Finished Mar 31 12:42:10 PM PDT 24
Peak memory 201504 kb
Host smart-7f891e29-9b05-4580-926e-853977a44bb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666481041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2666481041
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.640020751
Short name T173
Test name
Test status
Simulation time 554194784252 ps
CPU time 63.2 seconds
Started Mar 31 12:41:57 PM PDT 24
Finished Mar 31 12:43:01 PM PDT 24
Peak memory 201972 kb
Host smart-17904116-69e5-4fdf-b1ad-7b51528aad70
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640020751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.640020751
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3593872752
Short name T594
Test name
Test status
Simulation time 158918681665 ps
CPU time 29.54 seconds
Started Mar 31 12:41:59 PM PDT 24
Finished Mar 31 12:42:28 PM PDT 24
Peak memory 201792 kb
Host smart-35d9cbd4-9da3-45dd-ac30-14362036fff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593872752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3593872752
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2466772525
Short name T139
Test name
Test status
Simulation time 333017051341 ps
CPU time 55.19 seconds
Started Mar 31 12:41:58 PM PDT 24
Finished Mar 31 12:42:54 PM PDT 24
Peak memory 201808 kb
Host smart-0c80faed-c8cd-43a7-a0a3-b160893d6186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466772525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2466772525
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3221636692
Short name T148
Test name
Test status
Simulation time 479783765317 ps
CPU time 277.87 seconds
Started Mar 31 12:41:59 PM PDT 24
Finished Mar 31 12:46:37 PM PDT 24
Peak memory 201860 kb
Host smart-62fe7049-fd04-4fab-82ee-e3e825b9cb64
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221636692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.3221636692
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.2040866129
Short name T496
Test name
Test status
Simulation time 500442882992 ps
CPU time 141.92 seconds
Started Mar 31 12:41:52 PM PDT 24
Finished Mar 31 12:44:14 PM PDT 24
Peak memory 201908 kb
Host smart-6ece5c8d-4968-4924-bd02-459a5f39cef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040866129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.2040866129
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1158515277
Short name T332
Test name
Test status
Simulation time 334479578790 ps
CPU time 386.69 seconds
Started Mar 31 12:41:57 PM PDT 24
Finished Mar 31 12:48:24 PM PDT 24
Peak memory 201948 kb
Host smart-fedbce11-c1a8-4874-8669-3d490a9b7549
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158515277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1158515277
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.4106783838
Short name T229
Test name
Test status
Simulation time 394015911662 ps
CPU time 216.25 seconds
Started Mar 31 12:41:57 PM PDT 24
Finished Mar 31 12:45:34 PM PDT 24
Peak memory 201796 kb
Host smart-ec0c96b6-84de-4d5f-bdb9-c73b37a087c3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106783838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.4106783838
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1682474139
Short name T513
Test name
Test status
Simulation time 592486300583 ps
CPU time 1284.05 seconds
Started Mar 31 12:41:57 PM PDT 24
Finished Mar 31 01:03:22 PM PDT 24
Peak memory 201856 kb
Host smart-469611b7-f3a5-44aa-80ee-7c046edb75f4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682474139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1682474139
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.2305023315
Short name T66
Test name
Test status
Simulation time 97515908008 ps
CPU time 351.25 seconds
Started Mar 31 12:41:57 PM PDT 24
Finished Mar 31 12:47:48 PM PDT 24
Peak memory 202112 kb
Host smart-ec79a320-a897-477a-b806-b6276f0a51c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305023315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.2305023315
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.784620149
Short name T712
Test name
Test status
Simulation time 31094472799 ps
CPU time 68.92 seconds
Started Mar 31 12:41:58 PM PDT 24
Finished Mar 31 12:43:07 PM PDT 24
Peak memory 201652 kb
Host smart-813df70b-1191-487d-bc2c-253a5e995509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784620149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.784620149
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3549663063
Short name T62
Test name
Test status
Simulation time 4210629689 ps
CPU time 11.59 seconds
Started Mar 31 12:41:58 PM PDT 24
Finished Mar 31 12:42:10 PM PDT 24
Peak memory 201612 kb
Host smart-0e91ca69-5a17-4233-a4ae-92104ef7bd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549663063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3549663063
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2795045672
Short name T348
Test name
Test status
Simulation time 5868589315 ps
CPU time 2.9 seconds
Started Mar 31 12:41:53 PM PDT 24
Finished Mar 31 12:41:56 PM PDT 24
Peak memory 201688 kb
Host smart-380be9bc-3df3-4f6d-af4a-2c736e0cd928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795045672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2795045672
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.1797296086
Short name T167
Test name
Test status
Simulation time 237226274755 ps
CPU time 472.9 seconds
Started Mar 31 12:41:59 PM PDT 24
Finished Mar 31 12:49:52 PM PDT 24
Peak memory 210508 kb
Host smart-6018d9c0-54ce-4e62-9a78-b5c67003a05e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797296086 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.1797296086
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.2998862937
Short name T526
Test name
Test status
Simulation time 336609528 ps
CPU time 0.8 seconds
Started Mar 31 12:42:12 PM PDT 24
Finished Mar 31 12:42:13 PM PDT 24
Peak memory 201520 kb
Host smart-046ac81a-be86-43b5-b7f3-6194e13afd1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998862937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.2998862937
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3932080174
Short name T556
Test name
Test status
Simulation time 611621270197 ps
CPU time 177.47 seconds
Started Mar 31 12:42:05 PM PDT 24
Finished Mar 31 12:45:03 PM PDT 24
Peak memory 201936 kb
Host smart-c99b5570-166e-4e75-bd8a-6b428510712f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932080174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3932080174
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.362559217
Short name T307
Test name
Test status
Simulation time 356241707933 ps
CPU time 867.51 seconds
Started Mar 31 12:42:03 PM PDT 24
Finished Mar 31 12:56:31 PM PDT 24
Peak memory 201860 kb
Host smart-e60558a8-95fd-4312-9bdd-d3cd5882871a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362559217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.362559217
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.3909036180
Short name T597
Test name
Test status
Simulation time 486812082164 ps
CPU time 1144.04 seconds
Started Mar 31 12:42:03 PM PDT 24
Finished Mar 31 01:01:08 PM PDT 24
Peak memory 201944 kb
Host smart-ec1caa69-0fac-441e-a969-10b7e7ddb18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909036180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.3909036180
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2650160836
Short name T375
Test name
Test status
Simulation time 488798990414 ps
CPU time 295.01 seconds
Started Mar 31 12:42:08 PM PDT 24
Finished Mar 31 12:47:04 PM PDT 24
Peak memory 201812 kb
Host smart-9f7002c3-97d0-4746-ab4e-346367ffa931
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650160836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2650160836
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.3685775052
Short name T558
Test name
Test status
Simulation time 168414881403 ps
CPU time 376.47 seconds
Started Mar 31 12:42:08 PM PDT 24
Finished Mar 31 12:48:25 PM PDT 24
Peak memory 201940 kb
Host smart-37a37722-3e9d-425f-bec6-27cc860e6a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685775052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.3685775052
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1644351548
Short name T659
Test name
Test status
Simulation time 167989344985 ps
CPU time 104.68 seconds
Started Mar 31 12:42:05 PM PDT 24
Finished Mar 31 12:43:50 PM PDT 24
Peak memory 201832 kb
Host smart-f2fb41ee-dfce-4c8d-a86d-db61445ce5c8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644351548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1644351548
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3640119155
Short name T557
Test name
Test status
Simulation time 379970691879 ps
CPU time 892.59 seconds
Started Mar 31 12:42:06 PM PDT 24
Finished Mar 31 12:57:00 PM PDT 24
Peak memory 201908 kb
Host smart-f2cabfaa-abde-466e-b278-86b3f13ac3b3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640119155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3640119155
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.333703058
Short name T438
Test name
Test status
Simulation time 214023294212 ps
CPU time 129.87 seconds
Started Mar 31 12:42:08 PM PDT 24
Finished Mar 31 12:44:18 PM PDT 24
Peak memory 201796 kb
Host smart-4d78a646-6409-4cbd-aa2d-a4e3a59982be
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333703058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.333703058
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2112187847
Short name T7
Test name
Test status
Simulation time 105173608146 ps
CPU time 436.5 seconds
Started Mar 31 12:42:10 PM PDT 24
Finished Mar 31 12:49:26 PM PDT 24
Peak memory 202164 kb
Host smart-ec3922d4-7819-46df-87b0-56e8f1a5b346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112187847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2112187847
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2421476551
Short name T583
Test name
Test status
Simulation time 42089911948 ps
CPU time 26.18 seconds
Started Mar 31 12:42:12 PM PDT 24
Finished Mar 31 12:42:39 PM PDT 24
Peak memory 201644 kb
Host smart-69cb84c2-d3d4-4290-b5f8-ac5896092579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421476551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2421476551
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.460159841
Short name T518
Test name
Test status
Simulation time 4271740424 ps
CPU time 3.07 seconds
Started Mar 31 12:42:08 PM PDT 24
Finished Mar 31 12:42:12 PM PDT 24
Peak memory 201692 kb
Host smart-5abfe0f0-ed26-46e4-bfe3-5098fe8ef8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460159841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.460159841
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2919643251
Short name T354
Test name
Test status
Simulation time 5631964027 ps
CPU time 11.27 seconds
Started Mar 31 12:42:07 PM PDT 24
Finished Mar 31 12:42:18 PM PDT 24
Peak memory 201716 kb
Host smart-672fc854-0007-4afc-8821-231d37dc7c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919643251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2919643251
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2569622333
Short name T705
Test name
Test status
Simulation time 298626525553 ps
CPU time 970.68 seconds
Started Mar 31 12:42:09 PM PDT 24
Finished Mar 31 12:58:20 PM PDT 24
Peak memory 210372 kb
Host smart-9d1ab1dd-bea1-4a2a-84b9-db497042a38a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569622333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2569622333
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.832370661
Short name T192
Test name
Test status
Simulation time 78057241346 ps
CPU time 181.17 seconds
Started Mar 31 12:42:10 PM PDT 24
Finished Mar 31 12:45:12 PM PDT 24
Peak memory 217684 kb
Host smart-b13c8bb6-35f5-494d-b475-66dca8869441
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832370661 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.832370661
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3252812821
Short name T787
Test name
Test status
Simulation time 296330953 ps
CPU time 1.33 seconds
Started Mar 31 12:42:17 PM PDT 24
Finished Mar 31 12:42:19 PM PDT 24
Peak memory 201512 kb
Host smart-20253443-c99b-4955-9164-c6ac8e5b4858
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252812821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3252812821
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.1229432159
Short name T668
Test name
Test status
Simulation time 165618978285 ps
CPU time 11.83 seconds
Started Mar 31 12:42:10 PM PDT 24
Finished Mar 31 12:42:22 PM PDT 24
Peak memory 201828 kb
Host smart-4975f01b-c9b8-404a-84d8-4f7d42508ff2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229432159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.1229432159
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2277746214
Short name T381
Test name
Test status
Simulation time 328756518013 ps
CPU time 165.64 seconds
Started Mar 31 12:42:09 PM PDT 24
Finished Mar 31 12:44:55 PM PDT 24
Peak memory 201848 kb
Host smart-c1763e3b-f256-4856-b86c-4d6adb3fc7df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277746214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2277746214
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3991639579
Short name T208
Test name
Test status
Simulation time 335010164595 ps
CPU time 818.09 seconds
Started Mar 31 12:42:10 PM PDT 24
Finished Mar 31 12:55:48 PM PDT 24
Peak memory 201916 kb
Host smart-75d28cc3-4c2a-4461-ba00-6af70d16cc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991639579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3991639579
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2157828607
Short name T477
Test name
Test status
Simulation time 331254596615 ps
CPU time 770.67 seconds
Started Mar 31 12:42:12 PM PDT 24
Finished Mar 31 12:55:03 PM PDT 24
Peak memory 201880 kb
Host smart-035fbb1a-c7a2-4d3f-9c88-76277a2d4413
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157828607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2157828607
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1538588750
Short name T239
Test name
Test status
Simulation time 468391714797 ps
CPU time 1000.28 seconds
Started Mar 31 12:42:11 PM PDT 24
Finished Mar 31 12:58:51 PM PDT 24
Peak memory 201956 kb
Host smart-04828c02-03a7-4968-9088-8308875a6029
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538588750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1538588750
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3023160174
Short name T559
Test name
Test status
Simulation time 594639887362 ps
CPU time 339.14 seconds
Started Mar 31 12:42:13 PM PDT 24
Finished Mar 31 12:47:53 PM PDT 24
Peak memory 201868 kb
Host smart-a168dda0-0d1a-4165-8701-6720ddd7f582
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023160174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3023160174
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.537076946
Short name T469
Test name
Test status
Simulation time 120902989813 ps
CPU time 431.78 seconds
Started Mar 31 12:42:16 PM PDT 24
Finished Mar 31 12:49:29 PM PDT 24
Peak memory 202088 kb
Host smart-2a90754a-3041-44a3-86a9-3c76a571ee80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537076946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.537076946
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.1772400183
Short name T652
Test name
Test status
Simulation time 30884762404 ps
CPU time 68.45 seconds
Started Mar 31 12:42:16 PM PDT 24
Finished Mar 31 12:43:25 PM PDT 24
Peak memory 201708 kb
Host smart-346d38b2-aa07-4135-b135-94cc27f13a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772400183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1772400183
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3291693403
Short name T360
Test name
Test status
Simulation time 3381106737 ps
CPU time 4.33 seconds
Started Mar 31 12:42:17 PM PDT 24
Finished Mar 31 12:42:21 PM PDT 24
Peak memory 201640 kb
Host smart-e52798fa-4063-46b8-9e93-ea812de2f721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291693403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3291693403
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3670321576
Short name T797
Test name
Test status
Simulation time 5737944351 ps
CPU time 2.79 seconds
Started Mar 31 12:42:09 PM PDT 24
Finished Mar 31 12:42:12 PM PDT 24
Peak memory 201680 kb
Host smart-6efe93f2-b1db-4105-8be9-44d2d3cedc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670321576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3670321576
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.4180009675
Short name T279
Test name
Test status
Simulation time 335221252863 ps
CPU time 796.59 seconds
Started Mar 31 12:42:15 PM PDT 24
Finished Mar 31 12:55:32 PM PDT 24
Peak memory 201828 kb
Host smart-b782dc29-a4b9-41dc-827f-78bb58e7962d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180009675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.4180009675
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.358253780
Short name T387
Test name
Test status
Simulation time 401407770 ps
CPU time 1.56 seconds
Started Mar 31 12:42:27 PM PDT 24
Finished Mar 31 12:42:29 PM PDT 24
Peak memory 201576 kb
Host smart-9c482737-e1b8-4735-a344-e289c579381d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358253780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.358253780
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.1741719739
Short name T242
Test name
Test status
Simulation time 367703524252 ps
CPU time 204.76 seconds
Started Mar 31 12:42:22 PM PDT 24
Finished Mar 31 12:45:47 PM PDT 24
Peak memory 201928 kb
Host smart-43282b8a-a067-4ca9-b483-586c86c2bff5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741719739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.1741719739
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.4259638216
Short name T322
Test name
Test status
Simulation time 162277163088 ps
CPU time 198.59 seconds
Started Mar 31 12:42:24 PM PDT 24
Finished Mar 31 12:45:43 PM PDT 24
Peak memory 201808 kb
Host smart-66a0ec46-4ac2-45dd-bb0c-3af9b70329c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259638216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.4259638216
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2125619199
Short name T741
Test name
Test status
Simulation time 325224019203 ps
CPU time 709.36 seconds
Started Mar 31 12:42:17 PM PDT 24
Finished Mar 31 12:54:07 PM PDT 24
Peak memory 201828 kb
Host smart-53b74e90-8ab1-41bb-93cf-c0d14ff687f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125619199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2125619199
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3768296155
Short name T459
Test name
Test status
Simulation time 489128965685 ps
CPU time 314.05 seconds
Started Mar 31 12:42:16 PM PDT 24
Finished Mar 31 12:47:31 PM PDT 24
Peak memory 201872 kb
Host smart-e45377bc-eb0b-4e64-814f-7aac6fc5780f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768296155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.3768296155
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2874902174
Short name T543
Test name
Test status
Simulation time 492586073807 ps
CPU time 329.29 seconds
Started Mar 31 12:42:17 PM PDT 24
Finished Mar 31 12:47:47 PM PDT 24
Peak memory 201840 kb
Host smart-423bdd7f-c4cb-4f76-94d1-ca7623f9c951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874902174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2874902174
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2846865668
Short name T566
Test name
Test status
Simulation time 160559943205 ps
CPU time 357.93 seconds
Started Mar 31 12:42:17 PM PDT 24
Finished Mar 31 12:48:15 PM PDT 24
Peak memory 201912 kb
Host smart-8d09a2fe-7463-4e83-b361-b4bf74a16507
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846865668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2846865668
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2099995651
Short name T576
Test name
Test status
Simulation time 367425502308 ps
CPU time 83.01 seconds
Started Mar 31 12:42:23 PM PDT 24
Finished Mar 31 12:43:46 PM PDT 24
Peak memory 201856 kb
Host smart-207dc498-eac4-4a0b-9a6c-780c97f34cab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099995651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2099995651
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1828328460
Short name T775
Test name
Test status
Simulation time 195545783159 ps
CPU time 439.58 seconds
Started Mar 31 12:42:25 PM PDT 24
Finished Mar 31 12:49:44 PM PDT 24
Peak memory 201852 kb
Host smart-1ccea001-d022-42ef-a01b-a3949723be62
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828328460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.1828328460
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1568308474
Short name T402
Test name
Test status
Simulation time 40502789834 ps
CPU time 29.67 seconds
Started Mar 31 12:42:23 PM PDT 24
Finished Mar 31 12:42:52 PM PDT 24
Peak memory 201596 kb
Host smart-a3df9d1e-d69c-4554-83df-d055e3c3fff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568308474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1568308474
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1366848263
Short name T430
Test name
Test status
Simulation time 4494325994 ps
CPU time 2.07 seconds
Started Mar 31 12:42:22 PM PDT 24
Finished Mar 31 12:42:25 PM PDT 24
Peak memory 201708 kb
Host smart-92ea83de-6f73-4dd3-9f8c-8ede95241ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366848263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1366848263
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3963588906
Short name T487
Test name
Test status
Simulation time 5551962278 ps
CPU time 13.56 seconds
Started Mar 31 12:42:15 PM PDT 24
Finished Mar 31 12:42:29 PM PDT 24
Peak memory 201588 kb
Host smart-77534413-e9b7-4bc8-ad45-1c2821f5fc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963588906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3963588906
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.4129431649
Short name T243
Test name
Test status
Simulation time 104822689088 ps
CPU time 43.25 seconds
Started Mar 31 12:42:24 PM PDT 24
Finished Mar 31 12:43:07 PM PDT 24
Peak memory 210416 kb
Host smart-b3fba91a-accc-42bd-a09f-e51584e67111
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129431649 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.4129431649
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.639383273
Short name T55
Test name
Test status
Simulation time 510311739 ps
CPU time 1.84 seconds
Started Mar 31 12:40:03 PM PDT 24
Finished Mar 31 12:40:05 PM PDT 24
Peak memory 201568 kb
Host smart-6af9b1aa-5238-4c87-98d4-b9eb03e96104
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639383273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.639383273
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.592276419
Short name T630
Test name
Test status
Simulation time 206302653058 ps
CPU time 484.07 seconds
Started Mar 31 12:40:08 PM PDT 24
Finished Mar 31 12:48:12 PM PDT 24
Peak memory 201848 kb
Host smart-1b683203-22c4-472f-824f-34ebc5bfb182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592276419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.592276419
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.4165965569
Short name T720
Test name
Test status
Simulation time 487236551103 ps
CPU time 584.68 seconds
Started Mar 31 12:40:04 PM PDT 24
Finished Mar 31 12:49:49 PM PDT 24
Peak memory 201780 kb
Host smart-3bcb93e6-9ba6-4cd8-a5dd-8ea14c680ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165965569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.4165965569
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.930892265
Short name T605
Test name
Test status
Simulation time 167857394791 ps
CPU time 381.52 seconds
Started Mar 31 12:40:05 PM PDT 24
Finished Mar 31 12:46:27 PM PDT 24
Peak memory 201872 kb
Host smart-c486e26c-3fc6-4446-b3a5-09ff89ff0f90
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=930892265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt
_fixed.930892265
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3469672747
Short name T210
Test name
Test status
Simulation time 166548074913 ps
CPU time 100.24 seconds
Started Mar 31 12:40:03 PM PDT 24
Finished Mar 31 12:41:44 PM PDT 24
Peak memory 201808 kb
Host smart-3adfb567-1cf3-4f04-adbe-c20ef84043cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469672747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3469672747
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1731624808
Short name T462
Test name
Test status
Simulation time 489031347207 ps
CPU time 1158.48 seconds
Started Mar 31 12:40:08 PM PDT 24
Finished Mar 31 12:59:27 PM PDT 24
Peak memory 201864 kb
Host smart-dcb465bc-0d83-4fbb-94d3-4c0300091cce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731624808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1731624808
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1741014183
Short name T573
Test name
Test status
Simulation time 564560626155 ps
CPU time 1283.31 seconds
Started Mar 31 12:39:55 PM PDT 24
Finished Mar 31 01:01:18 PM PDT 24
Peak memory 201880 kb
Host smart-868c634e-7926-45be-ae57-87d038eb8f83
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741014183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1741014183
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.4068893105
Short name T336
Test name
Test status
Simulation time 204391138083 ps
CPU time 449.64 seconds
Started Mar 31 12:40:03 PM PDT 24
Finished Mar 31 12:47:33 PM PDT 24
Peak memory 201860 kb
Host smart-79149c17-01af-4c8a-8507-f318cea454e8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068893105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.4068893105
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.1274829733
Short name T415
Test name
Test status
Simulation time 101374924413 ps
CPU time 332.48 seconds
Started Mar 31 12:40:03 PM PDT 24
Finished Mar 31 12:45:36 PM PDT 24
Peak memory 201952 kb
Host smart-6350cdf6-43ba-4959-a076-42339cf4c9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274829733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1274829733
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.3460440526
Short name T747
Test name
Test status
Simulation time 29691109064 ps
CPU time 13.96 seconds
Started Mar 31 12:40:06 PM PDT 24
Finished Mar 31 12:40:20 PM PDT 24
Peak memory 201624 kb
Host smart-30dbad1b-3f0e-42f1-910f-a99eb8fceb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460440526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.3460440526
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.2559957938
Short name T563
Test name
Test status
Simulation time 3280097244 ps
CPU time 5.29 seconds
Started Mar 31 12:40:05 PM PDT 24
Finished Mar 31 12:40:10 PM PDT 24
Peak memory 201704 kb
Host smart-9d770297-ecf7-400c-a676-feef828c9fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559957938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.2559957938
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.615123564
Short name T93
Test name
Test status
Simulation time 3661223057 ps
CPU time 2.41 seconds
Started Mar 31 12:40:04 PM PDT 24
Finished Mar 31 12:40:06 PM PDT 24
Peak memory 217412 kb
Host smart-51265a4b-15e5-47c1-9703-c5fe67e6c3f2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615123564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.615123564
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.56233540
Short name T546
Test name
Test status
Simulation time 5903396873 ps
CPU time 2.54 seconds
Started Mar 31 12:40:03 PM PDT 24
Finished Mar 31 12:40:06 PM PDT 24
Peak memory 201580 kb
Host smart-6d857330-0648-433f-9043-b0086088f65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56233540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.56233540
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.1934630799
Short name T318
Test name
Test status
Simulation time 3581609764772 ps
CPU time 6988.4 seconds
Started Mar 31 12:40:00 PM PDT 24
Finished Mar 31 02:36:29 PM PDT 24
Peak memory 210316 kb
Host smart-776330fe-0ac5-499c-8d46-81cf80823d25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934630799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
1934630799
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3795713895
Short name T572
Test name
Test status
Simulation time 760927159149 ps
CPU time 195.28 seconds
Started Mar 31 12:40:04 PM PDT 24
Finished Mar 31 12:43:20 PM PDT 24
Peak memory 210612 kb
Host smart-682edf42-b717-44c5-9eef-354fcdaf4dbb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795713895 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3795713895
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.799601206
Short name T609
Test name
Test status
Simulation time 309279016 ps
CPU time 0.74 seconds
Started Mar 31 12:42:37 PM PDT 24
Finished Mar 31 12:42:37 PM PDT 24
Peak memory 201508 kb
Host smart-2790ca00-692a-46c3-8744-74673e7d9eef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799601206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.799601206
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.2462370558
Short name T748
Test name
Test status
Simulation time 380538093928 ps
CPU time 231.5 seconds
Started Mar 31 12:42:26 PM PDT 24
Finished Mar 31 12:46:18 PM PDT 24
Peak memory 201960 kb
Host smart-a94864f8-2836-464e-920b-1f59572fbe56
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462370558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.2462370558
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1647044617
Short name T215
Test name
Test status
Simulation time 523638817516 ps
CPU time 366.92 seconds
Started Mar 31 12:42:34 PM PDT 24
Finished Mar 31 12:48:41 PM PDT 24
Peak memory 201884 kb
Host smart-8ed8631b-35ba-4a5e-b60c-984ed73d4422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647044617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1647044617
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.4073098480
Short name T232
Test name
Test status
Simulation time 337335130359 ps
CPU time 207.53 seconds
Started Mar 31 12:42:26 PM PDT 24
Finished Mar 31 12:45:54 PM PDT 24
Peak memory 201860 kb
Host smart-6741550a-8de6-43f6-a980-93cf0d9b396c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073098480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.4073098480
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2422748778
Short name T632
Test name
Test status
Simulation time 485201041527 ps
CPU time 912.11 seconds
Started Mar 31 12:42:28 PM PDT 24
Finished Mar 31 12:57:40 PM PDT 24
Peak memory 201800 kb
Host smart-33936ea4-e077-4e6f-92cf-a2464db255ec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422748778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2422748778
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3568503693
Short name T458
Test name
Test status
Simulation time 326427413265 ps
CPU time 176.64 seconds
Started Mar 31 12:42:27 PM PDT 24
Finished Mar 31 12:45:23 PM PDT 24
Peak memory 201876 kb
Host smart-ddb2c1a8-e847-40ec-9bef-ed6dec89c085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568503693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3568503693
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3502253610
Short name T750
Test name
Test status
Simulation time 324883006910 ps
CPU time 81.25 seconds
Started Mar 31 12:42:28 PM PDT 24
Finished Mar 31 12:43:49 PM PDT 24
Peak memory 201944 kb
Host smart-5352125c-f8ee-474a-a33d-dbeff4b87d54
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502253610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3502253610
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.1669722279
Short name T174
Test name
Test status
Simulation time 609863027141 ps
CPU time 1307.89 seconds
Started Mar 31 12:42:27 PM PDT 24
Finished Mar 31 01:04:15 PM PDT 24
Peak memory 201892 kb
Host smart-cf073e80-1dd6-4ee5-849b-15ea0a6fa0b5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669722279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.1669722279
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.3791345105
Short name T591
Test name
Test status
Simulation time 74478391423 ps
CPU time 391.25 seconds
Started Mar 31 12:42:34 PM PDT 24
Finished Mar 31 12:49:06 PM PDT 24
Peak memory 202148 kb
Host smart-f9c2778c-5933-4bf8-8550-fa5954d5dc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791345105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.3791345105
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1577473970
Short name T575
Test name
Test status
Simulation time 26219414863 ps
CPU time 61.85 seconds
Started Mar 31 12:42:35 PM PDT 24
Finished Mar 31 12:43:37 PM PDT 24
Peak memory 201692 kb
Host smart-1fd34af8-5214-41a2-8773-dc51b09c0195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577473970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1577473970
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1332161907
Short name T464
Test name
Test status
Simulation time 5340064144 ps
CPU time 3.75 seconds
Started Mar 31 12:42:33 PM PDT 24
Finished Mar 31 12:42:37 PM PDT 24
Peak memory 201644 kb
Host smart-0703fdf5-9c6f-40bc-bbab-694377ffdb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332161907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1332161907
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.1071384250
Short name T437
Test name
Test status
Simulation time 5797200927 ps
CPU time 4.73 seconds
Started Mar 31 12:42:26 PM PDT 24
Finished Mar 31 12:42:30 PM PDT 24
Peak memory 201652 kb
Host smart-9cc47c35-f3a2-43da-a76b-dca35df5636c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071384250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1071384250
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.663793607
Short name T274
Test name
Test status
Simulation time 535155977681 ps
CPU time 285.62 seconds
Started Mar 31 12:42:36 PM PDT 24
Finished Mar 31 12:47:22 PM PDT 24
Peak memory 201884 kb
Host smart-646fb09f-862e-494e-ba4f-abcbe19c21ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663793607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.
663793607
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.1627699478
Short name T23
Test name
Test status
Simulation time 22659999861 ps
CPU time 63.87 seconds
Started Mar 31 12:42:33 PM PDT 24
Finished Mar 31 12:43:37 PM PDT 24
Peak memory 210588 kb
Host smart-aeb842c2-4e25-4446-841c-696235a27ee4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627699478 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.1627699478
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.480410375
Short name T795
Test name
Test status
Simulation time 528321623 ps
CPU time 1.93 seconds
Started Mar 31 12:42:44 PM PDT 24
Finished Mar 31 12:42:46 PM PDT 24
Peak memory 201576 kb
Host smart-7e76f1d7-bec8-431a-b6e7-2304f6325a1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480410375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.480410375
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.4248789748
Short name T314
Test name
Test status
Simulation time 353948126363 ps
CPU time 877.18 seconds
Started Mar 31 12:42:46 PM PDT 24
Finished Mar 31 12:57:23 PM PDT 24
Peak memory 201892 kb
Host smart-8764b776-e30d-4912-b0fa-5356aee0f6be
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248789748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.4248789748
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.435088970
Short name T163
Test name
Test status
Simulation time 512106234509 ps
CPU time 311.51 seconds
Started Mar 31 12:42:45 PM PDT 24
Finished Mar 31 12:47:57 PM PDT 24
Peak memory 201964 kb
Host smart-6415981c-e887-40a6-8cbc-c4130cd3b78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435088970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.435088970
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.943318543
Short name T756
Test name
Test status
Simulation time 169504214476 ps
CPU time 387.48 seconds
Started Mar 31 12:42:44 PM PDT 24
Finished Mar 31 12:49:12 PM PDT 24
Peak memory 201880 kb
Host smart-ed427b00-5aaf-43a5-984e-eec6a9e92f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943318543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.943318543
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2576665061
Short name T644
Test name
Test status
Simulation time 162662438193 ps
CPU time 359.18 seconds
Started Mar 31 12:42:45 PM PDT 24
Finished Mar 31 12:48:44 PM PDT 24
Peak memory 201856 kb
Host smart-1b87f039-9b15-4b72-9474-9c0c5fc44162
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576665061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2576665061
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2551087833
Short name T143
Test name
Test status
Simulation time 501565552464 ps
CPU time 257.54 seconds
Started Mar 31 12:42:35 PM PDT 24
Finished Mar 31 12:46:52 PM PDT 24
Peak memory 201864 kb
Host smart-97ef42d1-4303-44fa-9f90-4d72bb21f7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551087833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2551087833
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3192239931
Short name T619
Test name
Test status
Simulation time 489290353233 ps
CPU time 1131.78 seconds
Started Mar 31 12:42:36 PM PDT 24
Finished Mar 31 01:01:28 PM PDT 24
Peak memory 201796 kb
Host smart-03dd6b79-02a4-4693-bd41-bf1d6a6eef0b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192239931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3192239931
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2386963611
Short name T272
Test name
Test status
Simulation time 187112547387 ps
CPU time 441.82 seconds
Started Mar 31 12:42:44 PM PDT 24
Finished Mar 31 12:50:06 PM PDT 24
Peak memory 201792 kb
Host smart-533f0a10-a7a8-4d29-b037-3038347a6a36
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386963611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2386963611
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.458803967
Short name T105
Test name
Test status
Simulation time 396257663578 ps
CPU time 941.4 seconds
Started Mar 31 12:42:44 PM PDT 24
Finished Mar 31 12:58:26 PM PDT 24
Peak memory 201860 kb
Host smart-eee808a5-383e-4adb-8a20-132e12fbd7cf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458803967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
adc_ctrl_filters_wakeup_fixed.458803967
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.489995934
Short name T328
Test name
Test status
Simulation time 75301282880 ps
CPU time 376.27 seconds
Started Mar 31 12:42:44 PM PDT 24
Finished Mar 31 12:49:00 PM PDT 24
Peak memory 202164 kb
Host smart-8f9d7c46-b714-4dc8-ab5d-b192d583c373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489995934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.489995934
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.258287033
Short name T25
Test name
Test status
Simulation time 22823622867 ps
CPU time 13.63 seconds
Started Mar 31 12:42:44 PM PDT 24
Finished Mar 31 12:42:57 PM PDT 24
Peak memory 201692 kb
Host smart-114f8f3c-e99a-4c80-9bee-20ba2b99ca57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258287033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.258287033
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.3194071344
Short name T687
Test name
Test status
Simulation time 4035429924 ps
CPU time 4.93 seconds
Started Mar 31 12:42:44 PM PDT 24
Finished Mar 31 12:42:49 PM PDT 24
Peak memory 201620 kb
Host smart-cdbadb85-fcfb-4274-ac71-4e10114856a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194071344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.3194071344
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.932037067
Short name T721
Test name
Test status
Simulation time 5982009054 ps
CPU time 1.72 seconds
Started Mar 31 12:42:35 PM PDT 24
Finished Mar 31 12:42:37 PM PDT 24
Peak memory 201700 kb
Host smart-fcec169e-23d3-4791-99e5-c1757508235f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932037067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.932037067
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.2391069164
Short name T317
Test name
Test status
Simulation time 493677615118 ps
CPU time 1150.11 seconds
Started Mar 31 12:42:45 PM PDT 24
Finished Mar 31 01:01:56 PM PDT 24
Peak memory 201940 kb
Host smart-c725ab99-5176-4aa5-81d7-832b21c84e85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391069164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.2391069164
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3049030200
Short name T48
Test name
Test status
Simulation time 105801798217 ps
CPU time 288.75 seconds
Started Mar 31 12:42:44 PM PDT 24
Finished Mar 31 12:47:33 PM PDT 24
Peak memory 210572 kb
Host smart-eaafaa20-b874-49b2-b23c-1884f620f4d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049030200 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3049030200
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2449612584
Short name T549
Test name
Test status
Simulation time 549122645 ps
CPU time 0.81 seconds
Started Mar 31 12:42:57 PM PDT 24
Finished Mar 31 12:42:58 PM PDT 24
Peak memory 201508 kb
Host smart-394742d2-d508-4f5d-9672-78f9af373d1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449612584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2449612584
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3076371727
Short name T428
Test name
Test status
Simulation time 162571172355 ps
CPU time 85.93 seconds
Started Mar 31 12:42:52 PM PDT 24
Finished Mar 31 12:44:18 PM PDT 24
Peak memory 201800 kb
Host smart-9e5ce2e9-c3d2-4ee5-a945-575bc9a9a7fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076371727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3076371727
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.2914236408
Short name T264
Test name
Test status
Simulation time 354617505161 ps
CPU time 428.14 seconds
Started Mar 31 12:42:50 PM PDT 24
Finished Mar 31 12:49:58 PM PDT 24
Peak memory 201844 kb
Host smart-724c2b32-2c53-44ec-a34a-ab4e03f70eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914236408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.2914236408
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.2815608676
Short name T217
Test name
Test status
Simulation time 492841538618 ps
CPU time 312.03 seconds
Started Mar 31 12:42:52 PM PDT 24
Finished Mar 31 12:48:04 PM PDT 24
Peak memory 201884 kb
Host smart-63bf8dad-b509-4a8b-b892-4138407ab3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815608676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2815608676
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.858310697
Short name T390
Test name
Test status
Simulation time 320539303199 ps
CPU time 177.76 seconds
Started Mar 31 12:42:52 PM PDT 24
Finished Mar 31 12:45:49 PM PDT 24
Peak memory 201856 kb
Host smart-9c4d5a98-d64e-41ea-8798-4b28d92fe800
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=858310697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrup
t_fixed.858310697
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1860748104
Short name T439
Test name
Test status
Simulation time 167801758236 ps
CPU time 392.04 seconds
Started Mar 31 12:42:50 PM PDT 24
Finished Mar 31 12:49:22 PM PDT 24
Peak memory 201868 kb
Host smart-4bc2dce7-2c8b-4025-bd83-3976e5f41ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860748104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1860748104
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.489841967
Short name T342
Test name
Test status
Simulation time 318291138271 ps
CPU time 772.62 seconds
Started Mar 31 12:42:51 PM PDT 24
Finished Mar 31 12:55:43 PM PDT 24
Peak memory 201936 kb
Host smart-324a20cf-46e1-49d3-8d5f-44fb71dcdff0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=489841967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.489841967
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.4080643076
Short name T269
Test name
Test status
Simulation time 180317113018 ps
CPU time 230.79 seconds
Started Mar 31 12:42:51 PM PDT 24
Finished Mar 31 12:46:42 PM PDT 24
Peak memory 201892 kb
Host smart-4f68a452-308c-438f-ad71-80aaa3b538a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080643076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.4080643076
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.1492714534
Short name T626
Test name
Test status
Simulation time 589234591163 ps
CPU time 196.61 seconds
Started Mar 31 12:42:53 PM PDT 24
Finished Mar 31 12:46:09 PM PDT 24
Peak memory 201872 kb
Host smart-6458f7b5-ae2a-464e-82ed-1aa56ccf9812
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492714534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.1492714534
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3577774655
Short name T431
Test name
Test status
Simulation time 95241522037 ps
CPU time 484.9 seconds
Started Mar 31 12:42:57 PM PDT 24
Finished Mar 31 12:51:02 PM PDT 24
Peak memory 202224 kb
Host smart-303eae35-22b6-47ba-9e3e-f6cf62156ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577774655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3577774655
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3579583473
Short name T394
Test name
Test status
Simulation time 39954186700 ps
CPU time 13.89 seconds
Started Mar 31 12:42:50 PM PDT 24
Finished Mar 31 12:43:04 PM PDT 24
Peak memory 201664 kb
Host smart-a88c76d3-7b98-4c6c-8ea9-8757c48fd7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579583473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3579583473
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.442860482
Short name T760
Test name
Test status
Simulation time 2829742521 ps
CPU time 6.99 seconds
Started Mar 31 12:42:52 PM PDT 24
Finished Mar 31 12:42:59 PM PDT 24
Peak memory 201692 kb
Host smart-8901e77f-dc90-455d-98d6-87d4d35b6320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442860482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.442860482
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3302136171
Short name T347
Test name
Test status
Simulation time 5576899820 ps
CPU time 12.86 seconds
Started Mar 31 12:42:50 PM PDT 24
Finished Mar 31 12:43:03 PM PDT 24
Peak memory 201628 kb
Host smart-7d664a1b-21c7-4fd7-a8e3-5ca434aa72ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302136171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3302136171
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.4249037989
Short name T758
Test name
Test status
Simulation time 330451998950 ps
CPU time 752.92 seconds
Started Mar 31 12:42:58 PM PDT 24
Finished Mar 31 12:55:31 PM PDT 24
Peak memory 201856 kb
Host smart-7371b907-efda-45ae-a4c9-695365b98928
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249037989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.4249037989
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.313683139
Short name T744
Test name
Test status
Simulation time 515854275 ps
CPU time 1.5 seconds
Started Mar 31 12:43:02 PM PDT 24
Finished Mar 31 12:43:04 PM PDT 24
Peak memory 201480 kb
Host smart-c222af7d-07f1-458c-a463-9ff3500072cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313683139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.313683139
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1897345282
Short name T261
Test name
Test status
Simulation time 491652592475 ps
CPU time 1214.89 seconds
Started Mar 31 12:42:56 PM PDT 24
Finished Mar 31 01:03:11 PM PDT 24
Peak memory 201816 kb
Host smart-b21361e6-9760-4a97-9599-b1910394dc64
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897345282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1897345282
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.2672145680
Short name T240
Test name
Test status
Simulation time 342549955832 ps
CPU time 371.54 seconds
Started Mar 31 12:42:58 PM PDT 24
Finished Mar 31 12:49:10 PM PDT 24
Peak memory 201816 kb
Host smart-61840623-7aa5-4af9-bed6-d7a82f41c45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672145680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.2672145680
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.3012141354
Short name T181
Test name
Test status
Simulation time 492226896158 ps
CPU time 161.45 seconds
Started Mar 31 12:42:56 PM PDT 24
Finished Mar 31 12:45:38 PM PDT 24
Peak memory 201812 kb
Host smart-fe9cee3d-382f-487f-85ae-e61cb7c80a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012141354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3012141354
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.3186451740
Short name T593
Test name
Test status
Simulation time 329628668501 ps
CPU time 743.58 seconds
Started Mar 31 12:43:02 PM PDT 24
Finished Mar 31 12:55:25 PM PDT 24
Peak memory 201808 kb
Host smart-334c9961-4646-4237-95a5-6f1b676f1147
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186451740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.3186451740
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.483526836
Short name T677
Test name
Test status
Simulation time 330408816239 ps
CPU time 763.31 seconds
Started Mar 31 12:42:56 PM PDT 24
Finished Mar 31 12:55:39 PM PDT 24
Peak memory 201936 kb
Host smart-6a72f2f6-6c6b-4398-a246-1823e2c8ab51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483526836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.483526836
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2411880294
Short name T620
Test name
Test status
Simulation time 331092870284 ps
CPU time 752.11 seconds
Started Mar 31 12:42:58 PM PDT 24
Finished Mar 31 12:55:30 PM PDT 24
Peak memory 201828 kb
Host smart-01f5c0e4-ace1-4c58-9062-fd580db8ebd7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411880294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2411880294
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.1180043561
Short name T285
Test name
Test status
Simulation time 372045533796 ps
CPU time 237.56 seconds
Started Mar 31 12:43:01 PM PDT 24
Finished Mar 31 12:46:59 PM PDT 24
Peak memory 201848 kb
Host smart-233dd299-f0a1-4884-9a43-c5c8f2bc52cb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180043561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.1180043561
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.1120556384
Short name T369
Test name
Test status
Simulation time 608085073271 ps
CPU time 1465.08 seconds
Started Mar 31 12:42:56 PM PDT 24
Finished Mar 31 01:07:21 PM PDT 24
Peak memory 201880 kb
Host smart-c239c36e-c4f2-48e2-a0a9-d273e8b07070
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120556384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.1120556384
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.1845077213
Short name T384
Test name
Test status
Simulation time 115428786411 ps
CPU time 640.36 seconds
Started Mar 31 12:43:02 PM PDT 24
Finished Mar 31 12:53:43 PM PDT 24
Peak memory 202204 kb
Host smart-ec633c62-5ed5-40ac-9331-5329d7cdf158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845077213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.1845077213
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.403784336
Short name T584
Test name
Test status
Simulation time 32241984833 ps
CPU time 20.34 seconds
Started Mar 31 12:42:55 PM PDT 24
Finished Mar 31 12:43:15 PM PDT 24
Peak memory 201672 kb
Host smart-ebacf1f0-a025-4417-ae73-cf0f813d22ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403784336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.403784336
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.2008452509
Short name T788
Test name
Test status
Simulation time 3154783785 ps
CPU time 2.6 seconds
Started Mar 31 12:42:56 PM PDT 24
Finished Mar 31 12:42:59 PM PDT 24
Peak memory 201656 kb
Host smart-cb134086-617a-4ac9-b0f8-830b688134a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008452509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2008452509
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.507403626
Short name T776
Test name
Test status
Simulation time 5853812415 ps
CPU time 16.49 seconds
Started Mar 31 12:42:54 PM PDT 24
Finished Mar 31 12:43:11 PM PDT 24
Peak memory 201628 kb
Host smart-5d8d9ab9-1a3b-4ed0-bf36-12a99608c4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507403626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.507403626
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.3745158573
Short name T35
Test name
Test status
Simulation time 297928549285 ps
CPU time 1068.96 seconds
Started Mar 31 12:43:03 PM PDT 24
Finished Mar 31 01:00:52 PM PDT 24
Peak memory 210372 kb
Host smart-d47f48e6-1ac4-41fa-a08f-d16d7938b867
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745158573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.3745158573
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.104726654
Short name T628
Test name
Test status
Simulation time 75230974506 ps
CPU time 151.6 seconds
Started Mar 31 12:43:02 PM PDT 24
Finished Mar 31 12:45:33 PM PDT 24
Peak memory 210560 kb
Host smart-6a339121-7157-4fbd-a5cb-f25567f92960
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104726654 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.104726654
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1455234408
Short name T731
Test name
Test status
Simulation time 359166952 ps
CPU time 1.04 seconds
Started Mar 31 12:43:09 PM PDT 24
Finished Mar 31 12:43:10 PM PDT 24
Peak memory 201540 kb
Host smart-547d9653-a26e-48a5-83b2-f4a0b0f2536a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455234408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1455234408
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.2974134763
Short name T246
Test name
Test status
Simulation time 515133379316 ps
CPU time 445.23 seconds
Started Mar 31 12:43:02 PM PDT 24
Finished Mar 31 12:50:28 PM PDT 24
Peak memory 201904 kb
Host smart-9d5a57c8-1cf4-4068-b9b0-358b62606098
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974134763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.2974134763
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.919089298
Short name T183
Test name
Test status
Simulation time 532150525904 ps
CPU time 308.73 seconds
Started Mar 31 12:43:11 PM PDT 24
Finished Mar 31 12:48:21 PM PDT 24
Peak memory 201932 kb
Host smart-a41baddc-d4ee-4816-b24a-466e4c55ba9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919089298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.919089298
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3576841447
Short name T185
Test name
Test status
Simulation time 491078207590 ps
CPU time 329.94 seconds
Started Mar 31 12:43:03 PM PDT 24
Finished Mar 31 12:48:33 PM PDT 24
Peak memory 201844 kb
Host smart-a9535f37-de05-4931-97f3-df791e2f1313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576841447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3576841447
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1802350679
Short name T389
Test name
Test status
Simulation time 325574099637 ps
CPU time 712.84 seconds
Started Mar 31 12:43:07 PM PDT 24
Finished Mar 31 12:55:00 PM PDT 24
Peak memory 201816 kb
Host smart-2cf5203a-bd78-4deb-bafa-32c1b301ca6e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802350679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1802350679
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.4075402581
Short name T283
Test name
Test status
Simulation time 495491796781 ps
CPU time 309.05 seconds
Started Mar 31 12:43:04 PM PDT 24
Finished Mar 31 12:48:13 PM PDT 24
Peak memory 201880 kb
Host smart-8d201943-81f2-40ee-b9b5-90a0e59462dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075402581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.4075402581
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.657696235
Short name T340
Test name
Test status
Simulation time 333192459078 ps
CPU time 685.5 seconds
Started Mar 31 12:43:04 PM PDT 24
Finished Mar 31 12:54:30 PM PDT 24
Peak memory 201864 kb
Host smart-e5cae82f-b9aa-44f5-b73c-10d190cf3f62
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=657696235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe
d.657696235
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1470193610
Short name T150
Test name
Test status
Simulation time 350615945964 ps
CPU time 75.02 seconds
Started Mar 31 12:43:03 PM PDT 24
Finished Mar 31 12:44:18 PM PDT 24
Peak memory 201952 kb
Host smart-cfa7666e-50fe-4213-9510-05c138e5a6bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470193610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1470193610
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.453071386
Short name T570
Test name
Test status
Simulation time 387922297812 ps
CPU time 205.43 seconds
Started Mar 31 12:43:04 PM PDT 24
Finished Mar 31 12:46:30 PM PDT 24
Peak memory 201800 kb
Host smart-322ecf76-3ff8-4618-9f29-cc960a703d08
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453071386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
adc_ctrl_filters_wakeup_fixed.453071386
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.2065471503
Short name T740
Test name
Test status
Simulation time 124650911329 ps
CPU time 544.59 seconds
Started Mar 31 12:43:09 PM PDT 24
Finished Mar 31 12:52:14 PM PDT 24
Peak memory 202176 kb
Host smart-9a35785b-c546-4848-9c84-4714930e5fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065471503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2065471503
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.261925769
Short name T634
Test name
Test status
Simulation time 40960268224 ps
CPU time 22.57 seconds
Started Mar 31 12:43:07 PM PDT 24
Finished Mar 31 12:43:30 PM PDT 24
Peak memory 201672 kb
Host smart-6de5b9b3-dd4b-41b2-9f6b-0121fa38eb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261925769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.261925769
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2265676979
Short name T595
Test name
Test status
Simulation time 4572330394 ps
CPU time 11.19 seconds
Started Mar 31 12:43:08 PM PDT 24
Finished Mar 31 12:43:19 PM PDT 24
Peak memory 201664 kb
Host smart-6f970d64-95fd-40fd-90e4-65fa008c6989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265676979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2265676979
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.2722399656
Short name T472
Test name
Test status
Simulation time 5825934516 ps
CPU time 14.94 seconds
Started Mar 31 12:43:04 PM PDT 24
Finished Mar 31 12:43:19 PM PDT 24
Peak memory 201688 kb
Host smart-5268fe55-a2c4-4aac-be59-cd3422fa884a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722399656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2722399656
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1733308586
Short name T512
Test name
Test status
Simulation time 179421072162 ps
CPU time 132.07 seconds
Started Mar 31 12:43:11 PM PDT 24
Finished Mar 31 12:45:24 PM PDT 24
Peak memory 210664 kb
Host smart-7e6b5b33-244b-4c9d-bc01-5bb76b7f4562
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733308586 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1733308586
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.706823551
Short name T406
Test name
Test status
Simulation time 552890771 ps
CPU time 0.95 seconds
Started Mar 31 12:43:23 PM PDT 24
Finished Mar 31 12:43:25 PM PDT 24
Peak memory 201576 kb
Host smart-6e917a74-a2c9-4e23-a3aa-e58ba2f85c1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706823551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.706823551
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.691043797
Short name T171
Test name
Test status
Simulation time 357153929273 ps
CPU time 60.16 seconds
Started Mar 31 12:43:16 PM PDT 24
Finished Mar 31 12:44:17 PM PDT 24
Peak memory 201876 kb
Host smart-fd196053-95e2-4def-bfe3-d7cf712fc055
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691043797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.691043797
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3651224824
Short name T221
Test name
Test status
Simulation time 168992386291 ps
CPU time 404.74 seconds
Started Mar 31 12:43:19 PM PDT 24
Finished Mar 31 12:50:04 PM PDT 24
Peak memory 201836 kb
Host smart-fdcba667-5901-46bf-9fd1-2b5c37e3338a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651224824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3651224824
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2898315854
Short name T752
Test name
Test status
Simulation time 491765727190 ps
CPU time 740.74 seconds
Started Mar 31 12:43:17 PM PDT 24
Finished Mar 31 12:55:39 PM PDT 24
Peak memory 201852 kb
Host smart-cc641fc9-729b-41a8-9d13-2505e66cc1c6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898315854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.2898315854
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.4037677724
Short name T26
Test name
Test status
Simulation time 493988404648 ps
CPU time 1127 seconds
Started Mar 31 12:43:11 PM PDT 24
Finished Mar 31 01:01:58 PM PDT 24
Peak memory 201916 kb
Host smart-bcd1c0ef-e190-455a-ad31-e3f9f0d2ea4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037677724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.4037677724
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.2912386982
Short name T455
Test name
Test status
Simulation time 323222388711 ps
CPU time 128.92 seconds
Started Mar 31 12:43:16 PM PDT 24
Finished Mar 31 12:45:26 PM PDT 24
Peak memory 201864 kb
Host smart-12d9fd75-d168-4823-946e-817421e37fe5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912386982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.2912386982
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3276355780
Short name T344
Test name
Test status
Simulation time 203622175657 ps
CPU time 485.22 seconds
Started Mar 31 12:43:16 PM PDT 24
Finished Mar 31 12:51:22 PM PDT 24
Peak memory 201892 kb
Host smart-def387f5-a2bc-4aa5-b05b-b283c318e878
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276355780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3276355780
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2561251893
Short name T542
Test name
Test status
Simulation time 125201240749 ps
CPU time 542.56 seconds
Started Mar 31 12:43:31 PM PDT 24
Finished Mar 31 12:52:33 PM PDT 24
Peak memory 202260 kb
Host smart-e892b999-28c8-4b4d-8d1d-9265c2497a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561251893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2561251893
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2710345296
Short name T615
Test name
Test status
Simulation time 22480805913 ps
CPU time 49.01 seconds
Started Mar 31 12:43:23 PM PDT 24
Finished Mar 31 12:44:12 PM PDT 24
Peak memory 201696 kb
Host smart-a6468e62-ec9c-4045-917d-07b2335f00d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710345296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2710345296
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.4186290134
Short name T335
Test name
Test status
Simulation time 3169127872 ps
CPU time 8.45 seconds
Started Mar 31 12:43:17 PM PDT 24
Finished Mar 31 12:43:25 PM PDT 24
Peak memory 201624 kb
Host smart-4d99c50c-3385-45b2-ae88-9226a95048a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186290134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.4186290134
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3873472467
Short name T666
Test name
Test status
Simulation time 5537455658 ps
CPU time 7.53 seconds
Started Mar 31 12:43:13 PM PDT 24
Finished Mar 31 12:43:21 PM PDT 24
Peak memory 201700 kb
Host smart-f717e3a7-f2ac-434c-bf55-6bb67ca4479b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873472467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3873472467
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.4071193378
Short name T781
Test name
Test status
Simulation time 208583955320 ps
CPU time 119.76 seconds
Started Mar 31 12:43:23 PM PDT 24
Finished Mar 31 12:45:23 PM PDT 24
Peak memory 201892 kb
Host smart-813d2de3-f724-4afb-9d41-0c517b52a85c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071193378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.4071193378
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.2331041983
Short name T22
Test name
Test status
Simulation time 50882694595 ps
CPU time 133.91 seconds
Started Mar 31 12:43:23 PM PDT 24
Finished Mar 31 12:45:38 PM PDT 24
Peak memory 210432 kb
Host smart-857fb65b-76eb-4ca6-84fa-54b69d07e198
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331041983 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.2331041983
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.4283120851
Short name T607
Test name
Test status
Simulation time 408659558 ps
CPU time 0.87 seconds
Started Mar 31 12:43:38 PM PDT 24
Finished Mar 31 12:43:40 PM PDT 24
Peak memory 201584 kb
Host smart-d2bc0788-79c1-4c4d-8171-a4b641585104
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283120851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.4283120851
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.706195134
Short name T491
Test name
Test status
Simulation time 178941268861 ps
CPU time 338.64 seconds
Started Mar 31 12:43:32 PM PDT 24
Finished Mar 31 12:49:11 PM PDT 24
Peak memory 201888 kb
Host smart-d882e1a6-a950-4678-88e0-17f8df34cf4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706195134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.706195134
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1838053768
Short name T633
Test name
Test status
Simulation time 165368072841 ps
CPU time 247.73 seconds
Started Mar 31 12:43:33 PM PDT 24
Finished Mar 31 12:47:41 PM PDT 24
Peak memory 201796 kb
Host smart-87160af0-e786-4c1a-bfe7-13f1c0bdf0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838053768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1838053768
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.4032184147
Short name T604
Test name
Test status
Simulation time 331528188183 ps
CPU time 542.78 seconds
Started Mar 31 12:43:34 PM PDT 24
Finished Mar 31 12:52:37 PM PDT 24
Peak memory 201844 kb
Host smart-17592d00-9ef9-4e0f-8800-356fc6501718
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032184147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.4032184147
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.4204152808
Short name T153
Test name
Test status
Simulation time 324255450398 ps
CPU time 686.62 seconds
Started Mar 31 12:43:31 PM PDT 24
Finished Mar 31 12:54:57 PM PDT 24
Peak memory 201964 kb
Host smart-5d02a7b6-bc55-4f0c-ba71-c70125960395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204152808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.4204152808
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2715814315
Short name T701
Test name
Test status
Simulation time 498653877828 ps
CPU time 324.35 seconds
Started Mar 31 12:43:31 PM PDT 24
Finished Mar 31 12:48:55 PM PDT 24
Peak memory 201892 kb
Host smart-de9cdf8e-3dc7-49f8-8f6d-bcbf748d902c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715814315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2715814315
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1446146979
Short name T587
Test name
Test status
Simulation time 659241810342 ps
CPU time 766.3 seconds
Started Mar 31 12:43:29 PM PDT 24
Finished Mar 31 12:56:16 PM PDT 24
Peak memory 201976 kb
Host smart-31990664-e3b4-4b99-b820-a5e8632486ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446146979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1446146979
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.744713535
Short name T673
Test name
Test status
Simulation time 411519492053 ps
CPU time 960.49 seconds
Started Mar 31 12:43:29 PM PDT 24
Finished Mar 31 12:59:30 PM PDT 24
Peak memory 201780 kb
Host smart-c78f67ec-35b6-476b-a7b9-c376dbc8b0f3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744713535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
adc_ctrl_filters_wakeup_fixed.744713535
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3235522426
Short name T193
Test name
Test status
Simulation time 117128953123 ps
CPU time 389.6 seconds
Started Mar 31 12:43:38 PM PDT 24
Finished Mar 31 12:50:08 PM PDT 24
Peak memory 202192 kb
Host smart-4719bdac-69ce-4d97-ba55-4a67db07d7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235522426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3235522426
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.1448555892
Short name T434
Test name
Test status
Simulation time 45179226291 ps
CPU time 24.38 seconds
Started Mar 31 12:43:29 PM PDT 24
Finished Mar 31 12:43:54 PM PDT 24
Peak memory 201696 kb
Host smart-8653020a-d2af-4a6d-9fb9-a4b270264422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448555892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.1448555892
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.3915818537
Short name T97
Test name
Test status
Simulation time 2835731137 ps
CPU time 2.19 seconds
Started Mar 31 12:43:31 PM PDT 24
Finished Mar 31 12:43:33 PM PDT 24
Peak memory 201704 kb
Host smart-6b093d95-e7d5-405d-b1e3-13c94280a718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915818537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.3915818537
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.2870853034
Short name T405
Test name
Test status
Simulation time 5565319943 ps
CPU time 4.26 seconds
Started Mar 31 12:43:23 PM PDT 24
Finished Mar 31 12:43:27 PM PDT 24
Peak memory 201580 kb
Host smart-f74e09bf-4680-4ac9-8076-be23352f01bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870853034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.2870853034
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1169807290
Short name T694
Test name
Test status
Simulation time 342361262412 ps
CPU time 414.71 seconds
Started Mar 31 12:43:37 PM PDT 24
Finished Mar 31 12:50:32 PM PDT 24
Peak memory 201864 kb
Host smart-a204c21d-f8f9-45e1-b1f2-baac57b53670
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169807290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1169807290
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1348736558
Short name T203
Test name
Test status
Simulation time 83762272177 ps
CPU time 247.92 seconds
Started Mar 31 12:43:35 PM PDT 24
Finished Mar 31 12:47:43 PM PDT 24
Peak memory 210796 kb
Host smart-312d71b4-1ded-4d05-8f7f-91eeb8faea09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348736558 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1348736558
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3873095971
Short name T345
Test name
Test status
Simulation time 341378458 ps
CPU time 1.48 seconds
Started Mar 31 12:43:46 PM PDT 24
Finished Mar 31 12:43:48 PM PDT 24
Peak memory 201544 kb
Host smart-4f14a2fe-1407-48c7-9e03-8137f37bd617
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873095971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3873095971
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.903594075
Short name T140
Test name
Test status
Simulation time 315970541962 ps
CPU time 197.35 seconds
Started Mar 31 12:43:48 PM PDT 24
Finished Mar 31 12:47:06 PM PDT 24
Peak memory 201860 kb
Host smart-e54909c3-54bc-4bcd-86d1-c7aeccd2d21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903594075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.903594075
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.709669167
Short name T219
Test name
Test status
Simulation time 329151885704 ps
CPU time 203.15 seconds
Started Mar 31 12:43:39 PM PDT 24
Finished Mar 31 12:47:02 PM PDT 24
Peak memory 201888 kb
Host smart-4c968c33-2eec-414b-bb81-8bc8b39db089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709669167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.709669167
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1926004709
Short name T463
Test name
Test status
Simulation time 163478279421 ps
CPU time 350.72 seconds
Started Mar 31 12:43:36 PM PDT 24
Finished Mar 31 12:49:26 PM PDT 24
Peak memory 201852 kb
Host smart-7445246d-a444-470e-b041-982d619f3a39
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926004709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1926004709
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2575005914
Short name T289
Test name
Test status
Simulation time 163923438554 ps
CPU time 203.99 seconds
Started Mar 31 12:43:48 PM PDT 24
Finished Mar 31 12:47:12 PM PDT 24
Peak memory 201860 kb
Host smart-da7450ab-d46e-40a1-8bc8-9f13e0302862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575005914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2575005914
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1320274469
Short name T333
Test name
Test status
Simulation time 162990621572 ps
CPU time 180.69 seconds
Started Mar 31 12:43:36 PM PDT 24
Finished Mar 31 12:46:38 PM PDT 24
Peak memory 201776 kb
Host smart-fa8ae1cc-9a7d-4b68-9c7c-68c9cb848893
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320274469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1320274469
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.3973195906
Short name T466
Test name
Test status
Simulation time 201441164495 ps
CPU time 223.42 seconds
Started Mar 31 12:43:48 PM PDT 24
Finished Mar 31 12:47:32 PM PDT 24
Peak memory 201840 kb
Host smart-a2c382cb-adec-405c-aab3-634d6c42e245
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973195906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.3973195906
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.2405693212
Short name T444
Test name
Test status
Simulation time 129288445481 ps
CPU time 404.83 seconds
Started Mar 31 12:43:42 PM PDT 24
Finished Mar 31 12:50:28 PM PDT 24
Peak memory 202168 kb
Host smart-bb1238f0-e608-4918-936d-528a18564578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405693212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2405693212
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.932497614
Short name T419
Test name
Test status
Simulation time 31799128934 ps
CPU time 8.84 seconds
Started Mar 31 12:43:36 PM PDT 24
Finished Mar 31 12:43:46 PM PDT 24
Peak memory 201620 kb
Host smart-c9672c6e-4f1a-4386-8bbc-48491bc293b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932497614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.932497614
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1862722420
Short name T765
Test name
Test status
Simulation time 5162829071 ps
CPU time 2.37 seconds
Started Mar 31 12:43:48 PM PDT 24
Finished Mar 31 12:43:51 PM PDT 24
Peak memory 201684 kb
Host smart-19861fde-4715-4a82-851f-b22fc5df9512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862722420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1862722420
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2697874946
Short name T42
Test name
Test status
Simulation time 6041293993 ps
CPU time 15.29 seconds
Started Mar 31 12:43:48 PM PDT 24
Finished Mar 31 12:44:04 PM PDT 24
Peak memory 201676 kb
Host smart-53eb8e7b-e87a-4b1a-8a13-ef25e4575900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697874946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2697874946
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.864883319
Short name T21
Test name
Test status
Simulation time 49447218531 ps
CPU time 125.72 seconds
Started Mar 31 12:43:45 PM PDT 24
Finished Mar 31 12:45:52 PM PDT 24
Peak memory 210404 kb
Host smart-4057baaa-00d4-41d2-95fe-1eddcc7ac85f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864883319 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.864883319
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1044563445
Short name T497
Test name
Test status
Simulation time 552950686 ps
CPU time 0.85 seconds
Started Mar 31 12:43:49 PM PDT 24
Finished Mar 31 12:43:50 PM PDT 24
Peak memory 201568 kb
Host smart-faed00c6-3fd5-40c4-93c3-0267e4247054
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044563445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1044563445
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.1009159702
Short name T486
Test name
Test status
Simulation time 483707616445 ps
CPU time 589.54 seconds
Started Mar 31 12:43:50 PM PDT 24
Finished Mar 31 12:53:40 PM PDT 24
Peak memory 201816 kb
Host smart-58dbf756-6e39-4089-8eb5-35dc6d1f4927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009159702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1009159702
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1323725669
Short name T664
Test name
Test status
Simulation time 326087925436 ps
CPU time 186.26 seconds
Started Mar 31 12:43:50 PM PDT 24
Finished Mar 31 12:46:56 PM PDT 24
Peak memory 201824 kb
Host smart-e5641be0-4ab8-4e51-b6eb-a86b9e547b87
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323725669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.1323725669
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.286032184
Short name T184
Test name
Test status
Simulation time 161655948410 ps
CPU time 100.72 seconds
Started Mar 31 12:43:42 PM PDT 24
Finished Mar 31 12:45:23 PM PDT 24
Peak memory 201868 kb
Host smart-2224ffc3-4e2f-4dce-a1be-00b1ae4a9728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286032184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.286032184
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.422095813
Short name T409
Test name
Test status
Simulation time 322008750741 ps
CPU time 201.34 seconds
Started Mar 31 12:43:43 PM PDT 24
Finished Mar 31 12:47:04 PM PDT 24
Peak memory 201892 kb
Host smart-b6cc1eac-c263-4d53-8c63-79206d6b89ca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=422095813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixe
d.422095813
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2941381898
Short name T161
Test name
Test status
Simulation time 672314688554 ps
CPU time 230.88 seconds
Started Mar 31 12:43:48 PM PDT 24
Finished Mar 31 12:47:39 PM PDT 24
Peak memory 201884 kb
Host smart-98685d84-5dd1-4fa6-a887-3be7f0ae326c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941381898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2941381898
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2881535101
Short name T579
Test name
Test status
Simulation time 597270771085 ps
CPU time 114.35 seconds
Started Mar 31 12:43:50 PM PDT 24
Finished Mar 31 12:45:44 PM PDT 24
Peak memory 201760 kb
Host smart-3362dde2-b475-4bae-ab0b-b8a48bb92f2b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881535101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2881535101
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.2590352407
Short name T548
Test name
Test status
Simulation time 88466025721 ps
CPU time 345.99 seconds
Started Mar 31 12:43:49 PM PDT 24
Finished Mar 31 12:49:35 PM PDT 24
Peak memory 202116 kb
Host smart-820d5fe8-5c72-4e97-9995-7d4ecc85b07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590352407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2590352407
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1384129470
Short name T423
Test name
Test status
Simulation time 23847946837 ps
CPU time 57.91 seconds
Started Mar 31 12:43:49 PM PDT 24
Finished Mar 31 12:44:47 PM PDT 24
Peak memory 201664 kb
Host smart-1b55289f-7cf3-45eb-8e8a-c4c547d31109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384129470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1384129470
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.392264223
Short name T103
Test name
Test status
Simulation time 4219595981 ps
CPU time 10.35 seconds
Started Mar 31 12:43:51 PM PDT 24
Finished Mar 31 12:44:01 PM PDT 24
Peak memory 201664 kb
Host smart-715c282a-9574-46f7-83a3-9f60f95cb44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392264223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.392264223
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1675294699
Short name T476
Test name
Test status
Simulation time 5600937330 ps
CPU time 3.18 seconds
Started Mar 31 12:43:44 PM PDT 24
Finished Mar 31 12:43:48 PM PDT 24
Peak memory 201700 kb
Host smart-f71ffcac-d455-4e01-b3e0-2d9da92043f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675294699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1675294699
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.1680335323
Short name T238
Test name
Test status
Simulation time 343970827816 ps
CPU time 386.4 seconds
Started Mar 31 12:43:50 PM PDT 24
Finished Mar 31 12:50:16 PM PDT 24
Peak memory 201924 kb
Host smart-c32353aa-fc78-49a7-9e35-284a861fde1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680335323 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.1680335323
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3721899989
Short name T554
Test name
Test status
Simulation time 134403962945 ps
CPU time 57.37 seconds
Started Mar 31 12:43:49 PM PDT 24
Finished Mar 31 12:44:46 PM PDT 24
Peak memory 202008 kb
Host smart-b22e64f9-7445-487e-bd69-c0dee24d9a16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721899989 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.3721899989
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.1278779479
Short name T13
Test name
Test status
Simulation time 505561147 ps
CPU time 1.66 seconds
Started Mar 31 12:43:56 PM PDT 24
Finished Mar 31 12:43:57 PM PDT 24
Peak memory 201520 kb
Host smart-32cd7773-59cd-4fe5-b565-3d15cff79159
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278779479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.1278779479
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.3081724856
Short name T524
Test name
Test status
Simulation time 166509828511 ps
CPU time 92.96 seconds
Started Mar 31 12:43:56 PM PDT 24
Finished Mar 31 12:45:30 PM PDT 24
Peak memory 201976 kb
Host smart-4144e72b-234b-4f55-aaf9-d243c7217229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081724856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.3081724856
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.3966755366
Short name T147
Test name
Test status
Simulation time 487545847130 ps
CPU time 1071.15 seconds
Started Mar 31 12:43:56 PM PDT 24
Finished Mar 31 01:01:47 PM PDT 24
Peak memory 201936 kb
Host smart-848b0c0c-be10-4810-a6df-f3e6293885b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966755366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.3966755366
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3357537641
Short name T9
Test name
Test status
Simulation time 493197240939 ps
CPU time 1140.91 seconds
Started Mar 31 12:43:56 PM PDT 24
Finished Mar 31 01:02:57 PM PDT 24
Peak memory 201780 kb
Host smart-50f9c482-abe1-4715-81cc-cdc54bc5346e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357537641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3357537641
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2132632653
Short name T771
Test name
Test status
Simulation time 327426166067 ps
CPU time 811.73 seconds
Started Mar 31 12:43:50 PM PDT 24
Finished Mar 31 12:57:22 PM PDT 24
Peak memory 201864 kb
Host smart-f9e5fdb2-6642-4ac3-9a7f-b19142159710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132632653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2132632653
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2488079550
Short name T551
Test name
Test status
Simulation time 497752015581 ps
CPU time 527.73 seconds
Started Mar 31 12:43:49 PM PDT 24
Finished Mar 31 12:52:37 PM PDT 24
Peak memory 201880 kb
Host smart-98b5ac20-f665-4cef-ac79-47d69a45bb5c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488079550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.2488079550
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.3273915914
Short name T540
Test name
Test status
Simulation time 376044180351 ps
CPU time 188.26 seconds
Started Mar 31 12:43:55 PM PDT 24
Finished Mar 31 12:47:04 PM PDT 24
Peak memory 201924 kb
Host smart-9dda995e-b62d-4457-80af-7217bdfdd799
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273915914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.3273915914
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2753402027
Short name T561
Test name
Test status
Simulation time 623518085141 ps
CPU time 798.93 seconds
Started Mar 31 12:43:56 PM PDT 24
Finished Mar 31 12:57:16 PM PDT 24
Peak memory 201760 kb
Host smart-6bcf339e-d996-4c1c-847b-806777076023
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753402027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2753402027
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.2356343954
Short name T784
Test name
Test status
Simulation time 96515960885 ps
CPU time 525.18 seconds
Started Mar 31 12:44:01 PM PDT 24
Finished Mar 31 12:52:47 PM PDT 24
Peak memory 202168 kb
Host smart-a22d2e70-3200-4506-b48b-45beb7dc3f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356343954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2356343954
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3746854874
Short name T648
Test name
Test status
Simulation time 31625402855 ps
CPU time 65.84 seconds
Started Mar 31 12:43:55 PM PDT 24
Finished Mar 31 12:45:01 PM PDT 24
Peak memory 201688 kb
Host smart-bc2084e5-9695-43f1-9fb1-5005b7909878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746854874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3746854874
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.3287097911
Short name T334
Test name
Test status
Simulation time 3685396506 ps
CPU time 2.07 seconds
Started Mar 31 12:43:56 PM PDT 24
Finished Mar 31 12:43:58 PM PDT 24
Peak memory 201656 kb
Host smart-6ef71e01-1bd2-4d4d-bf5f-cff5b49c2565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287097911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3287097911
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.124544564
Short name T637
Test name
Test status
Simulation time 5845322646 ps
CPU time 7.63 seconds
Started Mar 31 12:43:49 PM PDT 24
Finished Mar 31 12:43:57 PM PDT 24
Peak memory 201716 kb
Host smart-522d3df7-fb16-4162-9eec-5d10d130e647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124544564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.124544564
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1693870343
Short name T18
Test name
Test status
Simulation time 18964198098 ps
CPU time 16.92 seconds
Started Mar 31 12:43:58 PM PDT 24
Finished Mar 31 12:44:15 PM PDT 24
Peak memory 210640 kb
Host smart-0d3adb5d-a264-40da-a2c9-a5b2d3bab8d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693870343 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.1693870343
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.1763553987
Short name T699
Test name
Test status
Simulation time 405616750 ps
CPU time 0.88 seconds
Started Mar 31 12:40:12 PM PDT 24
Finished Mar 31 12:40:14 PM PDT 24
Peak memory 201572 kb
Host smart-c60e5ffd-eb80-4ee2-af0a-1b23d2713618
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763553987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.1763553987
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.1995233109
Short name T643
Test name
Test status
Simulation time 375256267014 ps
CPU time 812.08 seconds
Started Mar 31 12:40:06 PM PDT 24
Finished Mar 31 12:53:38 PM PDT 24
Peak memory 201916 kb
Host smart-c89df342-925f-4f5a-82fd-7e2cc4e1e718
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995233109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.1995233109
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3867830646
Short name T186
Test name
Test status
Simulation time 357344013557 ps
CPU time 220.89 seconds
Started Mar 31 12:40:07 PM PDT 24
Finished Mar 31 12:43:48 PM PDT 24
Peak memory 201872 kb
Host smart-10b52d62-b1ce-4833-84da-206d897dab1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867830646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3867830646
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1944653198
Short name T311
Test name
Test status
Simulation time 164797926505 ps
CPU time 99.29 seconds
Started Mar 31 12:40:11 PM PDT 24
Finished Mar 31 12:41:52 PM PDT 24
Peak memory 201980 kb
Host smart-6b56df4a-dea7-444e-89eb-ea27c41cc4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944653198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1944653198
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.4070641025
Short name T671
Test name
Test status
Simulation time 496197953910 ps
CPU time 1099.59 seconds
Started Mar 31 12:40:03 PM PDT 24
Finished Mar 31 12:58:23 PM PDT 24
Peak memory 201780 kb
Host smart-c575fc2b-1df2-424c-8d7f-41854226253b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070641025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.4070641025
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.978126828
Short name T735
Test name
Test status
Simulation time 508694297851 ps
CPU time 1202.28 seconds
Started Mar 31 12:40:01 PM PDT 24
Finished Mar 31 01:00:03 PM PDT 24
Peak memory 201868 kb
Host smart-509a6b4f-2c05-443a-b369-33e2188db023
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=978126828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.978126828
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1304383480
Short name T298
Test name
Test status
Simulation time 395654093583 ps
CPU time 142.08 seconds
Started Mar 31 12:40:01 PM PDT 24
Finished Mar 31 12:42:23 PM PDT 24
Peak memory 201960 kb
Host smart-06ec0089-a863-41fe-80be-e20751c6eb8e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304383480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1304383480
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2989988491
Short name T339
Test name
Test status
Simulation time 610438183245 ps
CPU time 706.21 seconds
Started Mar 31 12:40:05 PM PDT 24
Finished Mar 31 12:51:51 PM PDT 24
Peak memory 201888 kb
Host smart-cafd796e-bb93-4bcb-adf3-e198222cc2af
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989988491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2989988491
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.3648417994
Short name T32
Test name
Test status
Simulation time 106251607047 ps
CPU time 455.01 seconds
Started Mar 31 12:40:10 PM PDT 24
Finished Mar 31 12:47:46 PM PDT 24
Peak memory 202136 kb
Host smart-6642d2a0-dcea-490a-9675-a71eafe7e2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648417994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.3648417994
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.990946850
Short name T504
Test name
Test status
Simulation time 32184884961 ps
CPU time 76.03 seconds
Started Mar 31 12:40:01 PM PDT 24
Finished Mar 31 12:41:18 PM PDT 24
Peak memory 201684 kb
Host smart-5d48f3eb-3342-4f4d-aa52-057e51985135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990946850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.990946850
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1433658758
Short name T379
Test name
Test status
Simulation time 4311099472 ps
CPU time 9.57 seconds
Started Mar 31 12:40:03 PM PDT 24
Finished Mar 31 12:40:13 PM PDT 24
Peak memory 201684 kb
Host smart-cb1f8082-db9b-44ed-95be-5eba6bf2e1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433658758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1433658758
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.4280829193
Short name T658
Test name
Test status
Simulation time 5972442666 ps
CPU time 4.92 seconds
Started Mar 31 12:40:00 PM PDT 24
Finished Mar 31 12:40:05 PM PDT 24
Peak memory 201644 kb
Host smart-154a9464-cf9b-446f-89f9-0a68bfca1ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280829193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.4280829193
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2893029316
Short name T236
Test name
Test status
Simulation time 165898984564 ps
CPU time 22.76 seconds
Started Mar 31 12:40:00 PM PDT 24
Finished Mar 31 12:40:23 PM PDT 24
Peak memory 201840 kb
Host smart-e9f29244-fad5-4d57-8dba-6dc5e0302187
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893029316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2893029316
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1148343729
Short name T17
Test name
Test status
Simulation time 56442732514 ps
CPU time 115.82 seconds
Started Mar 31 12:40:04 PM PDT 24
Finished Mar 31 12:42:00 PM PDT 24
Peak memory 217720 kb
Host smart-f9bb5124-b3d4-4e9a-978a-01264bfb3c84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148343729 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1148343729
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2915446141
Short name T383
Test name
Test status
Simulation time 433499440 ps
CPU time 0.86 seconds
Started Mar 31 12:40:02 PM PDT 24
Finished Mar 31 12:40:03 PM PDT 24
Peak memory 201576 kb
Host smart-b29b8d6b-92d7-4052-825c-fbac938bb113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915446141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2915446141
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2828945255
Short name T501
Test name
Test status
Simulation time 508405208925 ps
CPU time 519.74 seconds
Started Mar 31 12:40:11 PM PDT 24
Finished Mar 31 12:48:52 PM PDT 24
Peak memory 201960 kb
Host smart-1af7a2ad-2ed5-41d3-b778-019a105e013d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828945255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2828945255
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.2559245800
Short name T299
Test name
Test status
Simulation time 550779612192 ps
CPU time 1392.18 seconds
Started Mar 31 12:40:02 PM PDT 24
Finished Mar 31 01:03:14 PM PDT 24
Peak memory 201912 kb
Host smart-0fbdaca2-96f7-455b-9fde-d2ca0f8745c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559245800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.2559245800
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.982541054
Short name T170
Test name
Test status
Simulation time 323105382662 ps
CPU time 168.05 seconds
Started Mar 31 12:40:09 PM PDT 24
Finished Mar 31 12:42:57 PM PDT 24
Peak memory 201884 kb
Host smart-4dfd252c-11c5-4ec1-9866-10f20810ced1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982541054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.982541054
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.422889142
Short name T722
Test name
Test status
Simulation time 334753889028 ps
CPU time 755.96 seconds
Started Mar 31 12:39:59 PM PDT 24
Finished Mar 31 12:52:35 PM PDT 24
Peak memory 201840 kb
Host smart-bf231559-dc26-4860-aae6-bdc61d2761ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=422889142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.422889142
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1611012447
Short name T691
Test name
Test status
Simulation time 327578598116 ps
CPU time 734.94 seconds
Started Mar 31 12:40:09 PM PDT 24
Finished Mar 31 12:52:25 PM PDT 24
Peak memory 201760 kb
Host smart-c0ae6cec-1273-4bef-9367-4c2f8d408126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611012447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1611012447
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.1967939718
Short name T567
Test name
Test status
Simulation time 491681899959 ps
CPU time 1116.39 seconds
Started Mar 31 12:40:04 PM PDT 24
Finished Mar 31 12:58:41 PM PDT 24
Peak memory 201864 kb
Host smart-9623f948-838b-47e9-a055-6af0f677ce3b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967939718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.1967939718
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2937480974
Short name T294
Test name
Test status
Simulation time 616173486616 ps
CPU time 1548.61 seconds
Started Mar 31 12:40:06 PM PDT 24
Finished Mar 31 01:05:55 PM PDT 24
Peak memory 201992 kb
Host smart-265ce21b-723c-46fb-8d2c-92007a69530e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937480974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2937480974
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.1693988373
Short name T452
Test name
Test status
Simulation time 197680211714 ps
CPU time 430.88 seconds
Started Mar 31 12:40:10 PM PDT 24
Finished Mar 31 12:47:22 PM PDT 24
Peak memory 201820 kb
Host smart-e511bef1-ba23-4fee-abb7-420977514b20
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693988373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.1693988373
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.2267421673
Short name T474
Test name
Test status
Simulation time 100330401808 ps
CPU time 367.54 seconds
Started Mar 31 12:40:08 PM PDT 24
Finished Mar 31 12:46:15 PM PDT 24
Peak memory 202260 kb
Host smart-9feac72f-3cd0-4514-9b9d-ada0654bb427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267421673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2267421673
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.218431465
Short name T676
Test name
Test status
Simulation time 37194310488 ps
CPU time 80.92 seconds
Started Mar 31 12:40:08 PM PDT 24
Finished Mar 31 12:41:29 PM PDT 24
Peak memory 201588 kb
Host smart-aaab3fa8-d682-43b5-8786-258824d36f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218431465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.218431465
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.4136191781
Short name T650
Test name
Test status
Simulation time 2956286906 ps
CPU time 4.01 seconds
Started Mar 31 12:40:10 PM PDT 24
Finished Mar 31 12:40:15 PM PDT 24
Peak memory 201492 kb
Host smart-ecd3ead8-8e7a-43db-9249-63035017bf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136191781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.4136191781
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2193476634
Short name T520
Test name
Test status
Simulation time 6145126270 ps
CPU time 5.12 seconds
Started Mar 31 12:40:03 PM PDT 24
Finished Mar 31 12:40:08 PM PDT 24
Peak memory 201704 kb
Host smart-428ce6db-4149-4c36-9a21-4bd0f5b63a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193476634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2193476634
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3510284898
Short name T774
Test name
Test status
Simulation time 195919062318 ps
CPU time 247.83 seconds
Started Mar 31 12:40:09 PM PDT 24
Finished Mar 31 12:44:18 PM PDT 24
Peak memory 201920 kb
Host smart-a5c2b37a-5a0d-44af-a418-86d1577bdf97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510284898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3510284898
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2144822896
Short name T28
Test name
Test status
Simulation time 98553841246 ps
CPU time 180.7 seconds
Started Mar 31 12:40:06 PM PDT 24
Finished Mar 31 12:43:07 PM PDT 24
Peak memory 218252 kb
Host smart-ec05091e-dbd6-49ee-ab8c-cb3612f3d930
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144822896 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.2144822896
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.853235838
Short name T331
Test name
Test status
Simulation time 489334826 ps
CPU time 1.23 seconds
Started Mar 31 12:40:08 PM PDT 24
Finished Mar 31 12:40:09 PM PDT 24
Peak memory 201588 kb
Host smart-0ede1876-50fc-41e0-8b8e-232a3e183e74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853235838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.853235838
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1307850593
Short name T234
Test name
Test status
Simulation time 356975010909 ps
CPU time 397.3 seconds
Started Mar 31 12:39:58 PM PDT 24
Finished Mar 31 12:46:36 PM PDT 24
Peak memory 201888 kb
Host smart-c140ebfa-47ca-46c8-84dd-cd1b120829eb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307850593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1307850593
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2432412394
Short name T471
Test name
Test status
Simulation time 161444733660 ps
CPU time 70.26 seconds
Started Mar 31 12:40:00 PM PDT 24
Finished Mar 31 12:41:11 PM PDT 24
Peak memory 201988 kb
Host smart-8517a0d3-7e26-4ae1-ba68-60b0001cab0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432412394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2432412394
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.2670144019
Short name T516
Test name
Test status
Simulation time 164988769427 ps
CPU time 100.71 seconds
Started Mar 31 12:39:55 PM PDT 24
Finished Mar 31 12:41:36 PM PDT 24
Peak memory 201944 kb
Host smart-7a95971f-4259-4fc1-975a-071750f01ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670144019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.2670144019
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.449138118
Short name T778
Test name
Test status
Simulation time 493832628624 ps
CPU time 223.83 seconds
Started Mar 31 12:40:01 PM PDT 24
Finished Mar 31 12:43:45 PM PDT 24
Peak memory 201864 kb
Host smart-b6137c7e-2048-44ab-bb9f-23c0f34f5a1a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=449138118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt
_fixed.449138118
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.797172848
Short name T537
Test name
Test status
Simulation time 322528850185 ps
CPU time 200.34 seconds
Started Mar 31 12:40:05 PM PDT 24
Finished Mar 31 12:43:26 PM PDT 24
Peak memory 201768 kb
Host smart-5a3d31e6-4536-49b7-9109-bb4754bebf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797172848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.797172848
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3740202563
Short name T550
Test name
Test status
Simulation time 327792901589 ps
CPU time 57.61 seconds
Started Mar 31 12:40:02 PM PDT 24
Finished Mar 31 12:41:00 PM PDT 24
Peak memory 201796 kb
Host smart-0accc3ac-7db0-4219-b48c-a40edbe3a53e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740202563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3740202563
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.3027267310
Short name T152
Test name
Test status
Simulation time 360277756190 ps
CPU time 519.43 seconds
Started Mar 31 12:40:10 PM PDT 24
Finished Mar 31 12:48:50 PM PDT 24
Peak memory 201904 kb
Host smart-94955f30-a676-44db-8341-ec6a582fcccc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027267310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.3027267310
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1763887711
Short name T63
Test name
Test status
Simulation time 603558570428 ps
CPU time 345.63 seconds
Started Mar 31 12:40:09 PM PDT 24
Finished Mar 31 12:45:56 PM PDT 24
Peak memory 201836 kb
Host smart-e7d3aae6-ec50-461b-9003-2edfd471bb6f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763887711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1763887711
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.533604410
Short name T200
Test name
Test status
Simulation time 94084532240 ps
CPU time 333.43 seconds
Started Mar 31 12:40:02 PM PDT 24
Finished Mar 31 12:45:35 PM PDT 24
Peak memory 202164 kb
Host smart-a78d8bb3-eacf-47ed-8508-1e1916f810d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533604410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.533604410
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2284640680
Short name T581
Test name
Test status
Simulation time 25784765923 ps
CPU time 15.87 seconds
Started Mar 31 12:40:10 PM PDT 24
Finished Mar 31 12:40:26 PM PDT 24
Peak memory 201680 kb
Host smart-7db76abf-2f5f-47dc-8c44-23eb59b57452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284640680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2284640680
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.1550349596
Short name T435
Test name
Test status
Simulation time 3782449494 ps
CPU time 6.06 seconds
Started Mar 31 12:40:05 PM PDT 24
Finished Mar 31 12:40:11 PM PDT 24
Peak memory 201692 kb
Host smart-d1f02996-7b6e-4c43-973a-34a22c02a40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550349596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1550349596
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.2581977715
Short name T502
Test name
Test status
Simulation time 5740498963 ps
CPU time 4.28 seconds
Started Mar 31 12:40:08 PM PDT 24
Finished Mar 31 12:40:12 PM PDT 24
Peak memory 201684 kb
Host smart-aaa845b5-791a-4a34-815f-10f2bce2566f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581977715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.2581977715
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.4034993939
Short name T649
Test name
Test status
Simulation time 168341513280 ps
CPU time 316.81 seconds
Started Mar 31 12:40:11 PM PDT 24
Finished Mar 31 12:45:29 PM PDT 24
Peak memory 201936 kb
Host smart-55570efd-0612-4af2-b120-b46d3298ff7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034993939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
4034993939
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.1027743483
Short name T54
Test name
Test status
Simulation time 28403435800 ps
CPU time 64.08 seconds
Started Mar 31 12:40:09 PM PDT 24
Finished Mar 31 12:41:15 PM PDT 24
Peak memory 210252 kb
Host smart-73d820b3-213f-4455-8ced-284d7a9abf4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027743483 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.1027743483
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1703385950
Short name T555
Test name
Test status
Simulation time 429069565 ps
CPU time 1.12 seconds
Started Mar 31 12:40:01 PM PDT 24
Finished Mar 31 12:40:02 PM PDT 24
Peak memory 201512 kb
Host smart-b129abe4-f123-40d0-bd8e-29c4f180a48b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703385950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1703385950
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.3592040289
Short name T40
Test name
Test status
Simulation time 163132288442 ps
CPU time 409 seconds
Started Mar 31 12:40:05 PM PDT 24
Finished Mar 31 12:46:54 PM PDT 24
Peak memory 201972 kb
Host smart-2be06010-b34d-4adb-9f6c-f9c4b1a9da9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592040289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.3592040289
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.751963345
Short name T730
Test name
Test status
Simulation time 494595791009 ps
CPU time 1118.85 seconds
Started Mar 31 12:40:05 PM PDT 24
Finished Mar 31 12:58:44 PM PDT 24
Peak memory 201860 kb
Host smart-7ad89a49-cea5-4e11-9b3f-3bf282f7d1ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=751963345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.751963345
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2807901404
Short name T315
Test name
Test status
Simulation time 328083750986 ps
CPU time 156.79 seconds
Started Mar 31 12:40:05 PM PDT 24
Finished Mar 31 12:42:42 PM PDT 24
Peak memory 201888 kb
Host smart-859de455-a3b1-461b-986e-906c5acf0328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807901404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2807901404
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.4285777651
Short name T421
Test name
Test status
Simulation time 160983503614 ps
CPU time 67.67 seconds
Started Mar 31 12:40:01 PM PDT 24
Finished Mar 31 12:41:09 PM PDT 24
Peak memory 201792 kb
Host smart-b03a550f-ebd6-432d-a7d7-74e6ec07a2f2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285777651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.4285777651
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2152994963
Short name T293
Test name
Test status
Simulation time 534054008991 ps
CPU time 1216.82 seconds
Started Mar 31 12:40:02 PM PDT 24
Finished Mar 31 01:00:19 PM PDT 24
Peak memory 201816 kb
Host smart-eb91f487-22bd-4df9-9d2a-8ed29075342c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152994963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2152994963
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3813189540
Short name T708
Test name
Test status
Simulation time 191957802955 ps
CPU time 265.36 seconds
Started Mar 31 12:40:00 PM PDT 24
Finished Mar 31 12:44:26 PM PDT 24
Peak memory 201808 kb
Host smart-a18b601c-d38b-437a-abc9-f56058b9de75
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813189540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3813189540
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2428977078
Short name T196
Test name
Test status
Simulation time 109446941952 ps
CPU time 388.67 seconds
Started Mar 31 12:40:03 PM PDT 24
Finished Mar 31 12:46:32 PM PDT 24
Peak memory 202160 kb
Host smart-659e3285-7075-4e93-b72f-21d3497a3610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428977078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2428977078
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.88367128
Short name T660
Test name
Test status
Simulation time 38550448584 ps
CPU time 22.64 seconds
Started Mar 31 12:40:07 PM PDT 24
Finished Mar 31 12:40:29 PM PDT 24
Peak memory 201676 kb
Host smart-44e68836-4f37-4cac-b41e-816c6d1eb574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88367128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.88367128
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.705112259
Short name T460
Test name
Test status
Simulation time 4661584433 ps
CPU time 1.82 seconds
Started Mar 31 12:40:01 PM PDT 24
Finished Mar 31 12:40:03 PM PDT 24
Peak memory 201604 kb
Host smart-368bf8e2-581b-485e-a500-cd4c0900d936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705112259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.705112259
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.336549843
Short name T697
Test name
Test status
Simulation time 6072805123 ps
CPU time 15.59 seconds
Started Mar 31 12:40:08 PM PDT 24
Finished Mar 31 12:40:24 PM PDT 24
Peak memory 201700 kb
Host smart-0c883dd2-216e-4bf6-9815-65c963dc5df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336549843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.336549843
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.966357119
Short name T582
Test name
Test status
Simulation time 313756194997 ps
CPU time 441.74 seconds
Started Mar 31 12:40:03 PM PDT 24
Finished Mar 31 12:47:25 PM PDT 24
Peak memory 212676 kb
Host smart-ceb83d5c-3a9c-49cb-8e39-be8f525eb0b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966357119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.966357119
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.98987274
Short name T457
Test name
Test status
Simulation time 304597401 ps
CPU time 1.3 seconds
Started Mar 31 12:40:02 PM PDT 24
Finished Mar 31 12:40:03 PM PDT 24
Peak memory 201820 kb
Host smart-172d2111-b048-4c37-8333-c1a789c08493
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98987274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.98987274
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.2793314947
Short name T798
Test name
Test status
Simulation time 503343631401 ps
CPU time 167.09 seconds
Started Mar 31 12:40:00 PM PDT 24
Finished Mar 31 12:42:47 PM PDT 24
Peak memory 201812 kb
Host smart-c9072713-141a-4083-8b07-67d79100eea5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793314947 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.2793314947
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1055050955
Short name T498
Test name
Test status
Simulation time 166633970329 ps
CPU time 400.37 seconds
Started Mar 31 12:39:58 PM PDT 24
Finished Mar 31 12:46:38 PM PDT 24
Peak memory 201816 kb
Host smart-d7081abb-bc59-47b9-98c4-3994f49e522e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055050955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1055050955
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1296607921
Short name T10
Test name
Test status
Simulation time 485320904279 ps
CPU time 1171.59 seconds
Started Mar 31 12:40:03 PM PDT 24
Finished Mar 31 12:59:35 PM PDT 24
Peak memory 201768 kb
Host smart-1368477d-5250-43fe-ad52-c9d0723ecb1d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296607921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.1296607921
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3215172026
Short name T106
Test name
Test status
Simulation time 328282678030 ps
CPU time 745.42 seconds
Started Mar 31 12:40:08 PM PDT 24
Finished Mar 31 12:52:33 PM PDT 24
Peak memory 201756 kb
Host smart-cea8aba6-4b22-4064-a86e-dc4c7d815cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215172026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3215172026
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.1882988361
Short name T629
Test name
Test status
Simulation time 325970160387 ps
CPU time 180.59 seconds
Started Mar 31 12:40:03 PM PDT 24
Finished Mar 31 12:43:04 PM PDT 24
Peak memory 201792 kb
Host smart-90f7e820-f01c-496a-9567-5d25278fc061
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882988361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.1882988361
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.863663680
Short name T41
Test name
Test status
Simulation time 381565992357 ps
CPU time 353.08 seconds
Started Mar 31 12:40:09 PM PDT 24
Finished Mar 31 12:46:02 PM PDT 24
Peak memory 201796 kb
Host smart-9ce07f49-35ce-498c-a343-80c09cf67712
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863663680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_w
akeup.863663680
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2628679743
Short name T683
Test name
Test status
Simulation time 395998071202 ps
CPU time 811.3 seconds
Started Mar 31 12:40:04 PM PDT 24
Finished Mar 31 12:53:36 PM PDT 24
Peak memory 201752 kb
Host smart-9152133e-74fd-4b6d-acc4-56a6ede3d77e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628679743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2628679743
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.823718886
Short name T197
Test name
Test status
Simulation time 126539105676 ps
CPU time 650.22 seconds
Started Mar 31 12:40:01 PM PDT 24
Finished Mar 31 12:50:51 PM PDT 24
Peak memory 202248 kb
Host smart-5a526c27-dc72-4356-8afd-5e4c9ac2b46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823718886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.823718886
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3790244762
Short name T710
Test name
Test status
Simulation time 37250334206 ps
CPU time 89.33 seconds
Started Mar 31 12:40:02 PM PDT 24
Finished Mar 31 12:41:31 PM PDT 24
Peak memory 201612 kb
Host smart-3ed20382-f21b-41ab-acd8-3d480c1af0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790244762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3790244762
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.2332768978
Short name T356
Test name
Test status
Simulation time 3819841692 ps
CPU time 2.03 seconds
Started Mar 31 12:40:07 PM PDT 24
Finished Mar 31 12:40:10 PM PDT 24
Peak memory 201612 kb
Host smart-62ad57c4-7096-419a-8805-675b630612a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332768978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.2332768978
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.2990990579
Short name T346
Test name
Test status
Simulation time 5562472501 ps
CPU time 13.98 seconds
Started Mar 31 12:40:02 PM PDT 24
Finished Mar 31 12:40:17 PM PDT 24
Peak memory 201612 kb
Host smart-041dd7e1-40c7-4682-92b0-87e212aa9a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990990579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.2990990579
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2262520993
Short name T635
Test name
Test status
Simulation time 173309984393 ps
CPU time 84.89 seconds
Started Mar 31 12:40:08 PM PDT 24
Finished Mar 31 12:41:33 PM PDT 24
Peak memory 201864 kb
Host smart-60d34972-899d-4951-8f28-c03e04f25112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262520993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2262520993
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1385983687
Short name T20
Test name
Test status
Simulation time 67425211743 ps
CPU time 155.57 seconds
Started Mar 31 12:40:09 PM PDT 24
Finished Mar 31 12:42:45 PM PDT 24
Peak memory 210480 kb
Host smart-f4a2c3d0-ca30-43a5-8d53-fb44a77ac419
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385983687 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.1385983687
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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