Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6683	1			T2	6		T6	20		T9	35
testmodes[AdcCtrlTestmodeNormal]	5650	1			T1	1		T2	4		T5	3
testmodes[AdcCtrlTestmodeLowpower]	5626	1			T3	3		T8	12		T9	24
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3498	1			T2	1		T6	19		T9	17
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1699	1			T2	4		T9	17		T27	11
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1375	1			T9	1		T27	10		T38	10
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1717	1			T2	4		T9	17		T27	13
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2094	1			T5	2		T7	1		T9	12
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1495	1			T9	1		T10	1		T27	17
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1357	1			T9	1		T27	8		T38	13
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1512	1			T9	1		T26	1		T27	19
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2516	1			T3	2		T8	11		T9	21