Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26166

1

T1

1

T2

10

T3

35

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22595

1

T1

1

T2

10

T3

35

auto[ADC_CTRL_FILTER_COND_OUT]

3571

1

T5

2

T9

1

T10

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20315

1

T2

10

T5

3

T6

20

auto[1]

5851

1

T1

1

T3

35

T9

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22173

1

T1

1

T2

10

T3

35

auto[1]

3993

1

T9

6

T10

23

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	34	1			T217	15		T218	19		-	-
values[0]	79	1			T139	1		T170	8		T219	13
values[1]	764	1			T9	7		T13	9		T25	36
values[2]	562	1			T5	1		T28	1		T48	22
values[3]	866	1			T37	11		T33	2		T220	7
values[4]	745	1			T7	1		T37	20		T221	3
values[5]	664	1			T10	36		T26	19		T28	1
values[6]	627	1			T221	33		T165	1		T151	25
values[7]	744	1			T5	1		T9	1		T28	1
values[8]	2865	1			T1	1		T3	35		T9	6
values[9]	1190	1			T5	1		T7	1		T25	10
minimum	17026	1			T2	10		T6	20		T8	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	920	1			T9	7		T13	9		T25	36
values[1]	764	1			T5	1		T28	1		T48	22
values[2]	752	1			T37	31		T33	2		T222	11
values[3]	816	1			T7	1		T10	13		T28	1
values[4]	569	1			T10	23		T26	19		T221	33
values[5]	641	1			T37	7		T151	25		T152	1
values[6]	2990	1			T1	1		T3	35		T5	1
values[7]	514	1			T9	6		T26	1		T28	1
values[8]	1013	1			T5	1		T25	10		T26	28
values[9]	160	1			T7	1		T223	1		T143	26
minimum	17027	1			T2	10		T6	20		T8	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

4214

1

T3

32

T9

4

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T9	5		T25	17		T27	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T13	9		T25	6		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T48	13		T153	15		T136	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	1		T28	1		T220	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T37	11		T33	1		T223	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T37	20		T222	1		T137	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	1		T10	1		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T47	10		T142	15		T70	31
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T221	18		T141	1		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T10	12		T26	11		T163	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T152	1		T222	1		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T37	7		T151	15		T224	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1615	1			T1	1		T3	35		T5	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T9	1		T135	14		T138	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T9	4		T28	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T26	1		T153	15		T68	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T221	7		T151	13		T144	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T5	1		T25	7		T26	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T7	1		T70	17		T225	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T223	1		T143	14		T226	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16891	1			T2	10		T6	20		T8	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T9	2		T25	8		T27	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T25	5		T227	8		T138	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T48	9		T220	3		T139	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T220	3		T228	9		T229	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T33	1		T230	9		T231	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T222	10		T137	10		T232	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T10	12		T203	1		T219	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T47	6		T139	9		T170	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T221	15		T182	7		T87	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T10	11		T26	8		T233	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T222	2		T234	10		T235	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T151	10		T138	11		T182	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1026	1			T11	8		T140	28		T166	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T138	1		T228	13		T77	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T9	2		T137	1		T18	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T36	7		T236	10		T32	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T144	10		T143	2		T145	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T25	3		T26	14		T47	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T225	2		T237	11		T98	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T143	12		T226	2		T238	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	2		T33	3		T34	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T217	9		T218	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T170	1		T188	3		T239	21
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T139	1		T219	1		T199	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T9	5		T25	17		T27	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T13	9		T25	6		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T48	13		T153	15		T136	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T5	1		T28	1		T220	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T37	11		T33	1		T220	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T137	10		T216	10		T20	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	1		T221	3		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T37	20		T47	10		T222	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T10	1		T28	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T10	12		T26	11		T163	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T221	18		T83	1		T240	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T165	1		T151	15		T233	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	1		T28	1		T152	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T9	1		T37	7		T135	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1636	1			T1	1		T3	35		T9	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T153	15		T68	1		T36	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T7	1		T221	7		T151	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T5	1		T25	7		T26	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16890	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T217	6		T218	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T170	7		T188	2		T239	21
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T219	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T9	2		T25	8		T27	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T25	5		T227	8		T138	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T48	9		T139	9		T182	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T220	3		T228	9		T229	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T33	1		T220	3		T230	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T137	10		T216	11		T20	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T203	1		T241	6		T242	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T47	6		T222	10		T139	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T10	12		T222	2		T182	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T10	11		T26	8		T170	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T221	15		T234	10		T235	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T151	10		T233	13		T16	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T243	12		T169	9		T244	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T138	1		T182	9		T228	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	981	1			T9	2		T11	8		T140	28
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T36	7		T79	9		T245	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T144	10		T143	1		T145	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T25	3		T26	14		T47	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T9	5		T25	9		T27	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T13	1		T25	6		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T48	10		T153	1		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T5	1		T28	1		T220	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T37	1		T33	2		T223	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T37	1		T222	11		T137	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T7	1		T10	13		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T47	7		T142	1		T70	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T221	16		T141	1		T182	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T10	12		T26	9		T163	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T152	1		T222	3		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T37	1		T151	11		T224	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1356	1			T1	1		T3	3		T5	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T9	1		T135	1		T138	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T9	4		T28	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T26	1		T153	1		T68	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T221	1		T151	1		T144	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T5	1		T25	4		T26	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T7	1		T70	1		T225	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T223	1		T143	13		T226	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17027	1			T2	10		T6	20		T8	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T9	2		T25	16		T27	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T13	8		T25	5		T227	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T48	12		T153	14		T136	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T220	20		T229	11		T246	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T37	10		T191	16		T230	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T37	19		T137	9		T216	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T221	2		T247	13		T219	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T47	9		T142	14		T70	29
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T221	17		T248	6		T249	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	11		T26	10		T163	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T240	12		T235	26		T149	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T37	6		T151	14		T224	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T3	32		T12	18		T14	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T135	13		T77	3		T183	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T9	2		T136	1		T18	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T153	14		T36	8		T203	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T221	6		T151	12		T144	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T25	6		T26	13		T47	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T70	16		T225	2		T237	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T143	13		T226	2		T250	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T217	7		T218	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T170	8		T188	3		T239	24
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T139	1		T219	13		T199	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	5		T25	9		T27	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T13	1		T25	6		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T48	10		T153	1		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T5	1		T28	1		T220	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T37	1		T33	2		T220	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T137	11		T216	12		T20	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T7	1		T221	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T37	1		T47	7		T222	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T10	13		T28	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	12		T26	9		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T221	16		T83	1		T240	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T165	1		T151	11		T233	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T5	1		T28	1		T152	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T9	1		T37	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1312	1			T1	1		T3	3		T9	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T153	1		T68	1		T36	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	385	1			T7	1		T221	1		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T5	1		T25	4		T26	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17026	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T217	8		T218	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T188	2		T239	18		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T199	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T9	2		T25	16		T27	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T13	8		T25	5		T227	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T48	12		T153	14		T136	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T220	20		T229	11		T246	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T37	10		T220	3		T191	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T137	9		T216	9		T20	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T221	2		T241	4		T247	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T37	19		T47	9		T142	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T219	7		T208	9		T249	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T10	11		T26	10		T163	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T221	17		T240	12		T235	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T151	14		T16	1		T224	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T17	2		T243	13		T169	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T37	6		T135	13		T77	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1305	1			T3	32		T9	2		T12	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T153	14		T36	8		T79	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T221	6		T151	12		T144	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T25	6		T26	13		T47	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

4214

1

T3

32

T9

4

T10

11

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26166

1

T1

1

T2

10

T3

35

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22551

1

T1

1

T2

10

T3

35

auto[ADC_CTRL_FILTER_COND_OUT]

3615

1

T5

1

T7

2

T9

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19936

1

T2

10

T5

2

T6

20

auto[1]

6230

1

T1

1

T3

35

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22173

1

T1

1

T2

10

T3

35

auto[1]

3993

1

T9

6

T10

23

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	27	1			T251	11		T252	16		-	-
values[0]	17	1			T196	12		T253	5		-	-
values[1]	645	1			T7	1		T25	10		T28	1
values[2]	705	1			T9	6		T223	1		T137	2
values[3]	746	1			T5	1		T221	3		T47	1
values[4]	2811	1			T1	1		T3	35		T5	1
values[5]	588	1			T7	1		T9	8		T141	1
values[6]	615	1			T13	9		T47	16		T48	22
values[7]	844	1			T37	18		T152	2		T153	15
values[8]	871	1			T10	13		T26	19		T37	20
values[9]	1271	1			T5	1		T10	23		T25	11
minimum	17026	1			T2	10		T6	20		T8	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	757	1			T7	1		T25	10		T221	33
values[1]	774	1			T9	6		T47	1		T34	3
values[2]	638	1			T5	1		T221	3		T163	9
values[3]	2911	1			T1	1		T3	35		T5	1
values[4]	677	1			T7	1		T9	7		T33	2
values[5]	541	1			T13	9		T47	16		T48	22
values[6]	902	1			T10	13		T26	19		T37	18
values[7]	786	1			T37	20		T47	22		T151	13
values[8]	860	1			T5	1		T10	23		T26	29
values[9]	293	1			T25	11		T28	2		T135	14
minimum	17027	1			T2	10		T6	20		T8	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

4214

1

T3

32

T9

4

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T25	7		T221	18		T165	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T7	1		T227	1		T138	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T9	4		T47	1		T34	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T222	1		T17	4		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	1		T227	16		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T221	3		T163	9		T142	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1655	1			T1	1		T3	35		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T5	1		T9	1		T254	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T33	1		T141	1		T222	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T7	1		T9	5		T233	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T13	9		T48	13		T243	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T47	10		T153	15		T223	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T26	11		T37	18		T220	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T10	1		T33	2		T152	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T153	15		T220	4		T137	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T37	20		T47	11		T151	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	1		T26	14		T27	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T10	12		T26	1		T130	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T28	1		T135	14		T136	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T25	6		T28	1		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16890	1			T2	10		T6	20		T8	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T28	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T25	3		T221	15		T151	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T227	8		T138	11		T170	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T9	2		T228	13		T156	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T222	10		T137	1		T145	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T227	12		T73	8		T145	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T84	12		T149	10		T237	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	994	1			T11	8		T25	8		T140	28
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T255	1		T242	1		T22	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T33	1		T222	2		T225	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T9	2		T233	13		T154	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T48	9		T243	12		T149	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T47	6		T143	1		T36	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T26	8		T220	3		T18	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T10	12		T33	1		T19	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T220	3		T137	10		T79	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T47	11		T16	2		T137	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T26	14		T27	1		T182	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T10	11		T130	20		T144	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T170	7		T32	11		T256	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T25	5		T257	14		T193	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	2		T33	3		T34	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T251	1		T252	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T196	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T253	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T25	7		T221	18		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T7	1		T28	1		T227	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T9	4		T223	1		T179	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T137	1		T145	13		T232	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	1		T47	1		T227	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T221	3		T222	1		T142	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1619	1			T1	1		T3	35		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	1		T254	1		T163	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T141	1		T18	2		T71	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T7	1		T9	6		T233	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T13	9		T48	13		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T47	10		T136	16		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T37	18		T220	21		T42	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T152	2		T153	15		T142	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T26	11		T153	15		T220	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T10	1		T37	20		T33	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T5	1		T26	14		T27	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	420	1			T10	12		T25	6		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16890	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T251	10		T252	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T196	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T253	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T25	3		T221	15		T151	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T227	8		T138	11		T170	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T9	2		T228	13		T241	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T137	1		T145	10		T232	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T227	12		T145	12		T203	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T222	10		T84	12		T231	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	955	1			T11	8		T25	8		T140	28
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T242	1		T22	16		T258	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T18	2		T230	9		T225	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T9	2		T233	13		T154	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T48	9		T33	1		T182	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T47	6		T143	1		T225	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T220	3		T243	12		T79	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T36	7		T19	12		T148	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T26	8		T220	3		T137	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	12		T33	1		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T26	14		T27	1		T182	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T10	11		T25	5		T47	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	2		T33	3		T34	1