Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26166

1

T1

1

T2

10

T3

35

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22664

1

T1

1

T2

10

T3

35

auto[ADC_CTRL_FILTER_COND_OUT]

3502

1

T5

2

T7

1

T9

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20351

1

T2

10

T5

2

T6

20

auto[1]

5815

1

T1

1

T3

35

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22173

1

T1

1

T2

10

T3

35

auto[1]

3993

1

T9

6

T10

23

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	87	1			T136	16		T266	46		T262	1
values[0]	64	1			T170	7		T32	16		T293	1
values[1]	650	1			T7	1		T13	9		T28	1
values[2]	808	1			T10	13		T25	25		T28	1
values[3]	765	1			T5	1		T9	6		T135	14
values[4]	648	1			T5	2		T25	11		T27	5
values[5]	2922	1			T1	1		T3	35		T11	9
values[6]	649	1			T37	20		T130	39		T141	1
values[7]	825	1			T10	23		T26	19		T254	1
values[8]	638	1			T9	7		T152	1		T220	7
values[9]	1084	1			T7	1		T9	1		T25	10
minimum	17026	1			T2	10		T6	20		T8	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	917	1			T7	1		T28	2		T151	25
values[1]	732	1			T9	6		T10	13		T13	9
values[2]	751	1			T5	1		T25	25		T27	5
values[3]	2957	1			T1	1		T3	35		T5	2
values[4]	632	1			T163	9		T227	7		T141	1
values[5]	726	1			T26	19		T37	20		T130	39
values[6]	759	1			T10	23		T254	1		T47	1
values[7]	645	1			T9	7		T25	10		T165	1
values[8]	775	1			T7	1		T9	1		T26	1
values[9]	232	1			T26	28		T221	7		T47	22
minimum	17040	1			T2	10		T6	20		T8	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

4214

1

T3

32

T9

4

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T7	1		T28	1		T17	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T28	1		T151	15		T145	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T10	1		T13	9		T221	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	4		T135	14		T70	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T5	1		T25	17		T33	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T27	4		T141	1		T34	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1615	1			T1	1		T3	35		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T5	2		T37	18		T221	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T227	3		T152	1		T18	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T163	9		T141	1		T143	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T26	11		T37	20		T142	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T130	19		T152	1		T153	30
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T254	1		T220	4		T137	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T10	12		T47	1		T68	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T9	5		T73	1		T207	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T25	7		T165	1		T223	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	1		T227	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T7	1		T26	1		T47	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T26	14		T221	7		T47	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T139	1		T170	1		T262	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16890	1			T2	10		T6	20		T8	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T323	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T143	1		T138	1		T71	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T151	10		T145	10		T182	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T10	12		T48	9		T33	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	2		T139	9		T42	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T25	8		T33	1		T16	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T27	1		T222	10		T233	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	936	1			T11	8		T25	5		T140	28
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T221	15		T230	9		T228	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T227	4		T18	9		T36	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T143	12		T138	13		T148	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T26	8		T154	15		T225	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T130	20		T243	12		T32	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T220	3		T137	1		T138	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	11		T182	9		T268	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T9	2		T73	8		T169	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T25	3		T137	10		T182	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T227	8		T18	2		T228	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T47	6		T144	10		T227	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T26	14		T47	11		T222	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T170	7		T324	1		T272	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	2		T33	3		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T323	13		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T136	16		T325	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T266	24		T262	1		T326	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T293	1		T184	13		T327	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T170	1		T32	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	1		T13	9		T48	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T28	1		T151	15		T145	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T10	1		T25	17		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T70	11		T139	7		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T5	1		T221	3		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T9	4		T135	14		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T25	6		T28	1		T203	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T5	2		T27	4		T37	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1605	1			T1	1		T3	35		T11	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T163	9		T71	6		T230	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T37	20		T154	14		T83	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T130	19		T141	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T26	11		T254	1		T142	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T10	12		T47	1		T182	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T9	5		T152	1		T220	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T223	1		T137	10		T68	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T9	1		T26	14		T221	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T7	1		T25	7		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16890	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T266	22		T290	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T327	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T170	6		T32	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T48	9		T143	1		T138	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T151	10		T145	10		T79	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T10	12		T25	8		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T139	9		T182	15		T42	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T33	1		T77	6		T203	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T9	2		T233	13		T143	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T25	5		T203	1		T242	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T27	1		T221	15		T222	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	974	1			T11	8		T140	28		T166	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T230	9		T259	11		T242	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T154	15		T225	2		T237	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T130	20		T138	13		T243	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T26	8		T138	11		T145	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T10	11		T182	9		T268	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T9	2		T220	3		T137	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T137	10		T235	11		T95	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T26	14		T47	11		T227	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T25	3		T47	6		T144	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T7	1		T28	1		T17	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T28	1		T151	11		T145	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T10	13		T13	1		T221	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T9	4		T135	1		T70	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T5	1		T25	9		T33	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T27	4		T141	1		T34	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T1	1		T3	3		T11	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	2		T37	2		T221	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T227	5		T152	1		T18	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T163	1		T141	1		T143	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T26	9		T37	1		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T130	21		T152	1		T153	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T254	1		T220	4		T137	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T10	12		T47	1		T68	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	5		T73	9		T207	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T25	4		T165	1		T223	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T9	1		T227	9		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T7	1		T26	1		T47	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T26	15		T221	1		T47	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T139	1		T170	8		T262	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17026	1			T2	10		T6	20		T8	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T323	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T17	2		T139	9		T84	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T151	14		T145	12		T241	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	8		T221	2		T48	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T9	2		T135	13		T70	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T25	16		T16	1		T142	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T27	1		T220	20		T19	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T3	32		T12	18		T14	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T37	16		T221	17		T224	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T227	2		T18	2		T36	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T163	8		T143	13		T138	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T26	10		T37	19		T142	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T130	18		T153	28		T243	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T220	3		T137	12		T138	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T10	11		T183	11		T256	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	2		T207	4		T169	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T25	6		T137	9		T179	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T136	1		T70	16		T18	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T47	9		T151	12		T144	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T26	13		T221	6		T47	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T289	18		T277	5		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T136	1		T325	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T266	23		T262	1		T326	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T293	1		T184	1		T327	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T170	7		T32	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T7	1		T13	1		T48	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T28	1		T151	11		T145	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T10	13		T25	9		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T70	1		T139	10		T182	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T5	1		T221	1		T33	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T9	4		T135	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T25	6		T28	1		T203	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	2		T27	4		T37	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T1	1		T3	3		T11	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T163	1		T71	1		T230	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T37	1		T154	16		T83	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T130	21		T141	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T26	9		T254	1		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T10	12		T47	1		T182	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T9	5		T152	1		T220	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T223	1		T137	11		T68	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T9	1		T26	15		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T7	1		T25	4		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17026	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T136	15		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T266	23		T290	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T184	12		T327	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T32	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T13	8		T48	12		T84	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T151	14		T145	12		T241	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T25	16		T16	1		T17	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T70	10		T139	6		T42	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T221	2		T142	14		T191	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T9	2		T135	13		T247	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T25	5		T203	3		T275	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T27	1		T37	16		T221	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T3	32		T12	18		T14	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T163	8		T71	5		T230	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T37	19		T154	13		T225	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T130	18		T153	28		T138	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T26	10		T142	14		T138	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T10	11		T183	11		T219	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T9	2		T220	3		T137	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T137	9		T179	12		T235	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T26	13		T221	6		T47	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T25	6		T47	9		T151	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

4214

1

T3

32

T9

4

T10

11