Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26166

1

T1

1

T2

10

T3

35

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22687

1

T1

1

T2

10

T3

35

auto[ADC_CTRL_FILTER_COND_OUT]

3479

1

T5

2

T9

1

T10

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20223

1

T2

10

T5

3

T6

20

auto[1]

5943

1

T1

1

T3

35

T9

14

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22173

1

T1

1

T2

10

T3

35

auto[1]

3993

1

T9

6

T10

23

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	270	1			T47	22		T223	1		T18	4
values[0]	28	1			T263	18		T320	10		-	-
values[1]	774	1			T9	7		T13	9		T25	36
values[2]	620	1			T5	1		T28	1		T48	22
values[3]	832	1			T37	11		T33	2		T220	7
values[4]	785	1			T7	1		T37	20		T221	3
values[5]	657	1			T10	36		T26	19		T28	1
values[6]	556	1			T221	33		T165	1		T151	25
values[7]	760	1			T5	1		T9	1		T37	7
values[8]	2837	1			T1	1		T3	35		T9	6
values[9]	1021	1			T5	1		T7	1		T25	10
minimum	17026	1			T2	10		T6	20		T8	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	678	1			T13	9		T25	11		T27	5
values[1]	755	1			T5	1		T28	1		T48	22
values[2]	758	1			T37	31		T47	16		T33	2
values[3]	818	1			T7	1		T10	13		T28	1
values[4]	562	1			T10	23		T26	19		T221	33
values[5]	712	1			T37	7		T165	1		T151	25
values[6]	2866	1			T1	1		T3	35		T5	1
values[7]	569	1			T9	6		T26	1		T28	1
values[8]	1053	1			T5	1		T7	1		T25	10
values[9]	119	1			T223	1		T70	17		T225	5
minimum	17276	1			T2	10		T6	20		T8	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

4214

1

T3

32

T9

4

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T27	4		T130	19		T33	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	9		T25	6		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T48	13		T153	15		T136	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	1		T28	1		T220	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T37	11		T47	10		T33	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T37	20		T137	10		T232	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T7	1		T10	1		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T222	1		T142	15		T70	31
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T221	18		T141	1		T222	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T10	12		T26	11		T163	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T152	1		T146	1		T83	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T37	7		T165	1		T151	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1582	1			T1	1		T3	35		T5	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T9	1		T135	14		T228	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T9	4		T28	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T26	1		T254	1		T153	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T7	1		T221	7		T151	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T5	1		T25	7		T26	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T70	17		T225	3		T237	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T223	1		T226	3		T238	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16955	1			T2	10		T6	20		T8	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T148	1		T170	1		T263	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T27	1		T130	20		T33	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T25	5		T227	8		T138	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T48	9		T220	3		T139	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T220	3		T228	9		T216	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T47	6		T33	1		T230	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T137	10		T232	1		T20	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T10	12		T219	10		T320	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T222	10		T139	9		T170	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T221	15		T222	2		T182	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T10	11		T26	8		T16	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T234	10		T235	24		T149	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T151	10		T233	13		T138	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T11	8		T140	28		T166	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T228	13		T77	6		T21	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T9	2		T137	1		T18	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T36	7		T245	11		T236	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T144	10		T143	1		T18	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T25	3		T26	14		T47	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T225	2		T237	11		T98	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T226	2		T238	6		T250	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T9	4		T25	8		T33	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T148	11		T170	6		T328	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T18	2		T225	3		T226	20
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T47	11		T223	1		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T320	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T263	18		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T9	5		T25	17		T27	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T13	9		T25	6		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T48	13		T130	19		T153	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	1		T28	1		T220	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T37	11		T33	1		T220	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T137	10		T216	10		T20	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	1		T221	3		T47	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T37	20		T222	1		T142	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T10	1		T28	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T10	12		T26	11		T163	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T221	18		T152	1		T83	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T165	1		T151	15		T233	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	1		T152	1		T17	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T9	1		T37	7		T135	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1634	1			T1	1		T3	35		T9	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T153	15		T68	1		T36	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T7	1		T221	7		T151	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T5	1		T25	7		T26	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16890	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T18	2		T225	2		T226	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T47	11		T238	6		T217	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T320	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	2		T25	8		T27	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T25	5		T227	8		T138	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T48	9		T130	20		T139	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T220	3		T228	9		T229	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T33	1		T220	3		T230	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T137	10		T216	11		T20	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T47	6		T83	2		T203	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T222	10		T139	9		T232	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T10	12		T222	2		T182	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T10	11		T26	8		T170	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T221	15		T234	10		T235	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T151	10		T233	13		T16	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T138	1		T243	12		T169	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T182	9		T228	13		T77	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	954	1			T9	2		T11	8		T140	28
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T36	7		T245	11		T236	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T144	10		T143	1		T71	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T25	3		T26	14		T227	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T27	4		T130	21		T33	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	1		T25	6		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T48	10		T153	1		T136	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T5	1		T28	1		T220	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T37	1		T47	7		T33	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T37	1		T137	11		T232	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	1		T10	13		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T222	11		T142	1		T70	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T221	16		T141	1		T222	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T10	12		T26	9		T163	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T152	1		T146	1		T83	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T37	1		T165	1		T151	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T1	1		T3	3		T5	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T9	1		T135	1		T228	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T9	4		T28	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T26	1		T254	1		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T7	1		T221	1		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T5	1		T25	4		T26	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T70	1		T225	3		T237	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T223	1		T226	3		T238	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17099	1			T2	10		T6	20		T8	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T148	12		T170	7		T263	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T27	1		T130	18		T137	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	8		T25	5		T227	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T48	12		T153	14		T136	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T220	20		T216	9		T229	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T37	10		T47	9		T179	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T37	19		T137	9		T20	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T221	2		T247	13		T172	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T142	14		T70	29		T139	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T221	17		T248	6		T249	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	11		T26	10		T163	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T240	12		T235	26		T149	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T37	6		T151	14		T224	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T3	32		T12	18		T14	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T135	13		T77	3		T183	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T9	2		T142	14		T136	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T153	14		T36	8		T203	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T221	6		T151	12		T144	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T25	6		T26	13		T47	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T70	16		T225	2		T237	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T226	2		T250	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T9	2		T25	16		T95	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T263	17		T328	16		T199	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T18	3		T225	3		T226	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T47	12		T223	1		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T320	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T263	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T9	5		T25	9		T27	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	1		T25	6		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T48	10		T130	21		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T5	1		T28	1		T220	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T37	1		T33	2		T220	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T137	11		T216	12		T20	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	1		T221	1		T47	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T37	1		T222	11		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T10	13		T28	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T10	12		T26	9		T163	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T221	16		T152	1		T83	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T165	1		T151	11		T233	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T5	1		T152	1		T17	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T9	1		T37	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T1	1		T3	3		T9	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T153	1		T68	1		T36	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	350	1			T7	1		T221	1		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T5	1		T25	4		T26	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17026	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T18	1		T225	2		T226	19
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T47	10		T207	4		T158	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T263	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	2		T25	16		T27	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T13	8		T25	5		T227	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T48	12		T130	18		T153	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T220	20		T229	11		T246	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T37	10		T220	3		T179	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T137	9		T216	9		T20	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T221	2		T47	9		T241	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T37	19		T142	14		T70	29
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T219	7		T249	9		T270	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T10	11		T26	10		T163	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T221	17		T240	12		T235	26
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T151	14		T16	1		T224	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T17	2		T243	13		T169	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T37	6		T135	13		T77	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T3	32		T9	2		T12	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T153	14		T36	8		T203	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T221	6		T151	12		T144	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T25	6		T26	13		T143	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

4214

1

T3

32

T9

4

T10

11