Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26166

1

T1

1

T2

10

T3

35

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22429

1

T1

1

T2

10

T3

35

auto[ADC_CTRL_FILTER_COND_OUT]

3737

1

T5

3

T7

1

T9

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19996

1

T2

10

T5

3

T6

20

auto[1]

6170

1

T1

1

T3

35

T9

6

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22173

1

T1

1

T2

10

T3

35

auto[1]

3993

1

T9

6

T10

23

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	61	1			T283	11		T199	10		T301	32
values[0]	44	1			T221	7		T256	27		T329	1
values[1]	751	1			T5	1		T47	1		T227	21
values[2]	841	1			T9	6		T25	10		T26	28
values[3]	812	1			T37	18		T221	3		T151	13
values[4]	765	1			T5	1		T7	1		T10	23
values[5]	521	1			T26	1		T254	1		T130	39
values[6]	676	1			T25	11		T27	5		T47	16
values[7]	647	1			T13	9		T26	19		T47	22
values[8]	642	1			T5	1		T9	8		T10	13
values[9]	3380	1			T1	1		T3	35		T7	1
minimum	17026	1			T2	10		T6	20		T8	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1012	1			T5	1		T26	28		T221	7
values[1]	777	1			T9	6		T25	10		T37	18
values[2]	846	1			T221	36		T152	1		T233	14
values[3]	713	1			T5	1		T7	1		T10	23
values[4]	617	1			T151	25		T130	39		T33	2
values[5]	533	1			T25	11		T27	5		T47	16
values[6]	2905	1			T1	1		T3	35		T9	1
values[7]	664	1			T5	1		T9	7		T26	19
values[8]	846	1			T7	1		T28	1		T152	1
values[9]	184	1			T222	3		T71	12		T169	19
minimum	17069	1			T2	10		T6	20		T8	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

4214

1

T3

32

T9

4

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T221	7		T47	1		T34	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T5	1		T26	14		T227	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T37	11		T151	13		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T9	4		T25	7		T37	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T221	3		T17	4		T68	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T221	18		T152	1		T233	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T25	17		T28	1		T135	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	1		T7	1		T10	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T151	15		T142	15		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T130	19		T33	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T47	10		T191	17		T83	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T25	6		T27	4		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1635	1			T1	1		T3	35		T9	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T13	9		T28	1		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T163	9		T16	5		T142	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	1		T9	5		T26	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	1		T28	1		T18	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T152	1		T154	14		T138	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T271	5		T263	13		T256	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T222	1		T71	1		T169	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16898	1			T2	10		T6	20		T8	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T238	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T182	9		T77	6		T79	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T26	14		T227	8		T145	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T137	10		T182	7		T232	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T9	2		T25	3		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T230	9		T244	7		T257	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T221	15		T233	13		T143	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T25	8		T48	9		T227	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T10	11		T170	11		T259	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T151	10		T138	1		T203	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T130	20		T33	1		T220	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T47	6		T83	2		T330	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T25	5		T27	1		T143	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	985	1			T10	12		T11	8		T140	28
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T222	10		T145	12		T79	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T16	2		T173	18		T249	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T9	2		T26	8		T144	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T18	9		T228	13		T225	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T154	15		T138	13		T36	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T271	1		T256	9		T324	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T222	2		T71	11		T169	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T9	2		T33	3		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T238	11		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T283	11		T331	8		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T199	10		T301	17		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T221	7		T329	1		T261	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T256	11		T23	4		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T47	1		T34	3		T153	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T5	1		T227	13		T70	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T141	1		T153	15		T137	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T9	4		T25	7		T26	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T37	11		T221	3		T151	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T37	7		T227	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T25	17		T28	1		T135	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T5	1		T7	1		T10	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T254	1		T142	15		T220	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T26	1		T130	19		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T47	10		T151	15		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T25	6		T27	4		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T47	11		T165	1		T137	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T13	9		T26	11		T138	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T9	1		T10	1		T16	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T5	1		T9	5		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1695	1			T1	1		T3	35		T7	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T152	1		T222	1		T143	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16890	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T301	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T256	16		T23	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T182	9		T79	9		T226	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T227	8		T216	11		T245	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T137	10		T77	6		T231	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T9	2		T25	3		T26	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T182	7		T230	9		T232	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T227	8		T148	11		T203	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T25	8		T48	9		T227	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T10	11		T233	13		T143	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T220	3		T225	9		T156	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T130	20		T33	1		T148	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T47	6		T151	10		T138	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T25	5		T27	1		T220	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T47	11		T137	1		T18	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T26	8		T138	11		T145	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T10	12		T16	2		T84	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T9	2		T144	10		T222	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1047	1			T11	8		T140	28		T166	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T222	2		T143	12		T154	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T221	1		T47	1		T34	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T5	1		T26	15		T227	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T37	1		T151	1		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T9	4		T25	4		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T221	1		T17	2		T68	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T221	16		T152	1		T233	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T25	9		T28	1		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T5	1		T7	1		T10	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T151	11		T142	1		T138	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T130	21		T33	2		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T47	7		T191	1		T83	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T25	6		T27	4		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T1	1		T3	3		T9	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T13	1		T28	1		T222	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T163	1		T16	6		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	1		T9	5		T26	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	1		T28	1		T18	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T152	1		T154	16		T138	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T271	5		T263	1		T256	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T222	3		T71	12		T169	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17037	1			T2	10		T6	20		T8	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T238	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T221	6		T153	28		T77	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T26	13		T227	12		T70	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T37	10		T151	12		T137	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T9	2		T25	6		T37	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T221	2		T17	2		T230	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T221	17		T155	12		T235	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T25	16		T135	13		T48	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T10	11		T37	19		T259	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T151	14		T142	14		T207	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T130	18		T220	3		T224	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T47	9		T191	16		T32	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T25	5		T27	1		T179	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1312	1			T3	32		T12	18		T14	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T13	8		T70	10		T71	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T163	8		T16	1		T142	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T9	2		T26	10		T144	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T18	2		T191	9		T225	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T154	13		T138	13		T179	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T271	1		T263	12		T256	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T169	14		T172	12		T332	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T219	7		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T238	13		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T283	1		T331	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T199	1		T301	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T221	1		T329	1		T261	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T256	17		T23	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T47	1		T34	3		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T5	1		T227	9		T70	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T141	1		T153	1		T137	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T9	4		T25	4		T26	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T37	1		T221	1		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T37	1		T227	9		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T25	9		T28	1		T135	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	1		T7	1		T10	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T254	1		T142	1		T220	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T26	1		T130	21		T33	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T47	7		T151	11		T138	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T25	6		T27	4		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T47	12		T165	1		T137	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	1		T26	9		T138	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T9	1		T10	13		T16	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T5	1		T9	5		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1416	1			T1	1		T3	3		T7	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	364	1			T152	1		T222	3		T143	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17026	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T283	10		T331	7		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T199	9		T301	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T221	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T256	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T153	14		T79	7		T183	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T227	12		T70	16		T216	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T153	14		T137	9		T77	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T9	2		T25	6		T26	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T37	10		T221	2		T151	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T37	6		T20	10		T235	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T25	16		T135	13		T48	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T10	11		T37	19		T155	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T142	14		T220	20		T225	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T130	18		T224	17		T259	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T47	9		T151	14		T191	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T25	5		T27	1		T220	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T47	10		T137	12		T18	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T13	8		T26	10		T138	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T16	1		T142	14		T84	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T9	2		T144	11		T136	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T3	32		T12	18		T14	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T143	13		T154	13		T138	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

4214

1

T3

32

T9

4

T10

11