Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26166

1

T1

1

T2

10

T3

35

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22681

1

T1

1

T2

10

T3

35

auto[ADC_CTRL_FILTER_COND_OUT]

3485

1

T7

1

T10

13

T13

9

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20100

1

T2

10

T5

2

T6

20

auto[1]

6066

1

T1

1

T3

35

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22173

1

T1

1

T2

10

T3

35

auto[1]

3993

1

T9

6

T10

23

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	837	1			T9	5		T27	10		T221	3
values[0]	37	1			T141	1		T147	1		T208	13
values[1]	716	1			T5	1		T25	10		T47	16
values[2]	2904	1			T1	1		T3	35		T7	1
values[3]	743	1			T130	39		T33	3		T152	1
values[4]	608	1			T5	2		T26	28		T27	5
values[5]	719	1			T10	23		T25	25		T37	11
values[6]	621	1			T9	7		T13	9		T221	7
values[7]	763	1			T26	19		T28	2		T135	14
values[8]	647	1			T141	1		T223	2		T191	17
values[9]	1046	1			T7	1		T9	6		T10	13
minimum	16525	1			T2	10		T6	20		T8	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	652	1			T5	1		T25	10		T37	7
values[1]	2934	1			T1	1		T3	35		T7	1
values[2]	763	1			T26	28		T33	3		T152	1
values[3]	655	1			T5	2		T25	25		T27	5
values[4]	560	1			T10	23		T13	9		T254	1
values[5]	724	1			T9	7		T135	14		T221	7
values[6]	799	1			T26	19		T28	2		T47	22
values[7]	593	1			T25	11		T221	33		T141	1
values[8]	1069	1			T7	1		T9	7		T10	13
values[9]	122	1			T227	21		T71	6		T287	3
minimum	17295	1			T2	10		T6	20		T8	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

4214

1

T3

32

T9

4

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	1		T37	7		T142	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T25	7		T34	3		T153	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1612	1			T1	1		T3	35		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	1		T154	14		T139	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T26	14		T137	10		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T33	2		T152	1		T220	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	2		T28	1		T37	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T25	17		T27	4		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T10	12		T254	1		T153	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T13	9		T35	1		T79	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T9	5		T222	1		T137	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T135	14		T221	7		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T26	11		T136	2		T240	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T28	2		T47	11		T151	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T25	6		T221	18		T68	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T141	1		T223	2		T70	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T7	1		T9	5		T144	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T10	1		T26	1		T221	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T227	13		T287	1		T333	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T71	6		T334	1		T201	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16963	1			T2	10		T6	20		T8	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T141	1		T146	1		T147	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T225	2		T245	11		T156	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T25	3		T220	3		T138	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1003	1			T11	8		T140	28		T166	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T154	15		T139	9		T230	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T26	14		T137	10		T182	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T33	1		T220	3		T145	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T335	10		T173	1		T97	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T25	8		T27	1		T143	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	11		T16	2		T73	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T79	15		T170	11		T248	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T9	2		T222	10		T137	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T33	1		T227	4		T222	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T26	8		T235	11		T237	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T47	11		T151	10		T143	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T25	5		T221	15		T216	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T79	9		T83	2		T225	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T9	2		T144	10		T227	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T10	12		T48	9		T18	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T227	8		T287	2		T307	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T250	11		T316	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	2		T47	6		T33	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T266	22		T193	8		T249	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	572	1			T9	5		T27	10		T38	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T221	3		T47	1		T18	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T293	1		T299	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T141	1		T147	1		T208	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	1		T47	10		T142	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T25	7		T34	3		T220	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1622	1			T1	1		T3	35		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	1		T153	15		T139	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T130	19		T137	10		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T33	2		T152	1		T220	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	2		T26	14		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T27	4		T152	1		T70	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T10	12		T37	11		T163	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T25	17		T143	14		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	5		T254	1		T222	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	9		T221	7		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T26	11		T136	2		T137	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T28	2		T135	14		T47	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T147	1		T216	10		T257	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T141	1		T223	2		T191	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T7	1		T9	4		T25	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T10	1		T26	1		T165	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16389	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T149	9		T32	12		T24	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T18	9		T277	10		T336	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T299	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T47	6		T225	2		T156	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T25	3		T220	3		T154	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T11	8		T140	28		T166	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T139	9		T230	9		T148	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T130	20		T137	10		T42	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T33	1		T220	3		T170	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T26	14		T182	15		T97	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T27	1		T139	9		T145	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T10	11		T16	2		T73	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T25	8		T143	12		T182	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T9	2		T222	10		T138	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T33	1		T227	4		T222	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T26	8		T137	1		T235	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T47	11		T151	10		T143	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T216	11		T257	23		T32	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T83	2		T225	9		T235	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T9	2		T25	5		T221	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T10	12		T48	9		T36	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	1		T37	1		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T25	4		T34	3		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1329	1			T1	1		T3	3		T11	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	1		T154	16		T139	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T26	15		T137	11		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T33	3		T152	1		T220	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T5	2		T28	1		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T25	9		T27	4		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T10	12		T254	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T13	1		T35	1		T79	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T9	5		T222	11		T137	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T135	1		T221	1		T33	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T26	9		T136	1		T240	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T28	2		T47	12		T151	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T25	6		T221	16		T68	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T141	1		T223	2		T70	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T7	1		T9	5		T144	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T10	13		T26	1		T221	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T227	9		T287	3		T333	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T71	1		T334	1		T201	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17060	1			T2	10		T6	20		T8	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T141	1		T146	1		T147	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T37	6		T142	14		T225	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T25	6		T153	14		T220	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T3	32		T12	18		T14	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T154	13		T139	9		T230	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T26	13		T137	9		T42	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T220	20		T145	12		T191	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T37	10		T163	8		T142	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T25	16		T27	1		T143	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T10	11		T153	14		T16	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T13	8		T248	6		T337	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T9	2		T137	12		T138	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T135	13		T221	6		T227	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T26	10		T136	1		T240	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T47	10		T151	14		T77	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T25	5		T221	17		T216	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T70	19		T191	16		T79	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T9	2		T144	11		T17	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T221	2		T151	12		T48	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T227	12		T338	20		T339	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T71	5		T250	10		T316	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T47	9		T179	12		T171	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T266	23		T193	10		T208	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	585	1			T9	5		T27	10		T38	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T221	1		T47	1		T18	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T293	1		T299	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T141	1		T147	1		T208	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T5	1		T47	7		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T25	4		T34	3		T220	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T1	1		T3	3		T11	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T7	1		T153	1		T139	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T130	21		T137	11		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T33	3		T152	1		T220	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	2		T26	15		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T27	4		T152	1		T70	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T10	12		T37	1		T163	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T25	9		T143	13		T182	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T9	5		T254	1		T222	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T13	1		T221	1		T33	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T26	9		T136	1		T137	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T28	2		T135	1		T47	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T147	1		T216	12		T257	25
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T141	1		T223	2		T191	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T7	1		T9	4		T25	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T10	13		T26	1		T165	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16525	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T17	2		T149	8		T32	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T221	2		T18	2		T183	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T299	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T208	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T47	9		T142	14		T179	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T25	6		T220	3		T154	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1293	1			T3	32		T12	18		T14	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T153	14		T139	9		T230	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T130	18		T137	9		T42	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T220	20		T191	9		T275	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T26	13		T142	14		T157	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T27	1		T70	16		T139	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T10	11		T37	10		T163	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T25	16		T143	13		T84	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T9	2		T138	13		T70	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	8		T221	6		T227	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T26	10		T136	1		T137	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T135	13		T47	10		T151	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T216	9		T257	11		T260	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T191	16		T225	8		T235	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T9	2		T25	5		T221	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T151	12		T48	12		T136	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

4214

1

T3

32

T9

4

T10

11