Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26166

1

T1

1

T2

10

T3

35

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22558

1

T1

1

T2

10

T3

35

auto[ADC_CTRL_FILTER_COND_OUT]

3608

1

T5

1

T7

2

T9

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19865

1

T2

10

T5

2

T6

20

auto[1]

6301

1

T1

1

T3

35

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22173

1

T1

1

T2

10

T3

35

auto[1]

3993

1

T9

6

T10

23

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	397	1			T26	28		T28	1		T130	39
values[0]	36	1			T200	15		T186	21		-	-
values[1]	643	1			T7	1		T25	10		T28	1
values[2]	666	1			T9	6		T223	1		T137	2
values[3]	729	1			T5	1		T221	3		T47	1
values[4]	2855	1			T1	1		T3	35		T5	1
values[5]	589	1			T7	1		T9	7		T33	2
values[6]	658	1			T13	9		T47	16		T48	22
values[7]	814	1			T10	13		T26	19		T37	18
values[8]	922	1			T37	20		T151	13		T33	3
values[9]	831	1			T5	1		T10	23		T25	11
minimum	17026	1			T2	10		T6	20		T8	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	554	1			T7	1		T25	10		T165	1
values[1]	761	1			T9	6		T47	1		T34	3
values[2]	593	1			T5	1		T221	3		T254	1
values[3]	2930	1			T1	1		T3	35		T5	1
values[4]	707	1			T7	1		T9	7		T33	2
values[5]	527	1			T13	9		T47	16		T48	22
values[6]	947	1			T10	13		T26	19		T37	38
values[7]	745	1			T47	22		T151	13		T153	15
values[8]	981	1			T5	1		T10	23		T26	29
values[9]	172	1			T25	11		T27	5		T28	1
minimum	17249	1			T2	10		T6	20		T8	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

4214

1

T3

32

T9

4

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T25	7		T165	1		T151	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T7	1		T227	1		T17	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T9	4		T47	1		T34	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T222	1		T137	1		T145	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	1		T227	16		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T221	3		T254	1		T163	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1641	1			T1	1		T3	35		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T5	1		T9	1		T265	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T33	1		T141	1		T222	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T7	1		T9	5		T233	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T13	9		T48	13		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T47	10		T153	15		T223	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T26	11		T37	18		T220	21
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T10	1		T37	20		T33	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T153	15		T220	4		T137	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T47	11		T151	13		T16	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T5	1		T26	14		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T10	12		T26	1		T130	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T27	4		T135	14		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T25	6		T28	1		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16942	1			T2	10		T6	20		T8	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T28	1		T70	11		T340	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T25	3		T151	10		T143	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T227	8		T138	11		T170	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T9	2		T156	2		T259	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T222	10		T137	1		T145	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T227	12		T145	12		T228	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T84	12		T149	10		T237	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	972	1			T11	8		T25	8		T140	28
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T255	1		T242	1		T22	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T33	1		T222	2		T225	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T9	2		T233	13		T154	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T48	9		T182	7		T243	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T47	6		T143	1		T36	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T26	8		T220	3		T18	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	12		T33	1		T19	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T220	3		T137	10		T79	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T47	11		T16	2		T137	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T26	14		T182	9		T84	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T10	11		T130	20		T144	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T27	1		T170	7		T256	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T25	5		T257	14		T332	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T9	2		T221	15		T33	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T253	1		T239	21		T317	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T26	14		T139	1		T84	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T28	1		T130	19		T144	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T186	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T200	15		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T25	7		T221	18		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	1		T28	1		T227	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T9	4		T223	1		T228	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T137	1		T145	13		T232	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	1		T47	1		T227	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T221	3		T222	1		T142	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1614	1			T1	1		T3	35		T11	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T5	1		T9	1		T254	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T33	1		T141	1		T18	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T7	1		T9	5		T233	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T13	9		T48	13		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T47	10		T143	1		T36	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T26	11		T37	18		T220	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T10	1		T152	2		T153	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T153	15		T220	4		T137	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T37	20		T151	13		T33	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T5	1		T27	4		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T10	12		T25	6		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16890	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T26	14		T84	6		T314	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T130	20		T144	10		T155	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T186	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T25	3		T221	15		T151	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T227	8		T138	11		T170	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T9	2		T228	13		T87	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T137	1		T145	10		T232	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T227	12		T145	12		T203	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T222	10		T84	12		T149	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	939	1			T11	8		T25	8		T140	28
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T242	1		T22	16		T281	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T33	1		T18	2		T139	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T9	2		T233	13		T154	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T48	9		T182	7		T149	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T47	6		T143	1		T36	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T26	8		T220	3		T243	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T10	12		T19	12		T148	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T220	3		T137	10		T18	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T33	1		T16	2		T137	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T27	1		T182	9		T170	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T10	11		T25	5		T47	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T25	4		T165	1		T151	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	1		T227	9		T17	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T9	4		T47	1		T34	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T222	11		T137	2		T145	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T5	1		T227	14		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T221	1		T254	1		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1299	1			T1	1		T3	3		T11	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	1		T9	1		T265	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T33	2		T141	1		T222	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T7	1		T9	5		T233	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T13	1		T48	10		T182	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T47	7		T153	1		T223	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T26	9		T37	2		T220	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T10	13		T37	1		T33	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T153	1		T220	4		T137	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T47	12		T151	1		T16	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T5	1		T26	15		T28	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T10	12		T26	1		T130	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T27	4		T135	1		T170	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T25	6		T28	1		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17111	1			T2	10		T6	20		T8	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T28	1		T70	1		T340	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T25	6		T151	14		T183	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T17	2		T138	11		T216	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	2		T259	12		T97	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T145	12		T169	11		T259	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T227	14		T145	3		T179	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T221	2		T163	8		T142	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1314	1			T3	32		T12	18		T14	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T260	2		T22	17		T261	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T71	5		T225	2		T256	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T9	2		T136	15		T154	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	8		T48	12		T243	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T47	9		T153	14		T36	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T26	10		T37	16		T220	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T37	19		T142	14		T191	25
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T153	14		T220	3		T137	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T47	10		T151	12		T16	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T26	13		T221	6		T136	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T10	11		T130	18		T144	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T27	1		T135	13		T262	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T25	5		T183	12		T332	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T221	17		T143	13		T186	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T70	10		T200	14		T239	18

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T26	15		T139	1		T84	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T28	1		T130	21		T144	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T186	17		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T200	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T25	4		T221	16		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	1		T28	1		T227	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T9	4		T223	1		T228	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T137	2		T145	11		T232	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	1		T47	1		T227	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T221	1		T222	11		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1262	1			T1	1		T3	3		T11	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	1		T9	1		T254	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T33	2		T141	1		T18	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	1		T9	5		T233	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	1		T48	10		T182	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T47	7		T143	2		T36	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T26	9		T37	2		T220	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T10	13		T152	2		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T153	1		T220	4		T137	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T37	1		T151	1		T33	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T5	1		T27	4		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T10	12		T25	6		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17026	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T26	13		T84	11		T262	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T130	18		T144	11		T70	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T186	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T200	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T25	6		T221	17		T151	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T17	2		T138	11		T70	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T9	2		T183	6		T97	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T145	12		T169	11		T216	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T227	14		T145	3		T179	24
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T221	2		T142	14		T84	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1291	1			T3	32		T12	18		T14	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T163	8		T260	2		T22	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T18	1		T71	5		T139	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T9	2		T136	15		T154	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T13	8		T48	12		T240	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T47	9		T36	8		T225	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T26	10		T37	16		T220	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T153	14		T142	14		T191	25
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T153	14		T220	3		T137	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T37	19		T151	12		T16	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T27	1		T135	13		T221	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T10	11		T25	5		T47	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

4214

1

T3

32

T9

4

T10

11