Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26166

1

T1

1

T2

10

T3

35

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22728

1

T1

1

T2

10

T3

35

auto[ADC_CTRL_FILTER_COND_OUT]

3438

1

T5

1

T7

1

T9

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19972

1

T2

10

T5

2

T6

20

auto[1]

6194

1

T1

1

T3

35

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22173

1

T1

1

T2

10

T3

35

auto[1]

3993

1

T9

6

T10

23

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	249	1			T70	11		T216	21		T294	18
values[0]	72	1			T226	36		T313	1		T289	19
values[1]	675	1			T7	1		T10	36		T25	11
values[2]	717	1			T26	1		T28	2		T33	2
values[3]	639	1			T7	1		T9	1		T152	2
values[4]	606	1			T5	1		T34	3		T153	15
values[5]	2993	1			T1	1		T3	35		T11	9
values[6]	625	1			T5	1		T25	25		T26	28
values[7]	799	1			T221	40		T233	14		T16	7
values[8]	770	1			T9	6		T37	27		T144	22
values[9]	995	1			T5	1		T9	7		T135	14
minimum	17026	1			T2	10		T6	20		T8	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	721	1			T10	36		T27	5		T221	3
values[1]	659	1			T7	1		T25	11		T26	1
values[2]	597	1			T5	1		T9	1		T152	1
values[3]	2948	1			T1	1		T3	35		T11	9
values[4]	706	1			T25	25		T26	28		T254	1
values[5]	523	1			T5	1		T28	1		T37	11
values[6]	846	1			T221	40		T144	22		T233	14
values[7]	725	1			T9	6		T37	27		T163	9
values[8]	1001	1			T5	1		T9	7		T135	14
values[9]	118	1			T47	16		T165	1		T137	14
minimum	17322	1			T2	10		T6	20		T7	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

4214

1

T3

32

T9

4

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T10	13		T27	4		T221	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T227	1		T154	14		T138	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T141	1		T152	2		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	1		T25	6		T26	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T152	1		T222	1		T136	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	1		T9	1		T153	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1612	1			T1	1		T3	35		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T13	9		T25	7		T17	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T25	17		T146	1		T230	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T26	14		T254	1		T47	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T5	1		T37	11		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T28	1		T143	1		T137	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T221	7		T144	12		T233	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T221	18		T16	5		T142	30
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T9	4		T37	27		T68	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T163	9		T153	15		T220	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	1		T135	14		T151	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T9	5		T70	11		T139	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T47	10		T165	1		T137	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T261	1		T315	1		T316	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16938	1			T2	10		T6	20		T7	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T26	11		T227	13		T257	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T10	23		T27	1		T182	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T227	8		T154	15		T138	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T169	4		T236	10		T229	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T25	5		T33	1		T235	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T222	10		T138	1		T170	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T71	11		T182	7		T155	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	932	1			T11	8		T140	28		T166	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T25	3		T220	3		T143	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T25	8		T230	9		T234	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T26	14		T47	11		T222	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T130	20		T227	4		T18	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T143	1		T137	11		T148	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T144	10		T233	13		T139	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T221	15		T16	2		T169	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T9	2		T36	7		T231	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T220	3		T143	1		T170	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T48	9		T33	1		T145	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T9	2		T243	12		T216	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T47	6		T137	1		T156	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T315	2		T316	20		T317	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T9	2		T33	3		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T26	8		T227	8		T257	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T294	10		T160	12		T320	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T70	11		T216	10		T98	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T313	1		T289	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T226	20		T277	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	1		T10	13		T27	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T25	6		T26	11		T227	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T141	1		T152	1		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T26	1		T28	2		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T152	2		T222	1		T136	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	1		T9	1		T70	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T34	3		T207	5		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T5	1		T153	15		T17	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1640	1			T1	1		T3	35		T11	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T13	9		T25	7		T254	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T5	1		T25	17		T37	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T26	14		T28	1		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T221	7		T233	1		T18	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T221	18		T16	5		T142	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T9	4		T37	27		T144	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T142	15		T220	4		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T5	1		T135	14		T47	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T9	5		T163	9		T153	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16890	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T294	8		T160	14		T320	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T216	11		T98	2		T315	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T289	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T226	16		T277	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T10	23		T27	1		T95	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T25	5		T26	8		T227	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T182	9		T169	4		T77	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T33	1		T138	13		T235	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T222	10		T138	1		T229	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T71	11		T182	7		T155	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T170	7		T330	5		T268	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T220	3		T143	12		T18	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	975	1			T11	8		T140	28		T166	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T25	3		T47	11		T138	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T25	8		T130	20		T227	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T26	14		T222	2		T137	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T233	13		T18	2		T19	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T221	15		T16	2		T143	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T9	2		T144	10		T139	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T220	3		T143	1		T97	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T47	6		T48	9		T33	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T9	2		T243	12		T170	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T10	25		T27	4		T221	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T227	9		T154	16		T138	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T141	1		T152	2		T146	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	1		T25	6		T26	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T152	1		T222	11		T136	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	1		T9	1		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T1	1		T3	3		T11	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T13	1		T25	4		T17	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T25	9		T146	1		T230	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T26	15		T254	1		T47	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	1		T37	1		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T28	1		T143	2		T137	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T221	1		T144	11		T233	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T221	16		T16	6		T142	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T9	4		T37	2		T68	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T163	1		T153	1		T220	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T5	1		T135	1		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T9	5		T70	1		T139	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T47	7		T165	1		T137	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T261	1		T315	3		T316	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17079	1			T2	10		T6	20		T7	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T26	9		T227	9		T257	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T10	11		T27	1		T221	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T154	13		T138	13		T271	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T169	14		T229	11		T266	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T25	5		T235	19		T244	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T136	15		T70	19		T191	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T153	14		T70	16		T71	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T3	32		T12	18		T14	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	8		T25	6		T17	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T25	16		T230	10		T247	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T26	13		T47	10		T138	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T37	10		T130	18		T227	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T137	9		T240	9		T260	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T221	6		T144	11		T139	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T221	17		T16	1		T142	28
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T9	2		T37	25		T36	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T163	8		T153	14		T220	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T135	13		T151	12		T48	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T9	2		T70	10		T243	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T47	9		T137	12		T89	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T316	15		T317	6		T322	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T341	11		T342	6		T343	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T26	10		T227	12		T226	19

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T294	9		T160	15		T320	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T70	1		T216	12		T98	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T313	1		T289	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T226	17		T277	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T7	1		T10	25		T27	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T25	6		T26	9		T227	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T141	1		T152	1		T182	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T26	1		T28	2		T33	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T152	2		T222	11		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	1		T9	1		T70	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T34	3		T207	1		T170	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T5	1		T153	1		T17	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T1	1		T3	3		T11	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T13	1		T25	4		T254	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	1		T25	9		T37	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T26	15		T28	1		T222	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T221	1		T233	14		T18	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T221	16		T16	6		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T9	4		T37	2		T144	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T142	1		T220	4		T143	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T5	1		T135	1		T47	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T9	5		T163	1		T153	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17026	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T294	9		T160	11		T321	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T70	10		T216	9		T174	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T289	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T226	19		T277	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T10	11		T27	1		T221	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T25	5		T26	10		T227	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T191	16		T169	14		T77	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T138	13		T235	19		T276	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T136	15		T70	19		T191	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T70	16		T179	12		T155	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T207	4		T247	18		T246	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T153	14		T17	2		T220	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1314	1			T3	32		T12	18		T14	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T13	8		T25	6		T47	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T25	16		T37	10		T130	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T26	13		T137	9		T257	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T221	6		T18	1		T19	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T221	17		T16	1		T142	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T9	2		T37	25		T144	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T142	14		T220	3		T240	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T135	13		T47	9		T151	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T9	2		T163	8		T153	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

4214

1

T3

32

T9

4

T10

11