Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26166

1

T1

1

T2

10

T3

35

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20604

1

T2

10

T5

1

T6

20

auto[ADC_CTRL_FILTER_COND_OUT]

5562

1

T1

1

T3

35

T5

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20114

1

T2

10

T6

20

T7

1

auto[1]

6052

1

T1

1

T3

35

T5

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22173

1

T1

1

T2

10

T3

35

auto[1]

3993

1

T9

6

T10

23

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	275	1			T28	1		T47	22		T227	16
values[0]	51	1			T10	13		T169	21		T344	1
values[1]	647	1			T26	19		T34	3		T153	15
values[2]	594	1			T9	1		T25	11		T141	1
values[3]	732	1			T7	1		T26	28		T221	3
values[4]	777	1			T5	1		T9	7		T33	3
values[5]	713	1			T13	9		T27	5		T135	14
values[6]	850	1			T9	6		T10	23		T26	1
values[7]	556	1			T5	2		T28	2		T151	13
values[8]	850	1			T25	35		T37	18		T47	1
values[9]	3095	1			T1	1		T3	35		T7	1
minimum	17026	1			T2	10		T6	20		T8	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	659	1			T26	19		T141	1		T34	3
values[1]	2841	1			T1	1		T3	35		T7	1
values[2]	837	1			T9	7		T26	28		T221	3
values[3]	760	1			T5	1		T33	3		T152	1
values[4]	736	1			T9	6		T13	9		T27	5
values[5]	686	1			T26	1		T221	33		T151	38
values[6]	752	1			T5	2		T10	23		T28	2
values[7]	666	1			T25	35		T37	18		T130	39
values[8]	852	1			T7	1		T28	1		T37	20
values[9]	167	1			T47	22		T224	18		T42	2
minimum	17210	1			T2	10		T6	20		T8	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

4214

1

T3

32

T9

4

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T141	1		T34	3		T18	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T26	11		T153	15		T73	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	1		T25	6		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1592	1			T1	1		T3	35		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T9	5		T221	3		T137	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T26	14		T163	9		T144	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T33	2		T17	4		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T5	1		T152	1		T233	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	9		T47	10		T18	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T9	4		T27	4		T135	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T151	15		T152	1		T138	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T26	1		T221	18		T151	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	1		T10	12		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T5	1		T28	2		T16	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T25	24		T37	7		T130	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T37	11		T136	16		T223	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T254	1		T33	1		T227	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T7	1		T28	1		T37	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T224	18		T31	1		T32	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T47	11		T42	2		T260	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16905	1			T2	10		T6	20		T8	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T139	7		T146	1		T230	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T18	9		T145	22		T148	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T26	8		T73	8		T236	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T25	5		T154	15		T139	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	950	1			T11	8		T140	28		T166	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T9	2		T137	1		T149	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T26	14		T144	10		T36	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T33	1		T244	7		T87	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T233	13		T182	15		T228	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T47	6		T18	2		T79	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T9	2		T27	1		T220	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T151	10		T138	13		T19	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T221	15		T222	10		T220	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T10	11		T48	9		T71	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T16	2		T182	7		T232	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T25	11		T130	20		T227	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T143	1		T137	1		T268	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T33	1		T227	12		T143	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T155	9		T234	2		T276	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T32	12		T295	2		T315	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T47	11		T193	8		T272	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T9	2		T10	12		T33	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T139	9		T230	9		T169	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T227	4		T224	18		T138	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T28	1		T47	11		T234	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T10	1		T277	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T169	12		T344	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T34	3		T145	13		T179	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T26	11		T153	15		T73	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T25	6		T141	1		T154	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T9	1		T222	1		T236	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T7	1		T221	3		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T26	14		T163	9		T144	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T9	5		T33	2		T345	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	1		T152	1		T142	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T13	9		T17	4		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T27	4		T135	14		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T10	12		T47	10		T151	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T9	4		T26	1		T221	25
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	1		T152	1		T223	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	1		T28	2		T151	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T25	24		T37	7		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T37	11		T16	5		T136	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T254	1		T130	19		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1655	1			T1	1		T3	35		T7	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16890	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T227	12		T138	11		T148	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T47	11		T234	2		T270	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T10	12		T277	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T169	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T145	10		T148	11		T216	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T26	8		T73	8		T139	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T25	5		T154	15		T18	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T222	2		T236	10		T156	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T137	1		T226	16		T242	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T26	14		T144	10		T36	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	2		T33	1		T244	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T182	15		T228	13		T149	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T79	15		T271	1		T21	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T27	1		T233	13		T220	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T10	11		T47	6		T151	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T9	2		T221	15		T222	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T84	12		T257	14		T87	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T220	3		T182	7		T83	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T25	11		T48	9		T227	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T16	2		T143	1		T137	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T130	20		T33	1		T143	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	963	1			T11	8		T140	28		T166	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T141	1		T34	3		T18	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T26	9		T153	1		T73	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	1		T25	6		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1274	1			T1	1		T3	3		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T9	5		T221	1		T137	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T26	15		T163	1		T144	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T33	3		T17	2		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T5	1		T152	1		T233	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	1		T47	7		T18	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T9	4		T27	4		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T151	11		T152	1		T138	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T26	1		T221	16		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	1		T10	12		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T5	1		T28	2		T16	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T25	13		T37	1		T130	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T37	1		T136	1		T223	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T254	1		T33	2		T227	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	1		T28	1		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T224	1		T31	1		T32	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T47	12		T42	2		T260	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17052	1			T2	10		T6	20		T8	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T139	10		T146	1		T230	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T18	2		T145	15		T179	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T26	10		T153	14		T94	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T25	5		T154	13		T139	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1268	1			T3	32		T12	18		T14	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T9	2		T221	2		T137	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T26	13		T163	8		T144	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T17	2		T244	5		T157	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T142	14		T191	16		T169	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	8		T47	9		T18	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T9	2		T27	1		T135	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T151	14		T138	13		T19	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T221	17		T151	12		T153	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T10	11		T48	12		T136	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T16	1		T84	11		T203	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T25	22		T37	6		T130	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T37	10		T136	15		T70	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T227	2		T143	13		T138	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T37	19		T155	12		T275	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T224	17		T32	13		T199	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T47	10		T193	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T183	6		T277	5		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T139	6		T230	10		T169	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T227	14		T224	1		T138	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T28	1		T47	12		T234	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T10	13		T277	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T169	10		T344	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T34	3		T145	11		T179	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T26	9		T153	1		T73	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T25	6		T141	1		T154	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T9	1		T222	3		T236	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	1		T221	1		T165	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T26	15		T163	1		T144	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T9	5		T33	3		T345	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T5	1		T152	1		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	1		T17	2		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T27	4		T135	1		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T10	12		T47	7		T151	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T9	4		T26	1		T221	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T5	1		T152	1		T223	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T5	1		T28	2		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T25	13		T37	1		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T37	1		T16	6		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T254	1		T130	21		T33	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1291	1			T1	1		T3	3		T7	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17026	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T227	2		T224	17		T138	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T47	10		T332	7		T291	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T277	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T169	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T145	12		T179	12		T216	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T26	10		T153	14		T139	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T25	5		T154	13		T18	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T259	16		T257	11		T246	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T221	2		T137	12		T70	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T26	13		T163	8		T144	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T9	2		T244	5		T149	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T142	14		T191	16		T149	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	8		T17	2		T271	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T27	1		T135	13		T220	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T10	11		T47	9		T151	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T9	2		T221	23		T153	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T84	15		T172	36		T161	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T151	12		T220	3		T84	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T25	22		T37	6		T48	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T37	10		T16	1		T136	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T130	18		T143	13		T243	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1327	1			T3	32		T12	18		T14	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

4214

1

T3

32

T9

4

T10

11