Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T25	4		T221	16		T165	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T7	1		T227	9		T138	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T9	4		T47	1		T34	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T222	11		T17	2		T137	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	1		T227	14		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T221	1		T163	1		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T1	1		T3	3		T11	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T5	1		T9	1		T254	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T33	2		T141	1		T222	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T7	1		T9	5		T233	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	1		T48	10		T243	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T47	7		T153	1		T223	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T26	9		T37	2		T220	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T10	13		T33	3		T152	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T153	1		T220	4		T137	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T37	1		T47	12		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T5	1		T26	15		T27	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T10	12		T26	1		T130	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T28	1		T135	1		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T25	6		T28	1		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17026	1			T2	10		T6	20		T8	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T28	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T25	6		T221	17		T151	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T138	11		T70	10		T216	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T9	2		T259	12		T97	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T17	2		T145	12		T169	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T227	14		T145	3		T179	24
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T221	2		T163	8		T142	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T3	32		T12	18		T14	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T260	2		T22	17		T261	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T71	5		T225	2		T256	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T9	2		T136	15		T154	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T13	8		T48	12		T243	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T47	9		T153	14		T36	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T26	10		T37	16		T220	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T142	14		T191	25		T19	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T153	14		T220	3		T137	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T37	19		T47	10		T151	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T26	13		T27	1		T221	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T10	11		T130	18		T144	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T135	13		T136	1		T262	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T25	5		T183	12		T193	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T251	11		T252	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T196	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T253	5		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T25	4		T221	16		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	1		T28	1		T227	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T9	4		T223	1		T179	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T137	2		T145	11		T232	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	1		T47	1		T227	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T221	1		T222	11		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1278	1			T1	1		T3	3		T11	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T5	1		T254	1		T163	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T141	1		T18	3		T71	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	1		T9	6		T233	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T13	1		T48	10		T33	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T47	7		T136	1		T143	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T37	2		T220	4		T42	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T152	2		T153	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T26	9		T153	1		T220	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T10	13		T37	1		T33	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T5	1		T26	15		T27	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	429	1			T10	12		T25	6		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17026	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T252	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T25	6		T221	17		T151	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T17	2		T138	11		T70	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T9	2		T179	12		T203	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T145	12		T169	11		T216	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T227	14		T145	3		T179	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T221	2		T142	14		T84	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1296	1			T3	32		T12	18		T14	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T163	8		T260	2		T22	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T18	1		T71	5		T230	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T9	2		T154	13		T263	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T13	8		T48	12		T240	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T47	9		T136	15		T225	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T37	16		T220	20		T243	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T153	14		T142	14		T36	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T26	10		T153	14		T220	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T37	19		T16	1		T137	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T26	13		T27	1		T135	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T10	11		T25	5		T47	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

4214

1

T3

32

T9

4

T10

11