Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26166

1

T1

1

T2

10

T3

35

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22499

1

T1

1

T2

10

T3

35

auto[ADC_CTRL_FILTER_COND_OUT]

3667

1

T5

3

T7

1

T9

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20316

1

T2

10

T5

1

T6

20

auto[1]

5850

1

T1

1

T3

35

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22173

1

T1

1

T2

10

T3

35

auto[1]

3993

1

T9

6

T10

23

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	54	1			T135	14		T142	15		T136	2
values[0]	26	1			T264	11		T105	15		-	-
values[1]	597	1			T47	1		T152	1		T233	14
values[2]	3079	1			T1	1		T3	35		T11	9
values[3]	721	1			T5	1		T28	1		T221	7
values[4]	711	1			T9	7		T37	11		T151	38
values[5]	794	1			T25	10		T221	33		T254	1
values[6]	687	1			T5	1		T9	1		T10	13
values[7]	740	1			T221	3		T47	22		T227	9
values[8]	654	1			T5	1		T10	23		T25	11
values[9]	1077	1			T7	2		T9	6		T26	29
minimum	17026	1			T2	10		T6	20		T8	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	962	1			T25	25		T27	5		T28	1
values[1]	2940	1			T1	1		T3	35		T11	9
values[2]	619	1			T5	1		T9	7		T28	1
values[3]	894	1			T25	10		T37	11		T151	38
values[4]	536	1			T221	33		T17	4		T223	1
values[5]	737	1			T5	1		T9	1		T10	13
values[6]	830	1			T5	1		T25	11		T221	3
values[7]	556	1			T9	6		T10	23		T227	30
values[8]	853	1			T7	2		T26	28		T28	1
values[9]	182	1			T26	1		T142	15		T138	23
minimum	17057	1			T2	10		T6	20		T8	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

4214

1

T3

32

T9

4

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T28	1		T47	1		T227	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T25	17		T27	4		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1633	1			T1	1		T3	35		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T221	7		T139	10		T148	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T28	1		T16	5		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	1		T9	5		T153	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T25	7		T37	11		T130	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T151	28		T222	1		T137	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T265	1		T266	24		T267	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T221	18		T17	4		T223	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T47	10		T71	6		T179	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	1		T9	1		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T25	6		T221	3		T34	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T5	1		T47	11		T18	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	4		T227	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T10	12		T227	13		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T7	1		T26	14		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T7	1		T28	1		T37	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T26	1		T138	12		T231	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T142	15		T268	1		T269	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16911	1			T2	10		T6	20		T8	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T227	4		T220	3		T154	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T25	8		T27	1		T233	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	973	1			T11	8		T140	28		T166	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T139	9		T148	11		T228	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T16	2		T170	6		T229	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T9	2		T36	7		T243	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T25	3		T130	20		T144	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T151	10		T222	2		T137	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T266	22		T242	1		T270	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T221	15		T143	1		T84	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T47	6		T235	13		T259	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T10	12		T26	8		T33	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T25	5		T143	1		T138	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T47	11		T18	2		T182	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T9	2		T227	8		T220	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T10	11		T227	8		T271	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T26	14		T232	1		T169	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T48	9		T33	1		T137	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T138	11		T231	5		T196	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T268	6		T196	11		T24	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T9	2		T33	3		T34	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T135	14		T142	15		T136	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T264	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T105	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T47	1		T152	1		T154	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T233	1		T138	14		T139	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1671	1			T1	1		T3	35		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T25	17		T27	4		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T28	1		T16	5		T224	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T5	1		T221	7		T153	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T37	11		T144	12		T143	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	5		T151	28		T222	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T25	7		T130	19		T265	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T221	18		T254	1		T17	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T47	10		T138	1		T71	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T5	1		T9	1		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T221	3		T227	1		T220	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T47	11		T18	2		T182	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T25	6		T34	3		T142	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	1		T10	12		T48	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T7	1		T9	4		T26	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T7	1		T28	1		T37	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16890	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T272	10		T24	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T264	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T105	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T154	15		T19	12		T170	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T233	13		T138	13		T139	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1014	1			T11	8		T140	28		T166	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T25	8		T27	1		T137	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T16	2		T145	12		T203	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T139	9		T36	7		T243	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T144	10		T143	12		T79	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T9	2		T151	10		T222	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T25	3		T130	20		T266	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T221	15		T143	1		T73	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T47	6		T138	1		T235	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T10	12		T26	8		T33	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T227	8		T220	3		T230	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T47	11		T18	2		T182	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T25	5		T143	1		T225	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T10	11		T48	9		T227	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T9	2		T26	14		T138	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T33	1		T71	11		T84	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T28	1		T47	1		T227	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T25	9		T27	4		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1298	1			T1	1		T3	3		T11	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T221	1		T139	10		T148	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T28	1		T16	6		T146	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	1		T9	5		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T25	4		T37	1		T130	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T151	12		T222	3		T137	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T265	1		T266	23		T267	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T221	16		T17	2		T223	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T47	7		T71	1		T179	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	1		T9	1		T10	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T25	6		T221	1		T34	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T5	1		T47	12		T18	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T9	4		T227	9		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T10	12		T227	9		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T7	1		T26	15		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T7	1		T28	1		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T26	1		T138	12		T231	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T142	1		T268	7		T269	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17038	1			T2	10		T6	20		T8	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T227	2		T220	3		T154	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T25	16		T27	1		T153	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1308	1			T3	32		T12	18		T13	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T221	6		T139	9		T77	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T16	1		T263	17		T229	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T9	2		T153	14		T36	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T25	6		T37	10		T130	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T151	26		T137	12		T70	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T266	23		T270	3		T88	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T221	17		T17	2		T191	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T47	9		T71	5		T179	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T26	10		T241	4		T240	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T25	5		T221	2		T136	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T47	10		T18	1		T169	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T9	2		T142	14		T220	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T10	11		T227	12		T271	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T26	13		T70	10		T169	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T37	6		T135	13		T163	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T138	11		T273	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T142	14		T24	3		T274	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T70	19		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T135	1		T142	1		T136	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T264	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T105	5		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T47	1		T152	1		T154	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T233	14		T138	14		T139	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1342	1			T1	1		T3	3		T11	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T25	9		T27	4		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T28	1		T16	6		T224	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T5	1		T221	1		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T37	1		T144	11		T143	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T9	5		T151	12		T222	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T25	4		T130	21		T265	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T221	16		T254	1		T17	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T47	7		T138	2		T71	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	1		T9	1		T10	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T221	1		T227	9		T220	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T47	12		T18	3		T182	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T25	6		T34	3		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T5	1		T10	12		T48	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T7	1		T9	4		T26	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	359	1			T7	1		T28	1		T37	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17026	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T135	13		T142	14		T136	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T264	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T105	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T154	13		T70	19		T19	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T138	13		T139	6		T172	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1343	1			T3	32		T12	18		T13	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T25	16		T27	1		T153	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T16	1		T224	17		T145	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T221	6		T153	14		T139	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T37	10		T144	11		T143	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T9	2		T151	26		T137	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T25	6		T130	18		T275	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T221	17		T17	2		T145	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T47	9		T71	5		T203	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T26	10		T84	11		T183	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T221	2		T220	20		T179	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T47	10		T18	1		T241	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T25	5		T142	14		T136	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	11		T48	12		T227	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T9	2		T26	13		T138	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T37	6		T163	8		T179	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

4214

1

T3

32

T9

4

T10

11