Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26166

1

T1

1

T2

10

T3

35

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20609

1

T2

10

T5

1

T6

20

auto[ADC_CTRL_FILTER_COND_OUT]

5557

1

T1

1

T3

35

T5

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20171

1

T2

10

T5

1

T6

20

auto[1]

5995

1

T1

1

T3

35

T5

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22173

1

T1

1

T2

10

T3

35

auto[1]

3993

1

T9

6

T10

23

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	14	1			T189	14		-	-		-	-
values[0]	63	1			T26	19		T146	1		T169	21
values[1]	647	1			T10	13		T34	3		T153	15
values[2]	621	1			T9	1		T25	11		T165	1
values[3]	719	1			T7	1		T26	28		T221	3
values[4]	762	1			T5	1		T9	7		T135	14
values[5]	733	1			T13	9		T27	5		T221	33
values[6]	810	1			T9	6		T26	1		T28	1
values[7]	580	1			T5	2		T10	23		T28	1
values[8]	887	1			T25	35		T37	18		T47	1
values[9]	3304	1			T1	1		T3	35		T7	1
minimum	17026	1			T2	10		T6	20		T8	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	808	1			T10	13		T26	19		T141	1
values[1]	2901	1			T1	1		T3	35		T7	1
values[2]	736	1			T9	7		T26	28		T221	3
values[3]	879	1			T5	1		T33	3		T152	1
values[4]	688	1			T13	9		T27	5		T135	14
values[5]	738	1			T9	6		T10	23		T26	1
values[6]	688	1			T5	2		T28	2		T48	22
values[7]	697	1			T25	35		T37	18		T47	1
values[8]	785	1			T7	1		T28	1		T37	20
values[9]	207	1			T47	22		T227	9		T224	18
minimum	17039	1			T2	10		T6	20		T8	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

4214

1

T3

32

T9

4

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T10	1		T141	1		T34	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T26	11		T153	15		T73	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T7	1		T25	6		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1608	1			T1	1		T3	35		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T9	5		T221	3		T137	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T26	14		T163	9		T144	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T33	2		T17	4		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T5	1		T152	1		T233	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	9		T47	10		T271	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T27	4		T135	14		T221	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T10	12		T151	15		T138	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T9	4		T26	1		T221	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	1		T48	13		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T5	1		T28	2		T16	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T25	24		T37	7		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T37	11		T136	16		T223	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T254	1		T33	1		T227	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T7	1		T28	1		T37	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T227	1		T224	18		T148	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T47	11		T260	1		T193	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16890	1			T2	10		T6	20		T8	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T183	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T10	12		T18	9		T145	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T26	8		T73	8		T139	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T25	5		T154	15		T139	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	968	1			T11	8		T140	28		T166	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T9	2		T137	1		T242	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T26	14		T144	10		T36	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T33	1		T79	15		T244	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T233	13		T182	15		T228	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T47	6		T271	1		T160	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T27	1		T220	3		T137	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T10	11		T151	10		T138	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T9	2		T221	15		T222	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T48	9		T77	6		T20	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T16	2		T220	3		T71	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T25	11		T130	20		T227	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T143	1		T137	1		T268	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T33	1		T227	4		T143	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T155	9		T234	2		T276	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T227	8		T148	4		T32	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T47	11		T193	8		T270	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	2		T33	3		T34	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T189	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T277	6		T278	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T26	11		T146	1		T169	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T10	1		T34	3		T145	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T153	15		T73	1		T139	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T25	6		T165	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T9	1		T236	1		T279	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T7	1		T221	3		T137	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T26	14		T163	9		T144	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T9	5		T33	2		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	1		T135	14		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T13	9		T17	4		T228	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T27	4		T221	18		T233	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T47	10		T151	15		T138	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T9	4		T26	1		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	1		T10	12		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	1		T28	1		T151	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T25	24		T37	7		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T37	11		T16	5		T136	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T254	1		T130	19		T33	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1715	1			T1	1		T3	35		T7	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16890	1			T2	10		T6	20		T8	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T277	10		T278	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T26	8		T169	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T10	12		T145	10		T148	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T73	8		T139	9		T230	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T25	5		T154	15		T18	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T236	10		T156	2		T259	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T137	1		T149	10		T226	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T26	14		T144	10		T222	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	2		T33	1		T244	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T182	15		T149	9		T280	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T228	9		T79	15		T235	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T27	1		T221	15		T233	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T47	6		T151	10		T138	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T9	2		T222	10		T229	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T10	11		T84	12		T257	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T220	3		T182	7		T83	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T25	11		T48	9		T227	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T16	2		T143	1		T137	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T130	20		T33	1		T227	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1030	1			T11	8		T140	28		T47	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T10	13		T141	1		T34	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T26	9		T153	1		T73	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	1		T25	6		T165	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1295	1			T1	1		T3	3		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T9	5		T221	1		T137	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T26	15		T163	1		T144	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T33	3		T17	2		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T5	1		T152	1		T233	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	1		T47	7		T271	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T27	4		T135	1		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T10	12		T151	11		T138	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T9	4		T26	1		T221	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	1		T48	10		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T5	1		T28	2		T16	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T25	13		T37	1		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T37	1		T136	1		T223	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T254	1		T33	2		T227	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	1		T28	1		T37	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T227	9		T224	1		T148	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T47	12		T260	1		T193	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17026	1			T2	10		T6	20		T8	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T183	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T18	2		T145	15		T179	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T26	10		T153	14		T139	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T25	5		T154	13		T70	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1281	1			T3	32		T12	18		T14	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T9	2		T221	2		T137	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T26	13		T163	8		T144	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T17	2		T244	5		T149	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T142	14		T191	16		T169	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T13	8		T47	9		T271	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T27	1		T135	13		T221	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T10	11		T151	14		T138	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T9	2		T221	17		T151	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T48	12		T207	4		T77	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T16	1		T136	1		T220	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T25	22		T37	6		T130	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T37	10		T136	15		T264	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T227	2		T143	13		T138	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T37	19		T70	19		T155	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T224	17		T32	13		T281	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T47	10		T193	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T183	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T189	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T277	11		T278	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T26	9		T146	1		T169	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T10	13		T34	3		T145	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T153	1		T73	9		T139	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T25	6		T165	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T9	1		T236	11		T279	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T7	1		T221	1		T137	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T26	15		T163	1		T144	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T9	5		T33	3		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T5	1		T135	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T13	1		T17	2		T228	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T27	4		T221	16		T233	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T47	7		T151	11		T138	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T9	4		T26	1		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T5	1		T10	12		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T5	1		T28	1		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T25	13		T37	1		T47	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T37	1		T16	6		T136	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T254	1		T130	21		T33	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1370	1			T1	1		T3	3		T7	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17026	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T189	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T277	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T26	10		T169	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T145	12		T179	12		T216	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T153	14		T139	6		T230	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T25	5		T154	13		T18	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T259	16		T257	11		T246	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T221	2		T137	12		T70	26
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T26	13		T163	8		T144	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T9	2		T244	5		T219	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T135	13		T142	14		T191	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	8		T17	2		T235	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T27	1		T221	17		T220	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T47	9		T151	14		T138	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	2		T221	6		T153	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T10	11		T84	15		T172	36
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T151	12		T136	15		T220	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T25	22		T37	6		T48	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T37	10		T16	1		T136	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T130	18		T227	2		T143	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1375	1			T3	32		T12	18		T14	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

4214

1

T3

32

T9

4

T10

11