Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26166

1

T1

1

T2

10

T3

35

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22493

1

T1

1

T2

10

T3

35

auto[ADC_CTRL_FILTER_COND_OUT]

3673

1

T5

1

T7

1

T9

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19947

1

T2

10

T5

3

T6

20

auto[1]

6219

1

T1

1

T3

35

T7

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22173

1

T1

1

T2

10

T3

35

auto[1]

3993

1

T9

6

T10

23

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	287	1			T7	1		T138	27		T146	1
values[0]	1	1			T282	1		-	-		-	-
values[1]	799	1			T5	1		T221	7		T47	1
values[2]	807	1			T9	6		T25	10		T26	28
values[3]	786	1			T37	18		T221	36		T151	13
values[4]	844	1			T5	1		T7	1		T10	23
values[5]	521	1			T254	1		T130	39		T142	15
values[6]	661	1			T25	11		T27	5		T47	16
values[7]	618	1			T13	9		T47	22		T165	1
values[8]	648	1			T5	1		T9	8		T10	13
values[9]	3168	1			T1	1		T3	35		T11	9
minimum	17026	1			T2	10		T6	20		T8	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	848	1			T5	1		T26	28		T221	7
values[1]	738	1			T9	6		T25	10		T37	7
values[2]	868	1			T37	11		T221	36		T152	1
values[3]	732	1			T5	1		T7	1		T10	23
values[4]	576	1			T151	25		T130	39		T142	15
values[5]	583	1			T25	11		T27	5		T47	16
values[6]	2839	1			T1	1		T3	35		T9	1
values[7]	686	1			T5	1		T9	7		T10	13
values[8]	902	1			T7	1		T28	1		T152	1
values[9]	162	1			T222	3		T169	19		T271	6
minimum	17232	1			T2	10		T6	20		T8	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

4214

1

T3

32

T9

4

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T5	1		T221	7		T47	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T26	14		T227	13		T223	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T141	1		T223	1		T137	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T9	4		T25	7		T37	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T37	11		T221	3		T17	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T221	18		T152	1		T233	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T25	17		T28	1		T37	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	1		T7	1		T10	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T151	15		T142	15		T207	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T130	19		T220	4		T224	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T47	10		T152	1		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T25	6		T27	4		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1594	1			T1	1		T3	35		T9	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T13	9		T28	1		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	1		T10	1		T163	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T9	5		T26	11		T144	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T7	1		T28	1		T154	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T152	1		T138	14		T71	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T271	5		T256	13		T160	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T222	1		T169	15		T283	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16954	1			T2	10		T6	20		T8	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T70	17		T256	13		T159	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T77	6		T79	9		T226	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T26	14		T227	8		T145	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T137	10		T182	7		T231	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T9	2		T25	3		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T230	9		T232	1		T244	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T221	15		T233	13		T143	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T25	8		T48	9		T170	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T10	11		T227	4		T220	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T151	10		T203	4		T226	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T130	20		T220	3		T148	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T47	6		T138	1		T83	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T25	5		T27	1		T33	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	960	1			T11	8		T140	28		T47	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T222	10		T145	12		T79	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T10	12		T16	2		T173	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T9	2		T26	8		T144	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T154	15		T18	9		T228	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T138	13		T71	11		T36	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T271	1		T256	9		T160	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T222	2		T169	4		T284	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T9	2		T33	3		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T256	9		T285	2		T286	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T7	1		T146	1		T191	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T138	14		T169	15		T170	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T282	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T5	1		T221	7		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T227	13		T70	17		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T141	1		T153	15		T137	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T9	4		T25	7		T26	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T37	11		T221	3		T17	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T37	7		T221	18		T151	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T25	17		T28	1		T37	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T5	1		T7	1		T10	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T254	1		T142	15		T203	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T130	19		T224	18		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T47	10		T151	15		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T25	6		T27	4		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T47	11		T165	1		T137	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T13	9		T70	11		T145	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	1		T9	1		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	5		T26	11		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1683	1			T1	1		T3	35		T11	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T152	1		T222	1		T143	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16890	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T271	1		T287	2		T160	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T138	13		T169	4		T170	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T77	6		T79	9		T226	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T227	8		T182	9		T216	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T137	10		T231	5		T242	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	2		T25	3		T26	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T182	7		T230	9		T232	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T221	15		T227	8		T148	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T25	8		T48	9		T244	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T10	11		T227	4		T233	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T203	4		T170	11		T225	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T130	20		T148	4		T156	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T47	6		T151	10		T138	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T25	5		T27	1		T33	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T47	11		T137	1		T18	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T145	12		T79	15		T170	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T10	12		T16	2		T84	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T9	2		T26	8		T144	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1045	1			T11	8		T140	28		T166	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T222	2		T143	12		T71	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	1		T221	1		T47	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T26	15		T227	9		T223	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T141	1		T223	1		T137	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T9	4		T25	4		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T37	1		T221	1		T17	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T221	16		T152	1		T233	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T25	9		T28	1		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	1		T7	1		T10	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T151	11		T142	1		T207	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T130	21		T220	4		T224	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T47	7		T152	1		T138	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T25	6		T27	4		T33	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T1	1		T3	3		T9	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T13	1		T28	1		T222	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	1		T10	13		T163	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T9	5		T26	9		T144	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T7	1		T28	1		T154	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T152	1		T138	14		T71	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T271	5		T256	10		T160	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T222	3		T169	5		T283	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17091	1			T2	10		T6	20		T8	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T70	1		T256	10		T159	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T221	6		T153	28		T77	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T26	13		T227	12		T145	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T137	9		T203	3		T247	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T9	2		T25	6		T37	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T37	10		T221	2		T17	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T221	17		T155	12		T235	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T25	16		T37	19		T135	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T10	11		T227	2		T220	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T151	14		T142	14		T207	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T130	18		T220	3		T224	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T47	9		T191	16		T225	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T25	5		T27	1		T179	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T3	32		T12	18		T14	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T13	8		T70	10		T71	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T163	8		T16	1		T142	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T9	2		T26	10		T144	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T154	13		T18	2		T191	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T138	13		T179	12		T36	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T271	1		T256	12		T160	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T169	14		T283	10		T288	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T263	16		T219	7		T252	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T70	16		T256	12		T159	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T7	1		T146	1		T191	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T138	14		T169	5		T170	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T282	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T5	1		T221	1		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T227	9		T70	1		T182	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T141	1		T153	1		T137	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T9	4		T25	4		T26	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T37	1		T221	1		T17	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T37	1		T221	16		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T25	9		T28	1		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	1		T7	1		T10	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T254	1		T142	1		T203	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T130	21		T224	1		T148	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T47	7		T151	11		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T25	6		T27	4		T33	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T47	12		T165	1		T137	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	1		T70	1		T145	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	1		T9	1		T10	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T9	5		T26	9		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1397	1			T1	1		T3	3		T11	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T152	1		T222	3		T143	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17026	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T191	9		T271	1		T160	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T138	13		T169	14		T281	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T221	6		T153	14		T77	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T227	12		T70	16		T216	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T153	14		T137	9		T203	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T9	2		T25	6		T26	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T37	10		T221	2		T17	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T37	6		T221	17		T151	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T25	16		T37	19		T135	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T10	11		T227	2		T220	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T142	14		T203	2		T225	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T130	18		T224	17		T259	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T47	9		T151	14		T191	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T25	5		T27	1		T220	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T47	10		T137	12		T18	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T13	8		T70	10		T145	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T163	8		T16	1		T142	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T9	2		T26	10		T144	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T3	32		T12	18		T14	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T143	13		T179	12		T36	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

4214

1

T3

32

T9

4

T10

11