Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26166

1

T1

1

T2

10

T3

35

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22653

1

T1

1

T2

10

T3

35

auto[ADC_CTRL_FILTER_COND_OUT]

3513

1

T5

2

T7

1

T9

6

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20341

1

T2

10

T5

2

T6

20

auto[1]

5825

1

T1

1

T3

35

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22173

1

T1

1

T2

10

T3

35

auto[1]

3993

1

T9

6

T10

23

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	225	1			T26	1		T221	7		T47	22
values[0]	7	1			T170	7		-	-		-	-
values[1]	712	1			T7	1		T13	9		T28	1
values[2]	860	1			T9	6		T10	13		T25	25
values[3]	710	1			T5	1		T221	3		T33	2
values[4]	589	1			T5	2		T25	11		T27	5
values[5]	2926	1			T1	1		T3	35		T11	9
values[6]	748	1			T26	19		T37	20		T163	9
values[7]	752	1			T10	23		T254	1		T47	1
values[8]	627	1			T9	7		T220	7		T223	1
values[9]	984	1			T7	1		T9	1		T25	10
minimum	17026	1			T2	10		T6	20		T8	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	672	1			T7	1		T13	9		T28	2
values[1]	763	1			T9	6		T10	13		T25	25
values[2]	756	1			T5	1		T27	5		T221	3
values[3]	2875	1			T1	1		T3	35		T5	2
values[4]	589	1			T28	1		T227	7		T143	26
values[5]	790	1			T26	19		T37	20		T163	9
values[6]	801	1			T10	23		T254	1		T47	1
values[7]	599	1			T9	7		T25	10		T165	1
values[8]	787	1			T7	1		T9	1		T26	29
values[9]	223	1			T221	7		T47	22		T222	3
minimum	17311	1			T2	10		T6	20		T8	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

4214

1

T3

32

T9

4

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T7	1		T13	9		T28	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T28	1		T182	1		T79	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T10	1		T25	17		T48	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T9	4		T135	14		T70	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T5	1		T221	3		T33	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T27	4		T141	1		T222	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1617	1			T1	1		T3	35		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	2		T37	18		T221	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T28	1		T227	3		T36	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T143	14		T71	6		T230	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T26	11		T37	20		T142	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T163	9		T130	19		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T254	1		T220	4		T137	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T10	12		T47	1		T68	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T9	5		T70	17		T73	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T25	7		T165	1		T223	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T9	1		T26	14		T227	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T7	1		T26	1		T47	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T221	7		T47	11		T222	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T139	1		T170	1		T266	24
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16942	1			T2	10		T6	20		T8	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T151	15		T145	13		T235	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T143	1		T138	1		T71	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T182	15		T79	15		T170	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T10	12		T25	8		T48	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T9	2		T139	9		T42	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T33	1		T16	2		T77	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T27	1		T222	10		T233	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	937	1			T11	8		T25	5		T140	28
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T221	15		T148	11		T228	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T227	4		T36	7		T232	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T143	12		T230	9		T271	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T26	8		T154	15		T225	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T130	20		T138	13		T182	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T220	3		T137	1		T138	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T10	11		T268	6		T256	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T9	2		T73	8		T169	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T25	3		T137	10		T182	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T26	14		T227	8		T18	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T47	6		T144	10		T227	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T47	11		T222	2		T246	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T170	7		T266	22		T289	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T9	2		T33	3		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T151	10		T145	10		T235	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T221	7		T47	11		T79	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T26	1		T151	13		T170	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T170	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	1		T13	9		T17	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T28	1		T151	15		T145	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T10	1		T25	17		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T9	4		T135	14		T70	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T5	1		T221	3		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T141	1		T233	1		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T25	6		T28	1		T203	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T5	2		T27	4		T37	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1599	1			T1	1		T3	35		T11	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T143	14		T70	20		T71	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T26	11		T37	20		T142	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T163	9		T130	19		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T254	1		T138	12		T145	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T10	12		T47	1		T182	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T9	5		T220	4		T137	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T223	1		T68	1		T179	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T9	1		T26	14		T227	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T7	1		T25	7		T47	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16890	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T47	11		T79	9		T160	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T170	7		T266	22		T272	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T170	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T143	1		T138	1		T71	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T151	10		T145	10		T79	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T10	12		T25	8		T48	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T9	2		T139	9		T182	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T33	1		T77	6		T203	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T233	13		T143	1		T255	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T25	5		T203	1		T242	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T27	1		T221	15		T222	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	937	1			T11	8		T140	28		T166	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T143	12		T230	9		T148	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T26	8		T154	15		T225	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T130	20		T138	13		T243	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T138	11		T145	12		T231	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T10	11		T182	9		T268	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T9	2		T220	3		T137	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T182	7		T83	2		T235	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T26	14		T227	8		T222	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T25	3		T47	6		T144	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	1		T13	1		T28	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T28	1		T182	16		T79	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T10	13		T25	9		T48	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T9	4		T135	1		T70	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T5	1		T221	1		T33	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T27	4		T141	1		T222	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T1	1		T3	3		T11	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T5	2		T37	2		T221	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T28	1		T227	5		T36	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T143	13		T71	1		T230	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T26	9		T37	1		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T163	1		T130	21		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T254	1		T220	4		T137	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T10	12		T47	1		T68	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T9	5		T70	1		T73	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T25	4		T165	1		T223	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T9	1		T26	15		T227	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T7	1		T26	1		T47	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T221	1		T47	12		T222	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T139	1		T170	8		T266	23
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17084	1			T2	10		T6	20		T8	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T151	11		T145	11		T235	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T13	8		T17	2		T139	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T241	4		T240	12		T263	29
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T25	16		T48	12		T229	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T9	2		T135	13		T70	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T221	2		T16	1		T142	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T27	1		T220	20		T19	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1289	1			T3	32		T12	18		T14	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T37	16		T221	17		T224	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T227	2		T36	8		T226	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T143	13		T71	5		T230	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T26	10		T37	19		T142	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T163	8		T130	18		T153	28
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T220	3		T137	12		T138	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T10	11		T183	11		T256	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T9	2		T70	16		T179	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T25	6		T137	9		T179	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T26	13		T136	16		T18	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T47	9		T151	12		T144	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T221	6		T47	10		T246	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T266	23		T289	10		T290	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T184	12		T291	4		T239	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T151	14		T145	12		T235	19

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T221	1		T47	12		T79	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T26	1		T151	1		T170	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T170	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T7	1		T13	1		T17	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T28	1		T151	11		T145	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T10	13		T25	9		T28	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T9	4		T135	1		T70	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T5	1		T221	1		T33	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T141	1		T233	14		T143	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T25	6		T28	1		T203	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T5	2		T27	4		T37	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T1	1		T3	3		T11	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T143	13		T70	1		T71	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T26	9		T37	1		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T163	1		T130	21		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T254	1		T138	12		T145	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T10	12		T47	1		T182	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	5		T220	4		T137	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T223	1		T68	1		T179	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T9	1		T26	15		T227	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T7	1		T25	4		T47	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17026	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T221	6		T47	10		T79	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T151	12		T266	23		T289	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	8		T17	2		T84	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T151	14		T145	12		T241	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T25	16		T48	12		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T9	2		T135	13		T70	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T221	2		T142	14		T191	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T247	18		T157	4		T292	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T25	5		T203	3		T183	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T27	1		T37	16		T221	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T3	32		T12	18		T14	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T143	13		T70	19		T71	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T26	10		T37	19		T142	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T163	8		T130	18		T153	28
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T138	11		T145	3		T173	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T10	11		T219	7		T193	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T9	2		T220	3		T137	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T179	12		T235	7		T183	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T26	13		T136	16		T70	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T25	6		T47	9		T144	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

4214

1

T3

32

T9

4

T10

11