Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26166

1

T1

1

T2

10

T3

35

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22531

1

T1

1

T2

10

T3

35

auto[ADC_CTRL_FILTER_COND_OUT]

3635

1

T7

2

T9

8

T10

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19748

1

T2

10

T5

2

T6

20

auto[1]

6418

1

T1

1

T3

35

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22173

1

T1

1

T2

10

T3

35

auto[1]

3993

1

T9

6

T10

23

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	560	1			T9	4		T27	10		T38	3
values[0]	73	1			T141	1		T293	1		T278	12
values[1]	654	1			T5	1		T25	10		T47	16
values[2]	3013	1			T1	1		T3	35		T11	9
values[3]	630	1			T7	1		T130	39		T33	3
values[4]	703	1			T5	1		T26	28		T27	5
values[5]	661	1			T5	1		T10	23		T13	9
values[6]	581	1			T9	7		T221	7		T254	1
values[7]	786	1			T26	19		T28	1		T135	14
values[8]	609	1			T28	1		T141	1		T223	2
values[9]	1371	1			T7	1		T9	7		T10	13
minimum	16525	1			T2	10		T6	20		T8	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	910	1			T5	1		T25	10		T37	7
values[1]	2911	1			T1	1		T3	35		T7	1
values[2]	773	1			T26	28		T33	3		T152	1
values[3]	619	1			T5	2		T25	25		T27	5
values[4]	592	1			T9	7		T13	9		T254	1
values[5]	699	1			T10	23		T221	7		T47	22
values[6]	810	1			T26	19		T28	2		T135	14
values[7]	582	1			T25	11		T141	1		T223	1
values[8]	940	1			T9	7		T10	13		T26	1
values[9]	264	1			T7	1		T227	21		T169	21
minimum	17066	1			T2	10		T6	20		T8	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

4214

1

T3

32

T9

4

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T5	1		T25	7		T37	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T141	1		T34	3		T153	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1551	1			T1	1		T3	35		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T7	1		T130	19		T139	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T26	14		T33	2		T137	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T152	1		T220	21		T145	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T5	2		T28	1		T163	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T25	17		T27	4		T37	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T254	1		T153	15		T16	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	5		T13	9		T169	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T10	12		T222	1		T18	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T221	7		T47	11		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T26	11		T28	1		T136	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T28	1		T135	14		T151	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T25	6		T141	1		T223	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T68	1		T70	20		T36	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T9	4		T221	18		T144	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T9	1		T10	1		T26	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T227	13		T294	10		T287	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T7	1		T169	12		T262	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16890	1			T2	10		T6	20		T8	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T295	1		T200	15		T296	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T25	3		T47	6		T225	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T220	3		T154	15		T138	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	947	1			T11	8		T140	28		T166	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T130	20		T139	9		T148	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T26	14		T33	1		T137	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T220	3		T145	10		T170	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T143	12		T182	7		T203	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T25	8		T27	1		T139	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T16	2		T73	8		T259	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T9	2		T169	4		T79	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T10	11		T222	2		T18	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T47	11		T33	1		T137	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T26	8		T228	13		T235	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T151	10		T227	4		T222	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T25	5		T257	23		T256	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T36	7		T79	9		T225	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T9	2		T221	15		T144	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T10	12		T48	9		T233	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T227	8		T294	8		T287	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T169	9		T297	6		T250	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	2		T33	3		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T295	2		T296	12		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	537	1			T9	4		T27	10		T38	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T293	1		T298	1		T299	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T141	1		T278	1		T300	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T5	1		T25	7		T47	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T34	3		T220	4		T154	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1575	1			T1	1		T3	35		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T153	15		T139	10		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T33	2		T146	1		T42	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T7	1		T130	19		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T5	1		T26	14		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T27	4		T152	1		T70	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	1		T10	12		T163	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	9		T25	17		T37	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T254	1		T35	1		T70	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	5		T221	7		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T26	11		T222	1		T136	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T28	1		T135	14		T47	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T28	1		T141	1		T223	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T223	1		T83	1		T225	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T9	4		T25	6		T221	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	393	1			T7	1		T9	1		T10	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16389	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T197	8		T301	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T299	11		T302	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T278	11		T300	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T25	3		T47	6		T232	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T220	3		T154	15		T138	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	965	1			T11	8		T140	28		T166	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T139	9		T148	4		T245	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T33	1		T42	4		T87	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T130	20		T220	3		T170	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T26	14		T143	12		T137	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T27	1		T139	9		T145	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T10	11		T16	2		T73	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T25	8		T169	4		T79	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T18	2		T226	16		T242	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T9	2		T33	1		T227	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T26	8		T222	2		T228	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T47	11		T151	10		T143	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T235	13		T257	9		T303	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T83	2		T225	9		T216	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T9	2		T25	5		T221	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T10	12		T48	9		T233	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T5	1		T25	4		T37	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T141	1		T34	3		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T1	1		T3	3		T11	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T7	1		T130	21		T139	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T26	15		T33	3		T137	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T152	1		T220	4		T145	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T5	2		T28	1		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T25	9		T27	4		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T254	1		T153	1		T16	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T9	5		T13	1		T169	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T10	12		T222	3		T18	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T221	1		T47	12		T33	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T26	9		T28	1		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T28	1		T135	1		T151	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T25	6		T141	1		T223	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T68	1		T70	1		T36	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T9	4		T221	16		T144	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T9	1		T10	13		T26	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T227	9		T294	9		T287	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T7	1		T169	10		T262	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17026	1			T2	10		T6	20		T8	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T295	3		T200	1		T296	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T25	6		T37	6		T47	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T153	14		T220	3		T154	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T3	32		T12	18		T14	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T130	18		T139	9		T207	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T26	13		T137	9		T42	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T220	20		T145	12		T191	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T163	8		T142	14		T143	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T25	16		T27	1		T37	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T153	14		T16	1		T70	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T9	2		T13	8		T169	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T10	11		T18	1		T240	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T221	6		T47	10		T137	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T26	10		T136	1		T179	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T135	13		T151	14		T227	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T25	5		T191	16		T257	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T70	19		T36	8		T79	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T9	2		T221	17		T144	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T221	2		T151	12		T48	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T227	12		T294	9		T280	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T169	11		T262	6		T297	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T200	14		T296	9		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	531	1			T9	4		T27	10		T38	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T293	1		T298	1		T299	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T141	1		T278	12		T300	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T5	1		T25	4		T47	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T34	3		T220	4		T154	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1290	1			T1	1		T3	3		T11	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T153	1		T139	10		T148	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T33	3		T146	1		T42	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	1		T130	21		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	1		T26	15		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T27	4		T152	1		T70	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T5	1		T10	12		T163	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T13	1		T25	9		T37	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T254	1		T35	1		T70	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T9	5		T221	1		T33	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T26	9		T222	3		T136	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T28	1		T135	1		T47	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T28	1		T141	1		T223	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T223	1		T83	3		T225	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	397	1			T9	4		T25	6		T221	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	398	1			T7	1		T9	1		T10	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16525	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T197	13		T301	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T299	8		T302	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T300	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T25	6		T47	9		T142	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T220	3		T154	13		T138	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1250	1			T3	32		T12	18		T14	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T153	14		T139	9		T149	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T42	5		T87	3		T97	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T130	18		T220	20		T191	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T26	13		T142	14		T143	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T27	1		T70	16		T139	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T10	11		T163	8		T153	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	8		T25	16		T37	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T70	10		T18	1		T179	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T9	2		T221	6		T227	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T26	10		T136	1		T240	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T135	13		T47	10		T151	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T191	16		T235	19		T263	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T225	8		T216	9		T32	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T9	2		T25	5		T221	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T221	2		T151	12		T48	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

4214

1

T3

32

T9

4

T10

11