Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26166

1

T1

1

T2

10

T3

35

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22636

1

T1

1

T2

10

T3

35

auto[ADC_CTRL_FILTER_COND_OUT]

3530

1

T5

1

T7

1

T9

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20084

1

T2

10

T5

2

T6

20

auto[1]

6082

1

T1

1

T3

35

T5

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22173

1

T1

1

T2

10

T3

35

auto[1]

3993

1

T9

6

T10

23

T11

8

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	6	1			T98	3		T311	1		T312	1
values[0]	46	1			T313	1		T289	19		T314	3
values[1]	643	1			T7	1		T10	23		T25	11
values[2]	754	1			T9	1		T10	13		T26	1
values[3]	639	1			T7	1		T141	1		T152	2
values[4]	643	1			T5	1		T34	3		T153	15
values[5]	2937	1			T1	1		T3	35		T11	9
values[6]	684	1			T5	1		T25	25		T26	28
values[7]	798	1			T221	33		T233	14		T16	7
values[8]	794	1			T9	6		T37	7		T135	14
values[9]	1196	1			T5	1		T9	7		T37	20
minimum	17026	1			T2	10		T6	20		T8	12

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	999	1			T10	36		T25	11		T26	19
values[1]	618	1			T7	1		T26	1		T28	2
values[2]	656	1			T5	1		T9	1		T152	1
values[3]	2810	1			T1	1		T3	35		T11	9
values[4]	807	1			T25	25		T26	28		T254	1
values[5]	533	1			T5	1		T28	1		T37	11
values[6]	853	1			T221	40		T144	22		T233	14
values[7]	716	1			T9	6		T37	27		T163	9
values[8]	970	1			T5	1		T9	7		T135	14
values[9]	152	1			T47	16		T165	1		T33	3
minimum	17052	1			T2	10		T6	20		T7	1

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

4214

1

T3

32

T9

4

T10

11

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T10	13		T221	3		T179	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T25	6		T26	11		T27	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T152	2		T146	1		T169	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	1		T26	1		T28	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T222	1		T136	16		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T5	1		T9	1		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1555	1			T1	1		T3	35		T11	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	9		T25	7		T17	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T25	17		T47	11		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T26	14		T254	1		T151	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T5	1		T37	11		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T28	1		T137	11		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T221	7		T233	1		T139	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T221	18		T144	12		T16	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T9	4		T37	27		T68	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T163	9		T153	15		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T5	1		T135	14		T151	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T9	5		T70	11		T139	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T47	10		T165	1		T33	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T261	1		T315	1		T316	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16892	1			T2	10		T6	20		T7	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T227	13		T146	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T10	23		T182	9		T77	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T25	5		T26	8		T27	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T169	4		T229	9		T266	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T33	1		T236	10		T235	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T222	10		T138	1		T170	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T71	11		T182	7		T155	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	959	1			T11	8		T140	28		T166	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T25	3		T220	3		T18	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T25	8		T47	11		T230	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T26	14		T151	10		T222	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T130	20		T227	4		T143	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T137	11		T148	4		T234	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T233	13		T139	9		T19	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T221	15		T144	10		T16	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T9	2		T36	7		T193	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T143	1		T170	11		T242	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T48	9		T145	12		T42	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T9	2		T243	12		T225	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T47	6		T33	1		T137	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T315	2		T316	20		T317	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T9	2		T33	3		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T227	8		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T98	1		T311	1		T312	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T284	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T313	1		T289	11		T314	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T218	10		T318	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T7	1		T10	12		T221	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T25	6		T26	11		T27	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T10	1		T182	1		T191	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T9	1		T26	1		T28	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T152	1		T222	1		T136	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T7	1		T141	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T34	3		T207	5		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T5	1		T153	15		T220	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1574	1			T1	1		T3	35		T11	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T13	9		T25	7		T151	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	1		T25	17		T37	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T26	14		T28	1		T254	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T233	1		T143	1		T18	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T221	18		T16	5		T224	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T9	4		T37	7		T135	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T144	12		T142	15		T220	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T5	1		T37	20		T47	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T9	5		T163	9		T153	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16890	1			T2	10		T6	20		T8	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T98	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T289	8		T314	2		T319	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T218	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T10	11		T98	3		T320	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T25	5		T26	8		T27	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T10	12		T182	9		T169	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T33	1		T138	13		T236	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T222	10		T138	1		T255	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T71	11		T182	7		T155	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T148	11		T170	7		T268	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T220	3		T143	12		T18	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T11	8		T140	28		T47	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T25	3		T151	10		T222	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T25	8		T130	20		T227	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T26	14		T137	11		T182	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T233	13		T143	1		T18	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T221	15		T16	2		T169	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T9	2		T139	9		T36	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T144	10		T220	3		T143	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T47	6		T48	9		T33	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T9	2		T243	12		T170	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T9	2		T33	3		T34	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T10	25		T221	1		T179	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T25	6		T26	9		T27	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T152	2		T146	1		T169	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T7	1		T26	1		T28	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T222	11		T136	1		T138	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	1		T9	1		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T1	1		T3	3		T11	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	1		T25	4		T17	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T25	9		T47	12		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T26	15		T254	1		T151	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	1		T37	1		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T28	1		T137	13		T148	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T221	1		T233	14		T139	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T221	16		T144	11		T16	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T9	4		T37	2		T68	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T163	1		T153	1		T143	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T5	1		T135	1		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T9	5		T70	1		T139	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T47	7		T165	1		T33	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T261	1		T315	3		T316	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17030	1			T2	10		T6	20		T7	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T227	9		T146	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T10	11		T221	2		T179	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T25	5		T26	10		T27	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T169	14		T229	11		T266	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T235	19		T244	5		T149	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T136	15		T70	19		T191	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T153	14		T70	16		T71	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T3	32		T12	18		T14	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	8		T25	6		T17	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T25	16		T47	10		T230	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T26	13		T151	14		T143	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T37	10		T130	18		T227	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T137	9		T240	9		T260	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T221	6		T139	9		T19	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T221	17		T144	11		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	2		T37	25		T36	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T163	8		T153	14		T240	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T135	13		T151	12		T48	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T9	2		T70	10		T243	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T47	9		T137	12		T321	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T316	15		T317	6		T322	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T227	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T98	3		T311	1		T312	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T284	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T313	1		T289	9		T314	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T218	10		T318	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T7	1		T10	12		T221	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T25	6		T26	9		T27	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T10	13		T182	10		T191	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T9	1		T26	1		T28	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T152	1		T222	11		T136	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	1		T141	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T34	3		T207	1		T148	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	1		T153	1		T220	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T1	1		T3	3		T11	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T13	1		T25	4		T151	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	1		T25	9		T37	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T26	15		T28	1		T254	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T233	14		T143	2		T18	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T221	16		T16	6		T224	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T9	4		T37	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T144	11		T142	1		T220	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T5	1		T37	1		T47	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	370	1			T9	5		T163	1		T153	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17026	1			T2	10		T6	20		T8	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T289	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T218	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T10	11		T221	2		T179	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T25	5		T26	10		T27	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T191	16		T169	14		T77	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T138	13		T235	19		T149	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T136	15		T70	19		T191	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T17	2		T70	16		T179	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T207	4		T247	18		T246	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T153	14		T220	20		T143	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T3	32		T12	18		T14	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	8		T25	6		T151	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T25	16		T37	10		T130	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T26	13		T142	14		T137	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T18	1		T19	6		T203	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T221	17		T16	1		T224	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T9	2		T37	6		T135	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T144	11		T142	14		T220	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T37	19		T47	9		T151	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T9	2		T163	8		T153	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21952

1

T1

1

T2

10

T3

3

auto[1]

auto[0]

4214

1

T3

32

T9

4

T10

11