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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.75 99.07 96.67 100.00 100.00 98.83 98.33 91.34


Total test records in report: 916
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T796 /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3562921148 Apr 02 02:00:24 PM PDT 24 Apr 02 02:19:39 PM PDT 24 491619016670 ps
T797 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.841412102 Apr 02 12:40:05 PM PDT 24 Apr 02 12:40:07 PM PDT 24 308605979 ps
T798 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3341772488 Apr 02 12:39:22 PM PDT 24 Apr 02 12:39:23 PM PDT 24 330817879 ps
T44 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3534394713 Apr 02 12:39:26 PM PDT 24 Apr 02 12:39:35 PM PDT 24 4616834649 ps
T107 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.772709806 Apr 02 12:39:20 PM PDT 24 Apr 02 12:39:23 PM PDT 24 1288802919 ps
T127 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3784154772 Apr 02 12:39:23 PM PDT 24 Apr 02 12:39:26 PM PDT 24 1332738671 ps
T799 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1334634095 Apr 02 12:39:49 PM PDT 24 Apr 02 12:39:51 PM PDT 24 525791276 ps
T122 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3760382150 Apr 02 12:40:04 PM PDT 24 Apr 02 12:40:07 PM PDT 24 328137567 ps
T45 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.763121386 Apr 02 12:39:49 PM PDT 24 Apr 02 12:40:05 PM PDT 24 5678466566 ps
T800 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3730846911 Apr 02 12:39:50 PM PDT 24 Apr 02 12:39:52 PM PDT 24 307600430 ps
T128 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1341586822 Apr 02 12:39:34 PM PDT 24 Apr 02 12:39:39 PM PDT 24 555502629 ps
T52 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.953452957 Apr 02 12:39:45 PM PDT 24 Apr 02 12:39:49 PM PDT 24 590833299 ps
T801 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.603787398 Apr 02 12:39:36 PM PDT 24 Apr 02 12:39:38 PM PDT 24 374690744 ps
T53 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2297854022 Apr 02 12:39:49 PM PDT 24 Apr 02 12:39:51 PM PDT 24 447906791 ps
T802 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1525190910 Apr 02 12:39:49 PM PDT 24 Apr 02 12:39:51 PM PDT 24 301835355 ps
T46 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1411031844 Apr 02 12:39:16 PM PDT 24 Apr 02 12:40:17 PM PDT 24 33227179010 ps
T54 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.703474637 Apr 02 12:39:33 PM PDT 24 Apr 02 12:39:40 PM PDT 24 508204845 ps
T129 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2628643363 Apr 02 12:39:43 PM PDT 24 Apr 02 12:39:45 PM PDT 24 522697059 ps
T108 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1009425009 Apr 02 12:39:22 PM PDT 24 Apr 02 12:39:24 PM PDT 24 599558114 ps
T64 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2580986683 Apr 02 12:39:35 PM PDT 24 Apr 02 12:39:39 PM PDT 24 471567094 ps
T109 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3931109007 Apr 02 12:39:20 PM PDT 24 Apr 02 12:39:23 PM PDT 24 1340976621 ps
T803 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3622119516 Apr 02 12:39:59 PM PDT 24 Apr 02 12:40:00 PM PDT 24 333630712 ps
T49 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.881496204 Apr 02 12:39:34 PM PDT 24 Apr 02 12:39:46 PM PDT 24 8459756682 ps
T123 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3156153514 Apr 02 12:39:48 PM PDT 24 Apr 02 12:39:52 PM PDT 24 2480092591 ps
T110 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1264358501 Apr 02 12:39:25 PM PDT 24 Apr 02 12:39:27 PM PDT 24 511689330 ps
T804 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.886817620 Apr 02 12:40:07 PM PDT 24 Apr 02 12:40:08 PM PDT 24 398593010 ps
T59 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2373464143 Apr 02 12:39:40 PM PDT 24 Apr 02 12:39:43 PM PDT 24 624655239 ps
T805 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2434720887 Apr 02 12:40:05 PM PDT 24 Apr 02 12:40:07 PM PDT 24 343305533 ps
T50 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.914553365 Apr 02 12:39:42 PM PDT 24 Apr 02 12:39:54 PM PDT 24 7954738340 ps
T806 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3156585345 Apr 02 12:39:48 PM PDT 24 Apr 02 12:39:49 PM PDT 24 509106277 ps
T51 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1808102203 Apr 02 12:39:25 PM PDT 24 Apr 02 12:39:29 PM PDT 24 4517607868 ps
T124 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.4211346613 Apr 02 12:39:44 PM PDT 24 Apr 02 12:39:45 PM PDT 24 511759989 ps
T125 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1320189291 Apr 02 12:39:45 PM PDT 24 Apr 02 12:39:51 PM PDT 24 3984163065 ps
T807 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.641403744 Apr 02 12:39:44 PM PDT 24 Apr 02 12:39:45 PM PDT 24 336150287 ps
T75 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3777730798 Apr 02 12:39:45 PM PDT 24 Apr 02 12:39:48 PM PDT 24 607367838 ps
T808 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2256366670 Apr 02 12:39:49 PM PDT 24 Apr 02 12:39:51 PM PDT 24 359589543 ps
T62 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1223617721 Apr 02 12:39:20 PM PDT 24 Apr 02 12:39:22 PM PDT 24 656596957 ps
T111 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3350932068 Apr 02 12:39:23 PM PDT 24 Apr 02 12:39:24 PM PDT 24 559503514 ps
T76 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.874633569 Apr 02 12:39:51 PM PDT 24 Apr 02 12:40:04 PM PDT 24 4799055216 ps
T809 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2749148140 Apr 02 12:39:50 PM PDT 24 Apr 02 12:39:52 PM PDT 24 483685109 ps
T60 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2880179340 Apr 02 12:39:21 PM PDT 24 Apr 02 12:39:24 PM PDT 24 619603969 ps
T112 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4180448176 Apr 02 12:39:21 PM PDT 24 Apr 02 12:39:23 PM PDT 24 499845908 ps
T63 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2760983489 Apr 02 12:39:20 PM PDT 24 Apr 02 12:39:23 PM PDT 24 533103771 ps
T810 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2358557438 Apr 02 12:39:18 PM PDT 24 Apr 02 12:39:21 PM PDT 24 580428938 ps
T113 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3344562666 Apr 02 12:39:22 PM PDT 24 Apr 02 12:39:24 PM PDT 24 530601472 ps
T811 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3921294770 Apr 02 12:39:20 PM PDT 24 Apr 02 12:39:21 PM PDT 24 489101127 ps
T346 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.4046611587 Apr 02 12:39:24 PM PDT 24 Apr 02 12:39:28 PM PDT 24 4578327117 ps
T812 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1564598887 Apr 02 12:39:20 PM PDT 24 Apr 02 12:39:23 PM PDT 24 517944306 ps
T813 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2494320509 Apr 02 12:39:22 PM PDT 24 Apr 02 12:39:24 PM PDT 24 1135830498 ps
T814 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.182999502 Apr 02 12:39:29 PM PDT 24 Apr 02 12:39:30 PM PDT 24 546543877 ps
T55 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1580895701 Apr 02 12:39:29 PM PDT 24 Apr 02 12:39:43 PM PDT 24 4710592972 ps
T815 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3693179847 Apr 02 12:39:45 PM PDT 24 Apr 02 12:39:47 PM PDT 24 351939786 ps
T816 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2537100070 Apr 02 12:39:50 PM PDT 24 Apr 02 12:39:52 PM PDT 24 481266022 ps
T817 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3679141572 Apr 02 12:39:18 PM PDT 24 Apr 02 12:39:20 PM PDT 24 460508171 ps
T818 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1860579746 Apr 02 12:39:26 PM PDT 24 Apr 02 12:39:29 PM PDT 24 556282596 ps
T819 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1636053269 Apr 02 12:39:37 PM PDT 24 Apr 02 12:39:38 PM PDT 24 405312685 ps
T126 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.904478324 Apr 02 12:39:20 PM PDT 24 Apr 02 12:39:25 PM PDT 24 4472821497 ps
T820 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1235687009 Apr 02 12:39:53 PM PDT 24 Apr 02 12:40:00 PM PDT 24 2614857874 ps
T821 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.133418632 Apr 02 12:39:43 PM PDT 24 Apr 02 12:39:45 PM PDT 24 512689600 ps
T822 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1540203539 Apr 02 12:39:52 PM PDT 24 Apr 02 12:39:54 PM PDT 24 296752085 ps
T114 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3405646506 Apr 02 12:39:25 PM PDT 24 Apr 02 12:40:18 PM PDT 24 32901257058 ps
T823 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.223532358 Apr 02 12:39:44 PM PDT 24 Apr 02 12:39:45 PM PDT 24 458972237 ps
T824 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1676707819 Apr 02 12:39:33 PM PDT 24 Apr 02 12:39:49 PM PDT 24 4552681663 ps
T825 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2676069800 Apr 02 12:39:21 PM PDT 24 Apr 02 12:39:22 PM PDT 24 449418956 ps
T826 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2680539708 Apr 02 12:39:21 PM PDT 24 Apr 02 12:39:23 PM PDT 24 457109333 ps
T827 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.364471478 Apr 02 12:39:46 PM PDT 24 Apr 02 12:39:48 PM PDT 24 384143569 ps
T828 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.117114480 Apr 02 12:39:20 PM PDT 24 Apr 02 12:39:22 PM PDT 24 846719179 ps
T829 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.200257959 Apr 02 12:39:41 PM PDT 24 Apr 02 12:39:43 PM PDT 24 601990633 ps
T115 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.941538915 Apr 02 12:39:29 PM PDT 24 Apr 02 12:39:30 PM PDT 24 380713274 ps
T830 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3204559438 Apr 02 12:39:44 PM PDT 24 Apr 02 12:39:45 PM PDT 24 564202590 ps
T831 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2809905686 Apr 02 12:39:49 PM PDT 24 Apr 02 12:39:51 PM PDT 24 532072669 ps
T832 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3859330427 Apr 02 12:39:48 PM PDT 24 Apr 02 12:39:49 PM PDT 24 423462238 ps
T349 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.809913663 Apr 02 12:39:20 PM PDT 24 Apr 02 12:39:39 PM PDT 24 8566289761 ps
T833 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2912823102 Apr 02 12:40:07 PM PDT 24 Apr 02 12:40:09 PM PDT 24 327963923 ps
T834 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3288553289 Apr 02 12:39:39 PM PDT 24 Apr 02 12:39:51 PM PDT 24 4517388151 ps
T835 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.4241078428 Apr 02 12:39:20 PM PDT 24 Apr 02 12:39:22 PM PDT 24 508261042 ps
T836 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.66882326 Apr 02 12:39:34 PM PDT 24 Apr 02 12:39:48 PM PDT 24 4639614717 ps
T837 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1538943576 Apr 02 12:39:31 PM PDT 24 Apr 02 12:39:38 PM PDT 24 390020137 ps
T119 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3291707956 Apr 02 12:39:38 PM PDT 24 Apr 02 12:39:39 PM PDT 24 437613412 ps
T838 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3699869997 Apr 02 12:39:43 PM PDT 24 Apr 02 12:39:49 PM PDT 24 8721299669 ps
T839 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2359843575 Apr 02 12:39:36 PM PDT 24 Apr 02 12:39:38 PM PDT 24 297745032 ps
T840 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2347342799 Apr 02 12:39:21 PM PDT 24 Apr 02 12:39:32 PM PDT 24 27174153594 ps
T841 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.314895008 Apr 02 12:39:41 PM PDT 24 Apr 02 12:39:52 PM PDT 24 2649456124 ps
T842 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1564999823 Apr 02 12:39:51 PM PDT 24 Apr 02 12:39:52 PM PDT 24 622270050 ps
T843 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1079895395 Apr 02 12:40:00 PM PDT 24 Apr 02 12:40:01 PM PDT 24 477316424 ps
T844 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.4075045352 Apr 02 12:39:51 PM PDT 24 Apr 02 12:39:52 PM PDT 24 530043584 ps
T845 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3793429011 Apr 02 12:39:21 PM PDT 24 Apr 02 12:39:30 PM PDT 24 4242946012 ps
T116 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.755126244 Apr 02 12:39:52 PM PDT 24 Apr 02 12:39:53 PM PDT 24 384201151 ps
T846 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.224712917 Apr 02 12:39:17 PM PDT 24 Apr 02 12:39:19 PM PDT 24 360154272 ps
T847 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3604974977 Apr 02 12:39:44 PM PDT 24 Apr 02 12:39:45 PM PDT 24 306697170 ps
T65 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1849294981 Apr 02 12:40:04 PM PDT 24 Apr 02 12:40:26 PM PDT 24 7922395070 ps
T848 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1158521211 Apr 02 12:39:22 PM PDT 24 Apr 02 12:39:23 PM PDT 24 1274615605 ps
T849 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.4052280375 Apr 02 12:39:33 PM PDT 24 Apr 02 12:39:41 PM PDT 24 3225554500 ps
T117 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4078745058 Apr 02 12:39:34 PM PDT 24 Apr 02 12:39:38 PM PDT 24 557845932 ps
T850 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.349883748 Apr 02 12:39:51 PM PDT 24 Apr 02 12:39:52 PM PDT 24 484572542 ps
T851 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.695521616 Apr 02 12:39:28 PM PDT 24 Apr 02 12:39:31 PM PDT 24 562625425 ps
T347 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1985828650 Apr 02 12:39:53 PM PDT 24 Apr 02 12:40:06 PM PDT 24 4366646736 ps
T118 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3630716306 Apr 02 12:39:33 PM PDT 24 Apr 02 12:39:39 PM PDT 24 554727561 ps
T852 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.320738156 Apr 02 12:39:50 PM PDT 24 Apr 02 12:39:53 PM PDT 24 4824288690 ps
T120 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.11219779 Apr 02 12:39:40 PM PDT 24 Apr 02 12:39:41 PM PDT 24 420487295 ps
T853 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1265416096 Apr 02 12:39:43 PM PDT 24 Apr 02 12:39:44 PM PDT 24 478970596 ps
T854 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1556902772 Apr 02 12:39:41 PM PDT 24 Apr 02 12:39:42 PM PDT 24 505478483 ps
T121 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3253709511 Apr 02 12:39:25 PM PDT 24 Apr 02 12:39:26 PM PDT 24 495058608 ps
T855 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4240611780 Apr 02 12:39:59 PM PDT 24 Apr 02 12:40:01 PM PDT 24 482886693 ps
T856 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3675302964 Apr 02 12:39:17 PM PDT 24 Apr 02 12:39:25 PM PDT 24 4843634163 ps
T857 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.469792331 Apr 02 12:39:51 PM PDT 24 Apr 02 12:39:53 PM PDT 24 482729948 ps
T858 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3648686855 Apr 02 12:39:33 PM PDT 24 Apr 02 12:39:39 PM PDT 24 584972676 ps
T859 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.955062528 Apr 02 12:39:28 PM PDT 24 Apr 02 12:39:32 PM PDT 24 2279069997 ps
T860 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3404010367 Apr 02 12:39:54 PM PDT 24 Apr 02 12:39:56 PM PDT 24 286270538 ps
T861 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1313102766 Apr 02 12:39:41 PM PDT 24 Apr 02 12:39:44 PM PDT 24 371257672 ps
T348 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1565823048 Apr 02 12:39:27 PM PDT 24 Apr 02 12:39:50 PM PDT 24 8306283950 ps
T862 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.4213544063 Apr 02 12:39:34 PM PDT 24 Apr 02 12:39:40 PM PDT 24 2171756494 ps
T863 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1761440120 Apr 02 12:39:49 PM PDT 24 Apr 02 12:40:01 PM PDT 24 4499841209 ps
T864 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2565243646 Apr 02 12:39:45 PM PDT 24 Apr 02 12:39:47 PM PDT 24 471897079 ps
T865 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2445204814 Apr 02 12:39:53 PM PDT 24 Apr 02 12:39:54 PM PDT 24 499594625 ps
T866 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.4227174188 Apr 02 12:39:48 PM PDT 24 Apr 02 12:39:56 PM PDT 24 5034980791 ps
T867 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.923530122 Apr 02 12:40:07 PM PDT 24 Apr 02 12:40:08 PM PDT 24 468535971 ps
T868 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3856357522 Apr 02 12:39:47 PM PDT 24 Apr 02 12:39:50 PM PDT 24 539286895 ps
T869 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3221509245 Apr 02 12:39:45 PM PDT 24 Apr 02 12:39:47 PM PDT 24 350110449 ps
T870 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1907054555 Apr 02 12:39:50 PM PDT 24 Apr 02 12:39:51 PM PDT 24 486428038 ps
T871 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1027279902 Apr 02 12:39:24 PM PDT 24 Apr 02 12:39:29 PM PDT 24 1280434256 ps
T872 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2261092246 Apr 02 12:39:26 PM PDT 24 Apr 02 12:39:28 PM PDT 24 681915239 ps
T873 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2343996117 Apr 02 12:40:05 PM PDT 24 Apr 02 12:40:08 PM PDT 24 540176740 ps
T874 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.509812917 Apr 02 12:39:39 PM PDT 24 Apr 02 12:40:00 PM PDT 24 8231241797 ps
T875 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2360887364 Apr 02 12:39:25 PM PDT 24 Apr 02 12:39:27 PM PDT 24 614985115 ps
T876 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2611690751 Apr 02 12:39:19 PM PDT 24 Apr 02 12:39:30 PM PDT 24 4112398399 ps
T877 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1317165914 Apr 02 12:39:45 PM PDT 24 Apr 02 12:39:47 PM PDT 24 306277655 ps
T878 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1448685797 Apr 02 12:39:44 PM PDT 24 Apr 02 12:39:45 PM PDT 24 453803641 ps
T879 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1850653583 Apr 02 12:39:19 PM PDT 24 Apr 02 12:39:24 PM PDT 24 8308398135 ps
T880 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1943477176 Apr 02 12:39:53 PM PDT 24 Apr 02 12:39:57 PM PDT 24 581076677 ps
T881 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1658237166 Apr 02 12:39:22 PM PDT 24 Apr 02 12:39:25 PM PDT 24 522519823 ps
T882 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2975598099 Apr 02 12:39:24 PM PDT 24 Apr 02 12:39:43 PM PDT 24 4738427843 ps
T883 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3568788269 Apr 02 12:39:19 PM PDT 24 Apr 02 12:39:37 PM PDT 24 11619866312 ps
T884 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2573331017 Apr 02 12:39:51 PM PDT 24 Apr 02 12:39:53 PM PDT 24 385406262 ps
T885 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2830674484 Apr 02 12:39:50 PM PDT 24 Apr 02 12:39:54 PM PDT 24 3598933181 ps
T886 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3345000065 Apr 02 12:39:41 PM PDT 24 Apr 02 12:39:42 PM PDT 24 506099156 ps
T887 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.747015891 Apr 02 12:39:40 PM PDT 24 Apr 02 12:39:46 PM PDT 24 2453988355 ps
T888 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2375207246 Apr 02 12:39:23 PM PDT 24 Apr 02 12:39:25 PM PDT 24 642803757 ps
T889 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.342445079 Apr 02 12:39:46 PM PDT 24 Apr 02 12:39:47 PM PDT 24 427974220 ps
T890 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2377145505 Apr 02 12:39:47 PM PDT 24 Apr 02 12:39:49 PM PDT 24 393669851 ps
T891 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3636778995 Apr 02 12:39:16 PM PDT 24 Apr 02 12:39:23 PM PDT 24 4172170239 ps
T892 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3667630252 Apr 02 12:39:22 PM PDT 24 Apr 02 12:39:24 PM PDT 24 518321339 ps
T893 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4207981424 Apr 02 12:39:44 PM PDT 24 Apr 02 12:39:46 PM PDT 24 465950304 ps
T894 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1214235790 Apr 02 12:39:28 PM PDT 24 Apr 02 12:39:30 PM PDT 24 576418056 ps
T895 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3174452353 Apr 02 12:39:49 PM PDT 24 Apr 02 12:39:50 PM PDT 24 383948856 ps
T896 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3183154524 Apr 02 12:39:28 PM PDT 24 Apr 02 12:39:29 PM PDT 24 464690167 ps
T897 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1513771129 Apr 02 12:39:53 PM PDT 24 Apr 02 12:39:54 PM PDT 24 363576311 ps
T898 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.428174952 Apr 02 12:39:49 PM PDT 24 Apr 02 12:39:51 PM PDT 24 622248448 ps
T899 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3899523177 Apr 02 12:39:37 PM PDT 24 Apr 02 12:39:41 PM PDT 24 599284070 ps
T900 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3501179070 Apr 02 12:39:25 PM PDT 24 Apr 02 12:39:28 PM PDT 24 438084339 ps
T901 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3569912192 Apr 02 12:39:20 PM PDT 24 Apr 02 12:39:35 PM PDT 24 19940926818 ps
T902 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.868336734 Apr 02 12:39:38 PM PDT 24 Apr 02 12:39:39 PM PDT 24 314406673 ps
T903 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1351178818 Apr 02 12:39:59 PM PDT 24 Apr 02 12:40:01 PM PDT 24 372816001 ps
T904 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2881096319 Apr 02 12:39:17 PM PDT 24 Apr 02 12:39:22 PM PDT 24 1293926878 ps
T905 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3264189729 Apr 02 12:39:39 PM PDT 24 Apr 02 12:39:40 PM PDT 24 579383111 ps
T906 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2734625572 Apr 02 12:39:23 PM PDT 24 Apr 02 12:39:24 PM PDT 24 516392463 ps
T907 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2423878554 Apr 02 12:39:24 PM PDT 24 Apr 02 12:39:25 PM PDT 24 2160560387 ps
T908 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2655244037 Apr 02 12:39:42 PM PDT 24 Apr 02 12:39:53 PM PDT 24 4487777322 ps
T909 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3337005975 Apr 02 12:39:46 PM PDT 24 Apr 02 12:39:48 PM PDT 24 463779120 ps
T910 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1653678589 Apr 02 12:39:38 PM PDT 24 Apr 02 12:39:42 PM PDT 24 484533165 ps
T911 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1595483737 Apr 02 12:39:42 PM PDT 24 Apr 02 12:39:45 PM PDT 24 2846980563 ps
T912 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3461823998 Apr 02 12:39:32 PM PDT 24 Apr 02 12:39:39 PM PDT 24 522178157 ps
T913 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.919615864 Apr 02 12:39:55 PM PDT 24 Apr 02 12:39:57 PM PDT 24 393146505 ps
T914 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.846232082 Apr 02 12:39:29 PM PDT 24 Apr 02 12:39:40 PM PDT 24 4673290889 ps
T915 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2175697989 Apr 02 12:39:29 PM PDT 24 Apr 02 12:39:31 PM PDT 24 342228255 ps
T916 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1093606421 Apr 02 12:39:43 PM PDT 24 Apr 02 12:39:44 PM PDT 24 462659577 ps

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.860471775
Short name T9
Test name
Test status
Simulation time 174394969028 ps
CPU time 93.16 seconds
Started Apr 02 01:57:41 PM PDT 24
Finished Apr 02 01:59:14 PM PDT 24
Peak memory 210500 kb
Host smart-bb6e5156-dfc2-436f-a7d9-c23853860b79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860471775 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.860471775
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.973408991
Short name T25
Test name
Test status
Simulation time 497236250347 ps
CPU time 323.22 seconds
Started Apr 02 01:51:39 PM PDT 24
Finished Apr 02 01:57:02 PM PDT 24
Peak memory 201936 kb
Host smart-517e01ab-6325-4d42-8f61-693dd9dc95ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973408991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.973408991
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1992571975
Short name T40
Test name
Test status
Simulation time 100288387182 ps
CPU time 529.62 seconds
Started Apr 02 01:59:26 PM PDT 24
Finished Apr 02 02:08:16 PM PDT 24
Peak memory 202244 kb
Host smart-178873cb-ee42-4fb8-8ead-a82504bd649c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992571975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1992571975
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1085258352
Short name T10
Test name
Test status
Simulation time 343418956539 ps
CPU time 785.6 seconds
Started Apr 02 01:56:46 PM PDT 24
Finished Apr 02 02:09:52 PM PDT 24
Peak memory 201864 kb
Host smart-c0a0a2a0-ac9d-4e77-9af8-6a5257332b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085258352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1085258352
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3588548387
Short name T47
Test name
Test status
Simulation time 515538365927 ps
CPU time 550.88 seconds
Started Apr 02 01:52:32 PM PDT 24
Finished Apr 02 02:01:43 PM PDT 24
Peak memory 201888 kb
Host smart-7e8936f6-24ac-4758-94a1-d2307780b40d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588548387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3588548387
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.4251883890
Short name T42
Test name
Test status
Simulation time 197220236453 ps
CPU time 345.11 seconds
Started Apr 02 01:54:41 PM PDT 24
Finished Apr 02 02:00:26 PM PDT 24
Peak memory 210444 kb
Host smart-ab51bf2a-c92e-4b73-a796-84486726e97e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251883890 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.4251883890
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.4054006367
Short name T220
Test name
Test status
Simulation time 341712722280 ps
CPU time 766.92 seconds
Started Apr 02 01:59:11 PM PDT 24
Finished Apr 02 02:11:58 PM PDT 24
Peak memory 201888 kb
Host smart-93547f15-ef48-4163-9a32-85383f59b5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054006367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.4054006367
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2427756965
Short name T138
Test name
Test status
Simulation time 482932109052 ps
CPU time 819.04 seconds
Started Apr 02 01:51:17 PM PDT 24
Finished Apr 02 02:04:56 PM PDT 24
Peak memory 201872 kb
Host smart-0861ce94-8b2f-4aec-bd4e-e3809c3b912a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427756965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2427756965
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.981376619
Short name T221
Test name
Test status
Simulation time 505926985081 ps
CPU time 325.38 seconds
Started Apr 02 01:58:43 PM PDT 24
Finished Apr 02 02:04:08 PM PDT 24
Peak memory 201832 kb
Host smart-006972f6-b0c9-4a18-acbf-9e32efe4bc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981376619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.981376619
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.703474637
Short name T54
Test name
Test status
Simulation time 508204845 ps
CPU time 2.95 seconds
Started Apr 02 12:39:33 PM PDT 24
Finished Apr 02 12:39:40 PM PDT 24
Peak memory 201992 kb
Host smart-88e0ddc2-6d9f-4a4f-a1a5-c43db3e5cfe8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703474637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.703474637
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3253059864
Short name T160
Test name
Test status
Simulation time 533855960927 ps
CPU time 125.14 seconds
Started Apr 02 01:51:40 PM PDT 24
Finished Apr 02 01:53:46 PM PDT 24
Peak memory 201948 kb
Host smart-923d3c23-e103-41ae-aac2-db357425a19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253059864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3253059864
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.1899908347
Short name T37
Test name
Test status
Simulation time 543277115065 ps
CPU time 633.44 seconds
Started Apr 02 01:56:45 PM PDT 24
Finished Apr 02 02:07:19 PM PDT 24
Peak memory 201896 kb
Host smart-b4b3013b-0755-43c7-90e9-14575e028aa1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899908347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.1899908347
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1674531485
Short name T56
Test name
Test status
Simulation time 3432920726 ps
CPU time 9.21 seconds
Started Apr 02 01:51:20 PM PDT 24
Finished Apr 02 01:51:30 PM PDT 24
Peak memory 217380 kb
Host smart-582b3469-cd3e-49a8-87c9-64a7a079f2d0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674531485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1674531485
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3804868512
Short name T169
Test name
Test status
Simulation time 325911819775 ps
CPU time 162.72 seconds
Started Apr 02 01:53:54 PM PDT 24
Finished Apr 02 01:56:37 PM PDT 24
Peak memory 201980 kb
Host smart-7a8be076-933e-409f-8c26-9f15c0086d64
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804868512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3804868512
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.3926260893
Short name T256
Test name
Test status
Simulation time 538706087037 ps
CPU time 1324.79 seconds
Started Apr 02 01:51:56 PM PDT 24
Finished Apr 02 02:14:01 PM PDT 24
Peak memory 201824 kb
Host smart-0653ef1d-2d17-4c15-b2a9-0673b3613b77
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926260893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.3926260893
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.1328988116
Short name T170
Test name
Test status
Simulation time 483676226491 ps
CPU time 181.61 seconds
Started Apr 02 01:51:32 PM PDT 24
Finished Apr 02 01:54:34 PM PDT 24
Peak memory 201884 kb
Host smart-7fbafef9-0193-4cad-a7c3-33647375411b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328988116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1328988116
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1411031844
Short name T46
Test name
Test status
Simulation time 33227179010 ps
CPU time 61.38 seconds
Started Apr 02 12:39:16 PM PDT 24
Finished Apr 02 12:40:17 PM PDT 24
Peak memory 201956 kb
Host smart-5bd30ba0-8bd3-4ca4-9e1a-e10367d01813
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411031844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1411031844
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.1609049210
Short name T226
Test name
Test status
Simulation time 341305369304 ps
CPU time 736.95 seconds
Started Apr 02 01:52:03 PM PDT 24
Finished Apr 02 02:04:20 PM PDT 24
Peak memory 201916 kb
Host smart-7bb4812a-f257-4138-a9d1-968f7b531de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609049210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.1609049210
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.4138415680
Short name T26
Test name
Test status
Simulation time 528973945718 ps
CPU time 1240.87 seconds
Started Apr 02 01:51:45 PM PDT 24
Finished Apr 02 02:12:27 PM PDT 24
Peak memory 201860 kb
Host smart-a6e77abd-6746-475e-91cc-dacd9b0e9a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138415680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.4138415680
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3238604647
Short name T32
Test name
Test status
Simulation time 503673419718 ps
CPU time 560.06 seconds
Started Apr 02 01:52:14 PM PDT 24
Finished Apr 02 02:01:34 PM PDT 24
Peak memory 201916 kb
Host smart-3e90fb16-534d-41d0-88fd-3360eaded86a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238604647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3238604647
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.867021049
Short name T137
Test name
Test status
Simulation time 519326725736 ps
CPU time 751.54 seconds
Started Apr 02 01:54:10 PM PDT 24
Finished Apr 02 02:06:42 PM PDT 24
Peak memory 201948 kb
Host smart-59c01763-e54a-4d5e-a1c2-9b8d9ca2584f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867021049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gati
ng.867021049
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2295403434
Short name T257
Test name
Test status
Simulation time 642914730404 ps
CPU time 1371.64 seconds
Started Apr 02 01:53:42 PM PDT 24
Finished Apr 02 02:16:33 PM PDT 24
Peak memory 201940 kb
Host smart-537e3327-f66e-4cc5-9cbb-0a9e4cdd6894
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295403434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2295403434
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.3380622790
Short name T140
Test name
Test status
Simulation time 487861757125 ps
CPU time 126.44 seconds
Started Apr 02 01:52:29 PM PDT 24
Finished Apr 02 01:54:35 PM PDT 24
Peak memory 201848 kb
Host smart-6d4bde1f-2f43-48f6-be34-ae348b4f0b1b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380622790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.3380622790
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.1326416917
Short name T71
Test name
Test status
Simulation time 412245118071 ps
CPU time 1152.89 seconds
Started Apr 02 02:00:17 PM PDT 24
Finished Apr 02 02:19:30 PM PDT 24
Peak memory 202268 kb
Host smart-e66fdf65-962b-4421-8b83-d873f7db6dc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326416917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.1326416917
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.4021034363
Short name T225
Test name
Test status
Simulation time 326735018499 ps
CPU time 138.1 seconds
Started Apr 02 02:00:13 PM PDT 24
Finished Apr 02 02:02:32 PM PDT 24
Peak memory 201900 kb
Host smart-b4ad231d-0a18-4760-9196-633f16be8d99
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021034363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.4021034363
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.10818093
Short name T227
Test name
Test status
Simulation time 584162644802 ps
CPU time 1360.3 seconds
Started Apr 02 01:58:52 PM PDT 24
Finished Apr 02 02:21:32 PM PDT 24
Peak memory 201860 kb
Host smart-38c9a328-55b4-409b-a692-c0bf78927326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10818093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.10818093
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.2650868396
Short name T289
Test name
Test status
Simulation time 333564492381 ps
CPU time 213.88 seconds
Started Apr 02 01:57:00 PM PDT 24
Finished Apr 02 02:00:34 PM PDT 24
Peak memory 201888 kb
Host smart-27f5ac61-d111-4837-a48b-94cace835d36
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650868396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.2650868396
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.2036440847
Short name T139
Test name
Test status
Simulation time 787220782966 ps
CPU time 855.35 seconds
Started Apr 02 02:00:45 PM PDT 24
Finished Apr 02 02:15:02 PM PDT 24
Peak memory 202188 kb
Host smart-dc267843-3da9-48d4-b9df-fdd7b26bec79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036440847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.2036440847
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2161685714
Short name T15
Test name
Test status
Simulation time 515466929 ps
CPU time 1.23 seconds
Started Apr 02 01:51:23 PM PDT 24
Finished Apr 02 01:51:24 PM PDT 24
Peak memory 201520 kb
Host smart-8c77e561-8573-4054-9518-7a0eed37624e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161685714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2161685714
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.138645429
Short name T142
Test name
Test status
Simulation time 371257323174 ps
CPU time 421.51 seconds
Started Apr 02 01:56:11 PM PDT 24
Finished Apr 02 02:03:13 PM PDT 24
Peak memory 201900 kb
Host smart-b2297066-930a-47eb-b8ac-ae99739746de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138645429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_
wakeup.138645429
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.881496204
Short name T49
Test name
Test status
Simulation time 8459756682 ps
CPU time 8.78 seconds
Started Apr 02 12:39:34 PM PDT 24
Finished Apr 02 12:39:46 PM PDT 24
Peak memory 201928 kb
Host smart-b09671a7-6341-43dc-a98a-f62b603525f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881496204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_in
tg_err.881496204
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.3327761673
Short name T145
Test name
Test status
Simulation time 344767234772 ps
CPU time 713.21 seconds
Started Apr 02 01:59:32 PM PDT 24
Finished Apr 02 02:11:26 PM PDT 24
Peak memory 201876 kb
Host smart-9d7288e2-f09f-4b50-8e42-03b56f0c4fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327761673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.3327761673
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1492091366
Short name T252
Test name
Test status
Simulation time 557352980646 ps
CPU time 1206.56 seconds
Started Apr 02 01:52:53 PM PDT 24
Finished Apr 02 02:13:00 PM PDT 24
Peak memory 202004 kb
Host smart-9bbcb23b-d77a-42fc-b7b6-e4c36647637f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492091366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1492091366
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.957393001
Short name T33
Test name
Test status
Simulation time 208173325174 ps
CPU time 173.57 seconds
Started Apr 02 01:51:29 PM PDT 24
Finished Apr 02 01:54:23 PM PDT 24
Peak memory 210612 kb
Host smart-49192f47-c514-437a-9963-05f81ce78cc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957393001 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.957393001
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3104821342
Short name T200
Test name
Test status
Simulation time 358796568502 ps
CPU time 213.47 seconds
Started Apr 02 01:56:27 PM PDT 24
Finished Apr 02 02:00:01 PM PDT 24
Peak memory 201884 kb
Host smart-52fdfd8d-feef-41c2-ace7-504ed2813f6e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104821342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3104821342
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.456437267
Short name T316
Test name
Test status
Simulation time 519183737592 ps
CPU time 103.08 seconds
Started Apr 02 02:02:00 PM PDT 24
Finished Apr 02 02:03:43 PM PDT 24
Peak memory 201912 kb
Host smart-232ca867-9a9e-43fd-9f51-36571c633e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456437267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.456437267
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.239660225
Short name T218
Test name
Test status
Simulation time 504537295939 ps
CPU time 303.25 seconds
Started Apr 02 02:00:13 PM PDT 24
Finished Apr 02 02:05:16 PM PDT 24
Peak memory 201904 kb
Host smart-2e36aebb-aa16-44b0-b90e-a3a942a158f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239660225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.239660225
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1300304332
Short name T105
Test name
Test status
Simulation time 336232981464 ps
CPU time 712.34 seconds
Started Apr 02 01:52:46 PM PDT 24
Finished Apr 02 02:04:39 PM PDT 24
Peak memory 201864 kb
Host smart-aca51b78-1f58-42c8-91c7-723106636c19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300304332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1300304332
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1654593663
Short name T299
Test name
Test status
Simulation time 177651001254 ps
CPU time 336.71 seconds
Started Apr 02 01:54:28 PM PDT 24
Finished Apr 02 02:00:05 PM PDT 24
Peak memory 201868 kb
Host smart-d5fd5112-ea9b-42ab-9daa-9b19fac07586
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654593663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1654593663
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.497938424
Short name T266
Test name
Test status
Simulation time 170271420673 ps
CPU time 406.1 seconds
Started Apr 02 01:58:20 PM PDT 24
Finished Apr 02 02:05:07 PM PDT 24
Peak memory 201876 kb
Host smart-f4ba0172-eea0-4bbe-bb78-166aef2f90cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497938424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.497938424
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1907989233
Short name T196
Test name
Test status
Simulation time 321925546398 ps
CPU time 182.47 seconds
Started Apr 02 01:51:47 PM PDT 24
Finished Apr 02 01:54:50 PM PDT 24
Peak memory 201888 kb
Host smart-f22bc2e2-4596-4eb9-8e3c-50653155c073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907989233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1907989233
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1891131232
Short name T327
Test name
Test status
Simulation time 528900150097 ps
CPU time 443.3 seconds
Started Apr 02 01:53:14 PM PDT 24
Finished Apr 02 02:00:37 PM PDT 24
Peak memory 201948 kb
Host smart-1e3fa16a-f100-4632-9142-e3cd6893d37c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891131232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1891131232
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3513205383
Short name T183
Test name
Test status
Simulation time 565679348552 ps
CPU time 284.98 seconds
Started Apr 02 01:57:47 PM PDT 24
Finished Apr 02 02:02:32 PM PDT 24
Peak memory 201868 kb
Host smart-9bc162fe-1fce-410a-91a2-009215a8dc04
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513205383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3513205383
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2198935504
Short name T283
Test name
Test status
Simulation time 175261833917 ps
CPU time 52.63 seconds
Started Apr 02 02:02:01 PM PDT 24
Finished Apr 02 02:02:54 PM PDT 24
Peak memory 201984 kb
Host smart-bf80fe5d-fda9-46e0-831d-4d3a48e5629d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198935504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2198935504
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1747312471
Short name T22
Test name
Test status
Simulation time 780454918234 ps
CPU time 859.66 seconds
Started Apr 02 01:54:14 PM PDT 24
Finished Apr 02 02:08:34 PM PDT 24
Peak memory 210464 kb
Host smart-5a5092d9-6113-4cb9-9ab7-ca4ab76bac92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747312471 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1747312471
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.4180448176
Short name T112
Test name
Test status
Simulation time 499845908 ps
CPU time 1.18 seconds
Started Apr 02 12:39:21 PM PDT 24
Finished Apr 02 12:39:23 PM PDT 24
Peak memory 201704 kb
Host smart-dffb8446-2ea6-4784-95cc-6587a676d64d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180448176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.4180448176
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.784283545
Short name T278
Test name
Test status
Simulation time 492610393833 ps
CPU time 297.16 seconds
Started Apr 02 01:52:18 PM PDT 24
Finished Apr 02 01:57:16 PM PDT 24
Peak memory 201808 kb
Host smart-37247431-75aa-4e93-bd4c-ecab2e71bc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784283545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.784283545
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.2863074337
Short name T301
Test name
Test status
Simulation time 511316363813 ps
CPU time 399.66 seconds
Started Apr 02 01:59:34 PM PDT 24
Finished Apr 02 02:06:14 PM PDT 24
Peak memory 201860 kb
Host smart-8666372f-ca65-4d32-aa06-fada253c1074
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863074337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.2863074337
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.1367486134
Short name T72
Test name
Test status
Simulation time 420660794552 ps
CPU time 891.82 seconds
Started Apr 02 01:52:17 PM PDT 24
Finished Apr 02 02:07:09 PM PDT 24
Peak memory 201872 kb
Host smart-81271b6c-7f94-4da0-9f4a-d71c699a4755
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367486134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.1367486134
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.3440707923
Short name T186
Test name
Test status
Simulation time 587208038442 ps
CPU time 63.56 seconds
Started Apr 02 01:53:31 PM PDT 24
Finished Apr 02 01:54:35 PM PDT 24
Peak memory 201900 kb
Host smart-3679f595-a97a-481a-9449-74d99d2fa193
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440707923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.3440707923
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.582559261
Short name T273
Test name
Test status
Simulation time 327863452536 ps
CPU time 766.56 seconds
Started Apr 02 01:51:32 PM PDT 24
Finished Apr 02 02:04:19 PM PDT 24
Peak memory 201896 kb
Host smart-3cc3196c-c122-4786-a715-a3c9bd6bd7e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582559261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.582559261
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2856802634
Short name T323
Test name
Test status
Simulation time 442455091729 ps
CPU time 362.85 seconds
Started Apr 02 01:59:01 PM PDT 24
Finished Apr 02 02:05:04 PM PDT 24
Peak memory 202188 kb
Host smart-9ca6bac0-39b5-4567-be3e-50d9d51231cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856802634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2856802634
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.648062658
Short name T16
Test name
Test status
Simulation time 26602709237 ps
CPU time 72.78 seconds
Started Apr 02 01:59:27 PM PDT 24
Finished Apr 02 02:00:40 PM PDT 24
Peak memory 210468 kb
Host smart-0b0292fd-5b31-4578-9a31-2a6827088afb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648062658 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.648062658
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3504685529
Short name T263
Test name
Test status
Simulation time 533803079155 ps
CPU time 1266.84 seconds
Started Apr 02 02:00:22 PM PDT 24
Finished Apr 02 02:21:29 PM PDT 24
Peak memory 201964 kb
Host smart-ebd555e4-906b-4d96-abc7-a52a8a43d40f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504685529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3504685529
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1985828650
Short name T347
Test name
Test status
Simulation time 4366646736 ps
CPU time 12.38 seconds
Started Apr 02 12:39:53 PM PDT 24
Finished Apr 02 12:40:06 PM PDT 24
Peak memory 201936 kb
Host smart-5bf6616c-b3fe-4ef3-8b01-6596826b60de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985828650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1985828650
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.1347541687
Short name T48
Test name
Test status
Simulation time 175907652381 ps
CPU time 113.73 seconds
Started Apr 02 01:51:25 PM PDT 24
Finished Apr 02 01:53:19 PM PDT 24
Peak memory 201964 kb
Host smart-a751e932-9bec-4274-9e39-d8c0bd91d7a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347541687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.1347541687
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.1267531646
Short name T141
Test name
Test status
Simulation time 335018000176 ps
CPU time 773.16 seconds
Started Apr 02 01:56:04 PM PDT 24
Finished Apr 02 02:08:57 PM PDT 24
Peak memory 201876 kb
Host smart-66230a88-26e6-45a8-a137-ac68e87769be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267531646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1267531646
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.2282367306
Short name T238
Test name
Test status
Simulation time 582734940590 ps
CPU time 1295.94 seconds
Started Apr 02 01:56:16 PM PDT 24
Finished Apr 02 02:17:52 PM PDT 24
Peak memory 201876 kb
Host smart-e00b352d-0e5f-4444-92f3-b2a1b0bd2378
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282367306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.2282367306
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.2969086319
Short name T264
Test name
Test status
Simulation time 320066258710 ps
CPU time 278.08 seconds
Started Apr 02 01:57:10 PM PDT 24
Finished Apr 02 02:01:48 PM PDT 24
Peak memory 201860 kb
Host smart-6d84a4cf-7e9b-49bf-bf1d-5567054975de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969086319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.2969086319
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.553220090
Short name T98
Test name
Test status
Simulation time 484120156405 ps
CPU time 495.63 seconds
Started Apr 02 01:57:29 PM PDT 24
Finished Apr 02 02:05:45 PM PDT 24
Peak memory 201820 kb
Host smart-1db66081-4883-4b69-b837-e304512e01a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553220090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.553220090
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.1368030898
Short name T253
Test name
Test status
Simulation time 60894657134 ps
CPU time 234.23 seconds
Started Apr 02 01:58:25 PM PDT 24
Finished Apr 02 02:02:19 PM PDT 24
Peak memory 210612 kb
Host smart-426e11d6-c50d-4214-b985-b18752b90ff2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368030898 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.1368030898
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2655756383
Short name T79
Test name
Test status
Simulation time 471434489564 ps
CPU time 898.9 seconds
Started Apr 02 02:01:53 PM PDT 24
Finished Apr 02 02:16:52 PM PDT 24
Peak memory 210420 kb
Host smart-bf5e0c69-8a4b-49af-968a-99659f4aeb46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655756383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2655756383
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.4151190976
Short name T189
Test name
Test status
Simulation time 394456967124 ps
CPU time 100.69 seconds
Started Apr 02 01:51:58 PM PDT 24
Finished Apr 02 01:53:38 PM PDT 24
Peak memory 201972 kb
Host smart-16cd93be-830c-4027-8d4f-ebc77fb3237e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151190976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.4151190976
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.1416181933
Short name T282
Test name
Test status
Simulation time 330882567874 ps
CPU time 173.24 seconds
Started Apr 02 01:51:58 PM PDT 24
Finished Apr 02 01:54:52 PM PDT 24
Peak memory 201852 kb
Host smart-e85e9549-8eaa-4499-94ca-9b08c0949e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416181933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.1416181933
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.632878072
Short name T320
Test name
Test status
Simulation time 493264332192 ps
CPU time 1167.04 seconds
Started Apr 02 01:58:06 PM PDT 24
Finished Apr 02 02:17:33 PM PDT 24
Peak memory 201880 kb
Host smart-c7a78150-cc4f-48c8-9636-12fc0a1cced6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632878072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.632878072
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3474405175
Short name T136
Test name
Test status
Simulation time 389536310797 ps
CPU time 900.74 seconds
Started Apr 02 01:58:05 PM PDT 24
Finished Apr 02 02:13:06 PM PDT 24
Peak memory 201856 kb
Host smart-b97f3b89-1aab-4939-b6c3-18d5b4e4753f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474405175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3474405175
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.495126338
Short name T91
Test name
Test status
Simulation time 102512833819 ps
CPU time 538.35 seconds
Started Apr 02 01:58:24 PM PDT 24
Finished Apr 02 02:07:23 PM PDT 24
Peak memory 202200 kb
Host smart-837706ad-2538-419a-bf55-73a25250afbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495126338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.495126338
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2460985746
Short name T284
Test name
Test status
Simulation time 498359222916 ps
CPU time 569.61 seconds
Started Apr 02 01:51:20 PM PDT 24
Finished Apr 02 02:00:49 PM PDT 24
Peak memory 201884 kb
Host smart-7662bba4-75fd-4994-9a8d-750fb80fd684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460985746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2460985746
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2528594089
Short name T74
Test name
Test status
Simulation time 67364032555 ps
CPU time 394.76 seconds
Started Apr 02 01:52:57 PM PDT 24
Finished Apr 02 01:59:32 PM PDT 24
Peak memory 202236 kb
Host smart-2aea3230-0311-42a6-adbc-f5e0707bb0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528594089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2528594089
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.2957577036
Short name T188
Test name
Test status
Simulation time 329828343078 ps
CPU time 125.33 seconds
Started Apr 02 01:55:29 PM PDT 24
Finished Apr 02 01:57:34 PM PDT 24
Peak memory 201868 kb
Host smart-8e9f7dc4-51ff-4d85-b4c8-99513445649a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957577036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.2957577036
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.223621360
Short name T27
Test name
Test status
Simulation time 85990424926 ps
CPU time 301.07 seconds
Started Apr 02 01:51:34 PM PDT 24
Finished Apr 02 01:56:35 PM PDT 24
Peak memory 210556 kb
Host smart-080cbc10-1ea4-43c6-9749-1825bf3effdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223621360 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.223621360
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.425904940
Short name T277
Test name
Test status
Simulation time 520532631802 ps
CPU time 543.37 seconds
Started Apr 02 01:59:57 PM PDT 24
Finished Apr 02 02:09:01 PM PDT 24
Peak memory 201892 kb
Host smart-38053aa6-1ca2-46de-a287-ed6d4140e426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425904940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.425904940
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.3236759730
Short name T219
Test name
Test status
Simulation time 333576949246 ps
CPU time 716.36 seconds
Started Apr 02 02:01:05 PM PDT 24
Finished Apr 02 02:13:02 PM PDT 24
Peak memory 201908 kb
Host smart-e6433032-12a4-4544-9ddf-0312f88eb950
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236759730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.3236759730
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2777639393
Short name T28
Test name
Test status
Simulation time 492350512468 ps
CPU time 278.41 seconds
Started Apr 02 01:51:44 PM PDT 24
Finished Apr 02 01:56:23 PM PDT 24
Peak memory 201804 kb
Host smart-5b508dbc-b3a5-4f1c-a620-71120a4a289a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777639393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2777639393
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.3442395945
Short name T296
Test name
Test status
Simulation time 510673724499 ps
CPU time 1160.85 seconds
Started Apr 02 01:51:57 PM PDT 24
Finished Apr 02 02:11:18 PM PDT 24
Peak memory 201804 kb
Host smart-1c6278e9-18d9-4163-9a43-7388e5f30939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442395945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.3442395945
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1849294981
Short name T65
Test name
Test status
Simulation time 7922395070 ps
CPU time 20.87 seconds
Started Apr 02 12:40:04 PM PDT 24
Finished Apr 02 12:40:26 PM PDT 24
Peak memory 201932 kb
Host smart-55c38b47-1318-4ff2-b17c-9bf927d6de64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849294981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.1849294981
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.942611381
Short name T300
Test name
Test status
Simulation time 523127773659 ps
CPU time 706.09 seconds
Started Apr 02 01:51:22 PM PDT 24
Finished Apr 02 02:03:09 PM PDT 24
Peak memory 201876 kb
Host smart-a9c4d83c-4281-4681-aaf1-50d27f20b6f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942611381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin
g.942611381
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.2181633816
Short name T341
Test name
Test status
Simulation time 331160000544 ps
CPU time 184.62 seconds
Started Apr 02 01:52:32 PM PDT 24
Finished Apr 02 01:55:37 PM PDT 24
Peak memory 201892 kb
Host smart-e26ab11c-c20e-4b41-834b-d32e951f4548
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181633816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.2181633816
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.2017847499
Short name T272
Test name
Test status
Simulation time 497643369810 ps
CPU time 272.87 seconds
Started Apr 02 01:53:08 PM PDT 24
Finished Apr 02 01:57:41 PM PDT 24
Peak memory 201960 kb
Host smart-a01c75b2-008e-44cf-bebf-2f9c26184142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017847499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2017847499
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.2023773262
Short name T215
Test name
Test status
Simulation time 114368298259 ps
CPU time 425.38 seconds
Started Apr 02 01:54:36 PM PDT 24
Finished Apr 02 02:01:42 PM PDT 24
Peak memory 202252 kb
Host smart-27194726-25fc-473b-a9bf-9b4891c64ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023773262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2023773262
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1735997920
Short name T70
Test name
Test status
Simulation time 510257604351 ps
CPU time 1087.39 seconds
Started Apr 02 01:55:25 PM PDT 24
Finished Apr 02 02:13:33 PM PDT 24
Peak memory 201944 kb
Host smart-a6b76156-fa61-445e-8f90-688ae41437b7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735997920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.1735997920
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.1709066171
Short name T274
Test name
Test status
Simulation time 458021622727 ps
CPU time 1045.32 seconds
Started Apr 02 01:56:11 PM PDT 24
Finished Apr 02 02:13:37 PM PDT 24
Peak memory 201888 kb
Host smart-30b355d1-3a6d-4f34-b8ee-b005ccccd1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709066171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.1709066171
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3003066827
Short name T208
Test name
Test status
Simulation time 343370588051 ps
CPU time 211.89 seconds
Started Apr 02 01:51:28 PM PDT 24
Finished Apr 02 01:55:00 PM PDT 24
Peak memory 201868 kb
Host smart-fdcc9c84-aae2-4dcb-87c9-3c455d857b81
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003066827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3003066827
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3277245273
Short name T199
Test name
Test status
Simulation time 536259164099 ps
CPU time 299.89 seconds
Started Apr 02 01:58:38 PM PDT 24
Finished Apr 02 02:03:38 PM PDT 24
Peak memory 201908 kb
Host smart-b2c41cbb-e9ac-4eac-85d0-64edf0b84218
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277245273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3277245273
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2756905524
Short name T212
Test name
Test status
Simulation time 102285448016 ps
CPU time 371.32 seconds
Started Apr 02 01:51:31 PM PDT 24
Finished Apr 02 01:57:42 PM PDT 24
Peak memory 202248 kb
Host smart-2f8314e8-7e1e-443f-88a5-0fed32aa0666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756905524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2756905524
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1658237166
Short name T881
Test name
Test status
Simulation time 522519823 ps
CPU time 2.55 seconds
Started Apr 02 12:39:22 PM PDT 24
Finished Apr 02 12:39:25 PM PDT 24
Peak memory 201776 kb
Host smart-ced6c6f8-55e5-4b03-a570-6d160621cefa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658237166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1658237166
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.772709806
Short name T107
Test name
Test status
Simulation time 1288802919 ps
CPU time 3.31 seconds
Started Apr 02 12:39:20 PM PDT 24
Finished Apr 02 12:39:23 PM PDT 24
Peak memory 201668 kb
Host smart-a382db74-786c-4d69-93f7-2c8cd40c56e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772709806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_re
set.772709806
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1223617721
Short name T62
Test name
Test status
Simulation time 656596957 ps
CPU time 1.21 seconds
Started Apr 02 12:39:20 PM PDT 24
Finished Apr 02 12:39:22 PM PDT 24
Peak memory 201768 kb
Host smart-adc75f7e-e91f-4f99-8d66-812261c5cea7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223617721 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1223617721
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.224712917
Short name T846
Test name
Test status
Simulation time 360154272 ps
CPU time 0.85 seconds
Started Apr 02 12:39:17 PM PDT 24
Finished Apr 02 12:39:19 PM PDT 24
Peak memory 201588 kb
Host smart-eab9607b-2539-4a11-8d7a-ae9e551cd74c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224712917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.224712917
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.3675302964
Short name T856
Test name
Test status
Simulation time 4843634163 ps
CPU time 6.85 seconds
Started Apr 02 12:39:17 PM PDT 24
Finished Apr 02 12:39:25 PM PDT 24
Peak memory 201988 kb
Host smart-a326817c-179a-4764-b410-8f9711ec60c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675302964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.3675302964
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2880179340
Short name T60
Test name
Test status
Simulation time 619603969 ps
CPU time 3.64 seconds
Started Apr 02 12:39:21 PM PDT 24
Finished Apr 02 12:39:24 PM PDT 24
Peak memory 211116 kb
Host smart-ac419186-b026-4c6b-9761-9a7097ec9725
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880179340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2880179340
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.3636778995
Short name T891
Test name
Test status
Simulation time 4172170239 ps
CPU time 6.69 seconds
Started Apr 02 12:39:16 PM PDT 24
Finished Apr 02 12:39:23 PM PDT 24
Peak memory 201964 kb
Host smart-2126e4af-e97e-42a7-9d7b-44fbb942957b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636778995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.3636778995
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3931109007
Short name T109
Test name
Test status
Simulation time 1340976621 ps
CPU time 2.69 seconds
Started Apr 02 12:39:20 PM PDT 24
Finished Apr 02 12:39:23 PM PDT 24
Peak memory 201852 kb
Host smart-ec6da508-45c4-4f5b-bcf1-602ced403b1b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931109007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3931109007
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3569912192
Short name T901
Test name
Test status
Simulation time 19940926818 ps
CPU time 14.49 seconds
Started Apr 02 12:39:20 PM PDT 24
Finished Apr 02 12:39:35 PM PDT 24
Peak memory 201984 kb
Host smart-d5fab5a7-dcdb-4b7d-9f0b-31fe6acc701e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569912192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3569912192
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.117114480
Short name T828
Test name
Test status
Simulation time 846719179 ps
CPU time 1.68 seconds
Started Apr 02 12:39:20 PM PDT 24
Finished Apr 02 12:39:22 PM PDT 24
Peak memory 201660 kb
Host smart-a3845601-82b2-442e-ba0f-d7d5d71cf753
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117114480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_re
set.117114480
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3679141572
Short name T817
Test name
Test status
Simulation time 460508171 ps
CPU time 1.15 seconds
Started Apr 02 12:39:18 PM PDT 24
Finished Apr 02 12:39:20 PM PDT 24
Peak memory 201700 kb
Host smart-792b80d4-6e55-4f56-91d6-3eba4c8f35a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679141572 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3679141572
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2734625572
Short name T906
Test name
Test status
Simulation time 516392463 ps
CPU time 1.07 seconds
Started Apr 02 12:39:23 PM PDT 24
Finished Apr 02 12:39:24 PM PDT 24
Peak memory 201668 kb
Host smart-fe50ae56-25d9-4a73-a619-b9c77fa73d9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734625572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2734625572
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3921294770
Short name T811
Test name
Test status
Simulation time 489101127 ps
CPU time 1.04 seconds
Started Apr 02 12:39:20 PM PDT 24
Finished Apr 02 12:39:21 PM PDT 24
Peak memory 201700 kb
Host smart-e7d45d4b-c250-4426-b0bd-9f29673a94eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921294770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3921294770
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3793429011
Short name T845
Test name
Test status
Simulation time 4242946012 ps
CPU time 9.06 seconds
Started Apr 02 12:39:21 PM PDT 24
Finished Apr 02 12:39:30 PM PDT 24
Peak memory 201932 kb
Host smart-3b82885c-7ee3-4e5f-9c18-ccc85e1765ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793429011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3793429011
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2358557438
Short name T810
Test name
Test status
Simulation time 580428938 ps
CPU time 2.45 seconds
Started Apr 02 12:39:18 PM PDT 24
Finished Apr 02 12:39:21 PM PDT 24
Peak memory 218312 kb
Host smart-9a79986d-7f02-4396-ad86-7e185481ce3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358557438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2358557438
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.809913663
Short name T349
Test name
Test status
Simulation time 8566289761 ps
CPU time 19.17 seconds
Started Apr 02 12:39:20 PM PDT 24
Finished Apr 02 12:39:39 PM PDT 24
Peak memory 201916 kb
Host smart-92be46ea-5f8c-4d66-be3c-1b4fc6c69325
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809913663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_int
g_err.809913663
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.2580986683
Short name T64
Test name
Test status
Simulation time 471567094 ps
CPU time 1.94 seconds
Started Apr 02 12:39:35 PM PDT 24
Finished Apr 02 12:39:39 PM PDT 24
Peak memory 201756 kb
Host smart-f364e0e0-139e-4441-987a-3036c53160a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580986683 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.2580986683
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.3630716306
Short name T118
Test name
Test status
Simulation time 554727561 ps
CPU time 1.51 seconds
Started Apr 02 12:39:33 PM PDT 24
Finished Apr 02 12:39:39 PM PDT 24
Peak memory 201616 kb
Host smart-ddfa2539-227d-4a55-9677-5e83c45fc6b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630716306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.3630716306
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.641403744
Short name T807
Test name
Test status
Simulation time 336150287 ps
CPU time 0.87 seconds
Started Apr 02 12:39:44 PM PDT 24
Finished Apr 02 12:39:45 PM PDT 24
Peak memory 201676 kb
Host smart-35883096-11b7-4d81-9203-6f5887c8370f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641403744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.641403744
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.4213544063
Short name T862
Test name
Test status
Simulation time 2171756494 ps
CPU time 2.4 seconds
Started Apr 02 12:39:34 PM PDT 24
Finished Apr 02 12:39:40 PM PDT 24
Peak memory 201776 kb
Host smart-6ec4ce40-c9d8-42f4-8f37-430cc4593127
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213544063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.4213544063
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2373464143
Short name T59
Test name
Test status
Simulation time 624655239 ps
CPU time 2.08 seconds
Started Apr 02 12:39:40 PM PDT 24
Finished Apr 02 12:39:43 PM PDT 24
Peak memory 201968 kb
Host smart-71255e64-2d38-45e5-b607-5bac09c73267
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373464143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2373464143
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.1580895701
Short name T55
Test name
Test status
Simulation time 4710592972 ps
CPU time 13.1 seconds
Started Apr 02 12:39:29 PM PDT 24
Finished Apr 02 12:39:43 PM PDT 24
Peak memory 201948 kb
Host smart-74b9f41f-2263-4481-a77c-12c40693b164
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580895701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.1580895701
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1093606421
Short name T916
Test name
Test status
Simulation time 462659577 ps
CPU time 1.43 seconds
Started Apr 02 12:39:43 PM PDT 24
Finished Apr 02 12:39:44 PM PDT 24
Peak memory 201752 kb
Host smart-a30644ea-9fb9-477e-b38d-3a0cc89b1dfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093606421 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1093606421
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2628643363
Short name T129
Test name
Test status
Simulation time 522697059 ps
CPU time 1.26 seconds
Started Apr 02 12:39:43 PM PDT 24
Finished Apr 02 12:39:45 PM PDT 24
Peak memory 201692 kb
Host smart-dfb74879-22fb-40b9-a53a-5baef5b4bd85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628643363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2628643363
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.868336734
Short name T902
Test name
Test status
Simulation time 314406673 ps
CPU time 1.04 seconds
Started Apr 02 12:39:38 PM PDT 24
Finished Apr 02 12:39:39 PM PDT 24
Peak memory 201652 kb
Host smart-7c3ef410-e8a4-4624-a2a0-713fbecde1b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868336734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.868336734
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.66882326
Short name T836
Test name
Test status
Simulation time 4639614717 ps
CPU time 10.51 seconds
Started Apr 02 12:39:34 PM PDT 24
Finished Apr 02 12:39:48 PM PDT 24
Peak memory 201896 kb
Host smart-9441d557-527b-4909-b1f3-1c2e4d9ea357
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66882326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ct
rl_same_csr_outstanding.66882326
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3221509245
Short name T869
Test name
Test status
Simulation time 350110449 ps
CPU time 1.64 seconds
Started Apr 02 12:39:45 PM PDT 24
Finished Apr 02 12:39:47 PM PDT 24
Peak memory 201676 kb
Host smart-69a7190d-e6b0-4371-8e54-2d6877b4b021
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221509245 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.3221509245
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.4078745058
Short name T117
Test name
Test status
Simulation time 557845932 ps
CPU time 0.81 seconds
Started Apr 02 12:39:34 PM PDT 24
Finished Apr 02 12:39:38 PM PDT 24
Peak memory 201716 kb
Host smart-8f032022-a77b-4f28-a2d6-24590df3f1db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078745058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.4078745058
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1317165914
Short name T877
Test name
Test status
Simulation time 306277655 ps
CPU time 0.98 seconds
Started Apr 02 12:39:45 PM PDT 24
Finished Apr 02 12:39:47 PM PDT 24
Peak memory 201596 kb
Host smart-0281f094-ac6c-4e07-b81b-72273b62ee9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317165914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1317165914
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.763121386
Short name T45
Test name
Test status
Simulation time 5678466566 ps
CPU time 14.8 seconds
Started Apr 02 12:39:49 PM PDT 24
Finished Apr 02 12:40:05 PM PDT 24
Peak memory 201824 kb
Host smart-b706eb29-2bb3-4923-a60d-d0f2d41a9088
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763121386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.763121386
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4207981424
Short name T893
Test name
Test status
Simulation time 465950304 ps
CPU time 1.34 seconds
Started Apr 02 12:39:44 PM PDT 24
Finished Apr 02 12:39:46 PM PDT 24
Peak memory 201684 kb
Host smart-9d05e75c-9dc2-49c3-bef2-31a4134ca6f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207981424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.4207981424
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.320738156
Short name T852
Test name
Test status
Simulation time 4824288690 ps
CPU time 2.13 seconds
Started Apr 02 12:39:50 PM PDT 24
Finished Apr 02 12:39:53 PM PDT 24
Peak memory 201920 kb
Host smart-ab1c50b4-2890-4bc2-bc5b-2d424572347c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320738156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_in
tg_err.320738156
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3264189729
Short name T905
Test name
Test status
Simulation time 579383111 ps
CPU time 1.17 seconds
Started Apr 02 12:39:39 PM PDT 24
Finished Apr 02 12:39:40 PM PDT 24
Peak memory 201728 kb
Host smart-1971aa79-0f47-4ae8-8185-130dcc963709
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264189729 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3264189729
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.4211346613
Short name T124
Test name
Test status
Simulation time 511759989 ps
CPU time 0.86 seconds
Started Apr 02 12:39:44 PM PDT 24
Finished Apr 02 12:39:45 PM PDT 24
Peak memory 201660 kb
Host smart-be048afe-fc59-4e38-a5d4-9c3b61eb7e27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211346613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.4211346613
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.603787398
Short name T801
Test name
Test status
Simulation time 374690744 ps
CPU time 0.84 seconds
Started Apr 02 12:39:36 PM PDT 24
Finished Apr 02 12:39:38 PM PDT 24
Peak memory 201708 kb
Host smart-e140a0eb-cdaa-46d9-8511-a4f6fa07d570
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603787398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.603787398
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3156153514
Short name T123
Test name
Test status
Simulation time 2480092591 ps
CPU time 3.51 seconds
Started Apr 02 12:39:48 PM PDT 24
Finished Apr 02 12:39:52 PM PDT 24
Peak memory 201696 kb
Host smart-3baf5d5d-f779-450a-9a16-9032647ecefd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156153514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3156153514
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.3204559438
Short name T830
Test name
Test status
Simulation time 564202590 ps
CPU time 1.59 seconds
Started Apr 02 12:39:44 PM PDT 24
Finished Apr 02 12:39:45 PM PDT 24
Peak memory 201952 kb
Host smart-97921b71-db7e-43f2-a755-7a560b00ea3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204559438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.3204559438
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1761440120
Short name T863
Test name
Test status
Simulation time 4499841209 ps
CPU time 11.85 seconds
Started Apr 02 12:39:49 PM PDT 24
Finished Apr 02 12:40:01 PM PDT 24
Peak memory 201932 kb
Host smart-caa638ee-51fd-422e-b866-d68b7b34d1b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761440120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1761440120
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3337005975
Short name T909
Test name
Test status
Simulation time 463779120 ps
CPU time 1.73 seconds
Started Apr 02 12:39:46 PM PDT 24
Finished Apr 02 12:39:48 PM PDT 24
Peak memory 201728 kb
Host smart-e93e61d7-5c94-4df2-a8da-a3848dee40de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337005975 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3337005975
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3856357522
Short name T868
Test name
Test status
Simulation time 539286895 ps
CPU time 1.53 seconds
Started Apr 02 12:39:47 PM PDT 24
Finished Apr 02 12:39:50 PM PDT 24
Peak memory 201668 kb
Host smart-044a1b1f-cc4d-46b1-a1b6-5c64b0d59fab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856357522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.3856357522
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.2573331017
Short name T884
Test name
Test status
Simulation time 385406262 ps
CPU time 1.62 seconds
Started Apr 02 12:39:51 PM PDT 24
Finished Apr 02 12:39:53 PM PDT 24
Peak memory 201680 kb
Host smart-28eafc8c-24d9-4711-bd8a-f026690d22b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573331017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.2573331017
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2655244037
Short name T908
Test name
Test status
Simulation time 4487777322 ps
CPU time 11.21 seconds
Started Apr 02 12:39:42 PM PDT 24
Finished Apr 02 12:39:53 PM PDT 24
Peak memory 201952 kb
Host smart-b6870089-b3bc-4f7b-9405-856c6d1d6dcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655244037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2655244037
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1653678589
Short name T910
Test name
Test status
Simulation time 484533165 ps
CPU time 3.25 seconds
Started Apr 02 12:39:38 PM PDT 24
Finished Apr 02 12:39:42 PM PDT 24
Peak memory 218276 kb
Host smart-2d83e278-1f07-47e0-8acc-6177de78d074
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653678589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1653678589
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3288553289
Short name T834
Test name
Test status
Simulation time 4517388151 ps
CPU time 11.81 seconds
Started Apr 02 12:39:39 PM PDT 24
Finished Apr 02 12:39:51 PM PDT 24
Peak memory 201896 kb
Host smart-0d2de6ac-f98e-45a1-aa31-52f25d6a45d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288553289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.3288553289
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.428174952
Short name T898
Test name
Test status
Simulation time 622248448 ps
CPU time 1.16 seconds
Started Apr 02 12:39:49 PM PDT 24
Finished Apr 02 12:39:51 PM PDT 24
Peak memory 201744 kb
Host smart-0089ce23-d6b0-4f6f-8236-32bf09638c93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428174952 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.428174952
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1265416096
Short name T853
Test name
Test status
Simulation time 478970596 ps
CPU time 1 seconds
Started Apr 02 12:39:43 PM PDT 24
Finished Apr 02 12:39:44 PM PDT 24
Peak memory 201708 kb
Host smart-a9a449a0-70e0-4029-8a9f-e305b3d475b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265416096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.1265416096
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.223532358
Short name T823
Test name
Test status
Simulation time 458972237 ps
CPU time 1.73 seconds
Started Apr 02 12:39:44 PM PDT 24
Finished Apr 02 12:39:45 PM PDT 24
Peak memory 201672 kb
Host smart-55afb01b-9fc4-4ab1-9aba-54e3ce576d65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223532358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.223532358
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1595483737
Short name T911
Test name
Test status
Simulation time 2846980563 ps
CPU time 2.72 seconds
Started Apr 02 12:39:42 PM PDT 24
Finished Apr 02 12:39:45 PM PDT 24
Peak memory 201856 kb
Host smart-a9e4819e-d013-45d5-99ee-df11c8c952b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595483737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1595483737
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2565243646
Short name T864
Test name
Test status
Simulation time 471897079 ps
CPU time 2.59 seconds
Started Apr 02 12:39:45 PM PDT 24
Finished Apr 02 12:39:47 PM PDT 24
Peak memory 201844 kb
Host smart-985b64c2-6dd5-4fab-bfc5-42f036c9e29e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565243646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.2565243646
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.509812917
Short name T874
Test name
Test status
Simulation time 8231241797 ps
CPU time 21.08 seconds
Started Apr 02 12:39:39 PM PDT 24
Finished Apr 02 12:40:00 PM PDT 24
Peak memory 201904 kb
Host smart-247157ce-1c8f-4c1f-b720-f084e8801f30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509812917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_in
tg_err.509812917
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2297854022
Short name T53
Test name
Test status
Simulation time 447906791 ps
CPU time 1.12 seconds
Started Apr 02 12:39:49 PM PDT 24
Finished Apr 02 12:39:51 PM PDT 24
Peak memory 201760 kb
Host smart-eeb28a50-83d8-4204-85da-0756c6b8ef9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297854022 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2297854022
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3760382150
Short name T122
Test name
Test status
Simulation time 328137567 ps
CPU time 1.43 seconds
Started Apr 02 12:40:04 PM PDT 24
Finished Apr 02 12:40:07 PM PDT 24
Peak memory 201688 kb
Host smart-39ff9251-6c3b-452d-9c1f-6e7e6ec4191a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760382150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3760382150
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1556902772
Short name T854
Test name
Test status
Simulation time 505478483 ps
CPU time 0.96 seconds
Started Apr 02 12:39:41 PM PDT 24
Finished Apr 02 12:39:42 PM PDT 24
Peak memory 201652 kb
Host smart-08055f5a-3a3a-4d45-9093-1d81c730823e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556902772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1556902772
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1235687009
Short name T820
Test name
Test status
Simulation time 2614857874 ps
CPU time 6.37 seconds
Started Apr 02 12:39:53 PM PDT 24
Finished Apr 02 12:40:00 PM PDT 24
Peak memory 201764 kb
Host smart-fef257e7-c29a-4ab3-9e3c-4bbbaec51e26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235687009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1235687009
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.953452957
Short name T52
Test name
Test status
Simulation time 590833299 ps
CPU time 2.97 seconds
Started Apr 02 12:39:45 PM PDT 24
Finished Apr 02 12:39:49 PM PDT 24
Peak memory 210104 kb
Host smart-112cef71-e284-4682-8c40-a0d5655890ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953452957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.953452957
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.874633569
Short name T76
Test name
Test status
Simulation time 4799055216 ps
CPU time 12.54 seconds
Started Apr 02 12:39:51 PM PDT 24
Finished Apr 02 12:40:04 PM PDT 24
Peak memory 201904 kb
Host smart-ac26de7c-b8fe-4451-a266-ca7529afd911
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874633569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_in
tg_err.874633569
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.469792331
Short name T857
Test name
Test status
Simulation time 482729948 ps
CPU time 2.07 seconds
Started Apr 02 12:39:51 PM PDT 24
Finished Apr 02 12:39:53 PM PDT 24
Peak memory 201788 kb
Host smart-f5710d44-0698-4e45-a2ed-f815a7b05bef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469792331 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.469792331
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.364471478
Short name T827
Test name
Test status
Simulation time 384143569 ps
CPU time 1.53 seconds
Started Apr 02 12:39:46 PM PDT 24
Finished Apr 02 12:39:48 PM PDT 24
Peak memory 201696 kb
Host smart-f78240d2-cea2-4706-9ad4-6c03d13556e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364471478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.364471478
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1907054555
Short name T870
Test name
Test status
Simulation time 486428038 ps
CPU time 1.14 seconds
Started Apr 02 12:39:50 PM PDT 24
Finished Apr 02 12:39:51 PM PDT 24
Peak memory 201660 kb
Host smart-1dec30cb-fdd0-4321-9cc1-ccd8ff2fc1bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907054555 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1907054555
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.1320189291
Short name T125
Test name
Test status
Simulation time 3984163065 ps
CPU time 5.62 seconds
Started Apr 02 12:39:45 PM PDT 24
Finished Apr 02 12:39:51 PM PDT 24
Peak memory 201948 kb
Host smart-f2af0b81-d9ba-4782-88b5-b52fdf266547
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320189291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.1320189291
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.200257959
Short name T829
Test name
Test status
Simulation time 601990633 ps
CPU time 1.71 seconds
Started Apr 02 12:39:41 PM PDT 24
Finished Apr 02 12:39:43 PM PDT 24
Peak memory 201956 kb
Host smart-fc6a29b9-4952-4f41-8bf1-ae9c1ed03036
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200257959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.200257959
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2377145505
Short name T890
Test name
Test status
Simulation time 393669851 ps
CPU time 1.2 seconds
Started Apr 02 12:39:47 PM PDT 24
Finished Apr 02 12:39:49 PM PDT 24
Peak memory 201768 kb
Host smart-82084c44-e5f6-42e9-81b7-48563fe3b686
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377145505 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.2377145505
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.755126244
Short name T116
Test name
Test status
Simulation time 384201151 ps
CPU time 1.3 seconds
Started Apr 02 12:39:52 PM PDT 24
Finished Apr 02 12:39:53 PM PDT 24
Peak memory 201672 kb
Host smart-f8c60aff-6663-4f99-a56e-ba5273232462
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755126244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.755126244
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.133418632
Short name T821
Test name
Test status
Simulation time 512689600 ps
CPU time 1.8 seconds
Started Apr 02 12:39:43 PM PDT 24
Finished Apr 02 12:39:45 PM PDT 24
Peak memory 201708 kb
Host smart-98e8b471-a501-44cb-9eba-e79bdfdecbb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133418632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.133418632
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.314895008
Short name T841
Test name
Test status
Simulation time 2649456124 ps
CPU time 10.79 seconds
Started Apr 02 12:39:41 PM PDT 24
Finished Apr 02 12:39:52 PM PDT 24
Peak memory 201948 kb
Host smart-235608a6-a7dc-478f-9e40-3e5f250be348
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314895008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_c
trl_same_csr_outstanding.314895008
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1313102766
Short name T861
Test name
Test status
Simulation time 371257672 ps
CPU time 2.78 seconds
Started Apr 02 12:39:41 PM PDT 24
Finished Apr 02 12:39:44 PM PDT 24
Peak memory 210112 kb
Host smart-14f7daa4-d715-4b02-9e14-38e4128a14e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313102766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1313102766
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3777730798
Short name T75
Test name
Test status
Simulation time 607367838 ps
CPU time 2.25 seconds
Started Apr 02 12:39:45 PM PDT 24
Finished Apr 02 12:39:48 PM PDT 24
Peak memory 201768 kb
Host smart-7f102c58-3d90-4d34-9d16-49e97c063293
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777730798 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3777730798
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2343996117
Short name T873
Test name
Test status
Simulation time 540176740 ps
CPU time 1.35 seconds
Started Apr 02 12:40:05 PM PDT 24
Finished Apr 02 12:40:08 PM PDT 24
Peak memory 201688 kb
Host smart-e865f08a-4f5b-4c28-80a4-4766f636c04c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343996117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2343996117
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2445204814
Short name T865
Test name
Test status
Simulation time 499594625 ps
CPU time 0.91 seconds
Started Apr 02 12:39:53 PM PDT 24
Finished Apr 02 12:39:54 PM PDT 24
Peak memory 201688 kb
Host smart-80de4966-2d79-4fb8-848c-7ab6dec53945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445204814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2445204814
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.2830674484
Short name T885
Test name
Test status
Simulation time 3598933181 ps
CPU time 3.09 seconds
Started Apr 02 12:39:50 PM PDT 24
Finished Apr 02 12:39:54 PM PDT 24
Peak memory 201952 kb
Host smart-2d80faa5-4e99-4870-8063-66285ddb7d8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830674484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.2830674484
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1943477176
Short name T880
Test name
Test status
Simulation time 581076677 ps
CPU time 3.68 seconds
Started Apr 02 12:39:53 PM PDT 24
Finished Apr 02 12:39:57 PM PDT 24
Peak memory 217984 kb
Host smart-ef1797eb-10d8-4d8b-bade-d370cdd78c74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943477176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1943477176
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3699869997
Short name T838
Test name
Test status
Simulation time 8721299669 ps
CPU time 5.85 seconds
Started Apr 02 12:39:43 PM PDT 24
Finished Apr 02 12:39:49 PM PDT 24
Peak memory 202016 kb
Host smart-376dd0c8-bff2-4b2c-bd49-c732d1384c63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699869997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3699869997
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.1009425009
Short name T108
Test name
Test status
Simulation time 599558114 ps
CPU time 2 seconds
Started Apr 02 12:39:22 PM PDT 24
Finished Apr 02 12:39:24 PM PDT 24
Peak memory 201868 kb
Host smart-e019c287-7aef-450a-9cdd-0a5aa9dc5712
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009425009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.1009425009
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3568788269
Short name T883
Test name
Test status
Simulation time 11619866312 ps
CPU time 17.91 seconds
Started Apr 02 12:39:19 PM PDT 24
Finished Apr 02 12:39:37 PM PDT 24
Peak memory 201876 kb
Host smart-e94c4696-5e9f-4ac5-acfa-5deecefea844
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568788269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.3568788269
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2881096319
Short name T904
Test name
Test status
Simulation time 1293926878 ps
CPU time 3.9 seconds
Started Apr 02 12:39:17 PM PDT 24
Finished Apr 02 12:39:22 PM PDT 24
Peak memory 201680 kb
Host smart-cdedea72-2700-4561-b2b4-ba93293aa7ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881096319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.2881096319
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1564598887
Short name T812
Test name
Test status
Simulation time 517944306 ps
CPU time 1.88 seconds
Started Apr 02 12:39:20 PM PDT 24
Finished Apr 02 12:39:23 PM PDT 24
Peak memory 201736 kb
Host smart-a09d411a-77a7-4f11-95c5-ac22fa64ea9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564598887 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.1564598887
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.3344562666
Short name T113
Test name
Test status
Simulation time 530601472 ps
CPU time 1.98 seconds
Started Apr 02 12:39:22 PM PDT 24
Finished Apr 02 12:39:24 PM PDT 24
Peak memory 201680 kb
Host smart-6fb03cd9-6f57-4630-8065-702697574d6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344562666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.3344562666
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3667630252
Short name T892
Test name
Test status
Simulation time 518321339 ps
CPU time 1.76 seconds
Started Apr 02 12:39:22 PM PDT 24
Finished Apr 02 12:39:24 PM PDT 24
Peak memory 201668 kb
Host smart-c497eb27-6e4b-4afb-a98b-f378d527b9b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667630252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3667630252
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.904478324
Short name T126
Test name
Test status
Simulation time 4472821497 ps
CPU time 5.08 seconds
Started Apr 02 12:39:20 PM PDT 24
Finished Apr 02 12:39:25 PM PDT 24
Peak memory 201940 kb
Host smart-4fbfe428-d073-4ced-bb89-40f542da45c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904478324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ct
rl_same_csr_outstanding.904478324
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.4241078428
Short name T835
Test name
Test status
Simulation time 508261042 ps
CPU time 1.69 seconds
Started Apr 02 12:39:20 PM PDT 24
Finished Apr 02 12:39:22 PM PDT 24
Peak memory 201956 kb
Host smart-4d18385b-b2a5-4edc-a3f5-4d089280b9f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241078428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.4241078428
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1850653583
Short name T879
Test name
Test status
Simulation time 8308398135 ps
CPU time 4.48 seconds
Started Apr 02 12:39:19 PM PDT 24
Finished Apr 02 12:39:24 PM PDT 24
Peak memory 202012 kb
Host smart-841f1f97-662a-4ea5-bdce-8cb8c06f8de3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850653583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1850653583
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.3730846911
Short name T800
Test name
Test status
Simulation time 307600430 ps
CPU time 1.39 seconds
Started Apr 02 12:39:50 PM PDT 24
Finished Apr 02 12:39:52 PM PDT 24
Peak memory 201568 kb
Host smart-7f41f35d-381b-4df8-ac5c-fb5d902e9ace
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730846911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.3730846911
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1540203539
Short name T822
Test name
Test status
Simulation time 296752085 ps
CPU time 1.35 seconds
Started Apr 02 12:39:52 PM PDT 24
Finished Apr 02 12:39:54 PM PDT 24
Peak memory 201656 kb
Host smart-45809fac-2777-4747-bf45-af7762c209e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540203539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1540203539
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.349883748
Short name T850
Test name
Test status
Simulation time 484572542 ps
CPU time 0.87 seconds
Started Apr 02 12:39:51 PM PDT 24
Finished Apr 02 12:39:52 PM PDT 24
Peak memory 201640 kb
Host smart-d5c38ae6-f145-4d4e-9483-f4a9273770e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349883748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.349883748
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.3604974977
Short name T847
Test name
Test status
Simulation time 306697170 ps
CPU time 0.77 seconds
Started Apr 02 12:39:44 PM PDT 24
Finished Apr 02 12:39:45 PM PDT 24
Peak memory 201684 kb
Host smart-312697a2-02e8-4b0c-b569-e14d79cbe689
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604974977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.3604974977
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1564999823
Short name T842
Test name
Test status
Simulation time 622270050 ps
CPU time 0.71 seconds
Started Apr 02 12:39:51 PM PDT 24
Finished Apr 02 12:39:52 PM PDT 24
Peak memory 201628 kb
Host smart-7f826811-abc6-46bf-ad97-394d3ac70a40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564999823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1564999823
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.3693179847
Short name T815
Test name
Test status
Simulation time 351939786 ps
CPU time 1.48 seconds
Started Apr 02 12:39:45 PM PDT 24
Finished Apr 02 12:39:47 PM PDT 24
Peak memory 201640 kb
Host smart-7f2b14fe-9454-4180-aa7e-52e94a4392ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693179847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.3693179847
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.342445079
Short name T889
Test name
Test status
Simulation time 427974220 ps
CPU time 1.55 seconds
Started Apr 02 12:39:46 PM PDT 24
Finished Apr 02 12:39:47 PM PDT 24
Peak memory 201708 kb
Host smart-26af9a80-66af-460e-ba13-167906336642
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342445079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.342445079
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.1448685797
Short name T878
Test name
Test status
Simulation time 453803641 ps
CPU time 0.88 seconds
Started Apr 02 12:39:44 PM PDT 24
Finished Apr 02 12:39:45 PM PDT 24
Peak memory 201672 kb
Host smart-4583ebf9-bb1b-449b-a9ff-de136641ade0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448685797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.1448685797
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.3859330427
Short name T832
Test name
Test status
Simulation time 423462238 ps
CPU time 0.87 seconds
Started Apr 02 12:39:48 PM PDT 24
Finished Apr 02 12:39:49 PM PDT 24
Peak memory 201668 kb
Host smart-afd63b76-dbd5-4fb1-a0cb-6a750a370736
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859330427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.3859330427
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.4240611780
Short name T855
Test name
Test status
Simulation time 482886693 ps
CPU time 0.95 seconds
Started Apr 02 12:39:59 PM PDT 24
Finished Apr 02 12:40:01 PM PDT 24
Peak memory 201696 kb
Host smart-982c7022-13ed-4aec-8b01-0582c9bc2c7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240611780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.4240611780
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3784154772
Short name T127
Test name
Test status
Simulation time 1332738671 ps
CPU time 2.65 seconds
Started Apr 02 12:39:23 PM PDT 24
Finished Apr 02 12:39:26 PM PDT 24
Peak memory 201832 kb
Host smart-0876e4e3-5eef-410d-8f7c-af5f93f41621
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784154772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3784154772
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3405646506
Short name T114
Test name
Test status
Simulation time 32901257058 ps
CPU time 52.96 seconds
Started Apr 02 12:39:25 PM PDT 24
Finished Apr 02 12:40:18 PM PDT 24
Peak memory 202000 kb
Host smart-d24a50de-1e9b-48dc-b994-1589cc76e810
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405646506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3405646506
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.2494320509
Short name T813
Test name
Test status
Simulation time 1135830498 ps
CPU time 1.46 seconds
Started Apr 02 12:39:22 PM PDT 24
Finished Apr 02 12:39:24 PM PDT 24
Peak memory 201632 kb
Host smart-b37eb8b5-2f43-4614-9622-9df1fd9b3698
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494320509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.2494320509
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2375207246
Short name T888
Test name
Test status
Simulation time 642803757 ps
CPU time 1.43 seconds
Started Apr 02 12:39:23 PM PDT 24
Finished Apr 02 12:39:25 PM PDT 24
Peak memory 201648 kb
Host smart-45891938-4f90-402e-9319-2590b2700c23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375207246 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.2375207246
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.1264358501
Short name T110
Test name
Test status
Simulation time 511689330 ps
CPU time 1.32 seconds
Started Apr 02 12:39:25 PM PDT 24
Finished Apr 02 12:39:27 PM PDT 24
Peak memory 201684 kb
Host smart-dd1f0629-f8f2-4a71-b258-4c4cbdf637ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264358501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.1264358501
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3341772488
Short name T798
Test name
Test status
Simulation time 330817879 ps
CPU time 1.44 seconds
Started Apr 02 12:39:22 PM PDT 24
Finished Apr 02 12:39:23 PM PDT 24
Peak memory 201644 kb
Host smart-b6dc0879-7793-4a94-b771-c3d58557f312
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341772488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3341772488
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2423878554
Short name T907
Test name
Test status
Simulation time 2160560387 ps
CPU time 1.27 seconds
Started Apr 02 12:39:24 PM PDT 24
Finished Apr 02 12:39:25 PM PDT 24
Peak memory 201704 kb
Host smart-e84e98e0-3288-4ae6-8b1f-f5034c80ec8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423878554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2423878554
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2760983489
Short name T63
Test name
Test status
Simulation time 533103771 ps
CPU time 2.8 seconds
Started Apr 02 12:39:20 PM PDT 24
Finished Apr 02 12:39:23 PM PDT 24
Peak memory 202016 kb
Host smart-7d0144e3-67bb-4680-951e-b3fce633dfe2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760983489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2760983489
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.2611690751
Short name T876
Test name
Test status
Simulation time 4112398399 ps
CPU time 11.41 seconds
Started Apr 02 12:39:19 PM PDT 24
Finished Apr 02 12:39:30 PM PDT 24
Peak memory 201904 kb
Host smart-4722b1cb-95a6-4ec1-a9a7-0a8fbaac9040
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611690751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.2611690751
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1079895395
Short name T843
Test name
Test status
Simulation time 477316424 ps
CPU time 0.99 seconds
Started Apr 02 12:40:00 PM PDT 24
Finished Apr 02 12:40:01 PM PDT 24
Peak memory 201620 kb
Host smart-e1087e7d-6cee-4061-8685-bd344389adf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079895395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1079895395
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3622119516
Short name T803
Test name
Test status
Simulation time 333630712 ps
CPU time 0.81 seconds
Started Apr 02 12:39:59 PM PDT 24
Finished Apr 02 12:40:00 PM PDT 24
Peak memory 201656 kb
Host smart-ee030b91-6bbd-4632-a93e-14435e588501
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622119516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3622119516
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1525190910
Short name T802
Test name
Test status
Simulation time 301835355 ps
CPU time 1.3 seconds
Started Apr 02 12:39:49 PM PDT 24
Finished Apr 02 12:39:51 PM PDT 24
Peak memory 201680 kb
Host smart-2f1eaac6-bc3b-4059-8ce0-b847745f6f85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525190910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1525190910
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2537100070
Short name T816
Test name
Test status
Simulation time 481266022 ps
CPU time 1.83 seconds
Started Apr 02 12:39:50 PM PDT 24
Finished Apr 02 12:39:52 PM PDT 24
Peak memory 201716 kb
Host smart-496faf31-7a88-4931-80aa-ee9b3a0e830f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537100070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2537100070
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2256366670
Short name T808
Test name
Test status
Simulation time 359589543 ps
CPU time 1.4 seconds
Started Apr 02 12:39:49 PM PDT 24
Finished Apr 02 12:39:51 PM PDT 24
Peak memory 201576 kb
Host smart-32a51ed9-25f5-4331-971c-2a1027dc20f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256366670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2256366670
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1334634095
Short name T799
Test name
Test status
Simulation time 525791276 ps
CPU time 0.94 seconds
Started Apr 02 12:39:49 PM PDT 24
Finished Apr 02 12:39:51 PM PDT 24
Peak memory 201704 kb
Host smart-63e0f9d0-2951-44d2-8983-5e16b7e742bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334634095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1334634095
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3404010367
Short name T860
Test name
Test status
Simulation time 286270538 ps
CPU time 1.31 seconds
Started Apr 02 12:39:54 PM PDT 24
Finished Apr 02 12:39:56 PM PDT 24
Peak memory 201676 kb
Host smart-182d4e0c-6b8b-4add-94af-f1d50af237a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404010367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3404010367
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2749148140
Short name T809
Test name
Test status
Simulation time 483685109 ps
CPU time 1.85 seconds
Started Apr 02 12:39:50 PM PDT 24
Finished Apr 02 12:39:52 PM PDT 24
Peak memory 201720 kb
Host smart-db9357f3-de77-4979-8021-5bfa99824ff4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749148140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2749148140
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2809905686
Short name T831
Test name
Test status
Simulation time 532072669 ps
CPU time 1.17 seconds
Started Apr 02 12:39:49 PM PDT 24
Finished Apr 02 12:39:51 PM PDT 24
Peak memory 201684 kb
Host smart-35ab1588-d174-4302-8f63-e2112d57cc67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809905686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2809905686
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3156585345
Short name T806
Test name
Test status
Simulation time 509106277 ps
CPU time 0.88 seconds
Started Apr 02 12:39:48 PM PDT 24
Finished Apr 02 12:39:49 PM PDT 24
Peak memory 201628 kb
Host smart-d1ab8ba9-1095-439d-b5f8-8698dbd4a96b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156585345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3156585345
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1027279902
Short name T871
Test name
Test status
Simulation time 1280434256 ps
CPU time 4.88 seconds
Started Apr 02 12:39:24 PM PDT 24
Finished Apr 02 12:39:29 PM PDT 24
Peak memory 201864 kb
Host smart-1e1623b2-17a6-4075-b4d5-c6e853104164
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027279902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.1027279902
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2347342799
Short name T840
Test name
Test status
Simulation time 27174153594 ps
CPU time 10.74 seconds
Started Apr 02 12:39:21 PM PDT 24
Finished Apr 02 12:39:32 PM PDT 24
Peak memory 201912 kb
Host smart-14aa2128-37b7-445a-b74a-b9e0e4126f90
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347342799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2347342799
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1158521211
Short name T848
Test name
Test status
Simulation time 1274615605 ps
CPU time 1.47 seconds
Started Apr 02 12:39:22 PM PDT 24
Finished Apr 02 12:39:23 PM PDT 24
Peak memory 201644 kb
Host smart-5e2c92db-5cd0-453b-9e71-a25f69b1f0d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158521211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.1158521211
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2680539708
Short name T826
Test name
Test status
Simulation time 457109333 ps
CPU time 1.29 seconds
Started Apr 02 12:39:21 PM PDT 24
Finished Apr 02 12:39:23 PM PDT 24
Peak memory 201740 kb
Host smart-d1576932-6834-4216-b580-c1b3104bff03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680539708 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2680539708
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3350932068
Short name T111
Test name
Test status
Simulation time 559503514 ps
CPU time 0.85 seconds
Started Apr 02 12:39:23 PM PDT 24
Finished Apr 02 12:39:24 PM PDT 24
Peak memory 201696 kb
Host smart-923d333e-dbf4-4028-9dc7-c0b5084c2b83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350932068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3350932068
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.2676069800
Short name T825
Test name
Test status
Simulation time 449418956 ps
CPU time 0.93 seconds
Started Apr 02 12:39:21 PM PDT 24
Finished Apr 02 12:39:22 PM PDT 24
Peak memory 201708 kb
Host smart-5659ae70-b689-4b86-b3d8-f60f339d81eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676069800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.2676069800
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2975598099
Short name T882
Test name
Test status
Simulation time 4738427843 ps
CPU time 19.05 seconds
Started Apr 02 12:39:24 PM PDT 24
Finished Apr 02 12:39:43 PM PDT 24
Peak memory 201976 kb
Host smart-eae34c01-d7b4-475c-b30c-b852785cd6df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975598099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2975598099
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.695521616
Short name T851
Test name
Test status
Simulation time 562625425 ps
CPU time 2.79 seconds
Started Apr 02 12:39:28 PM PDT 24
Finished Apr 02 12:39:31 PM PDT 24
Peak memory 201968 kb
Host smart-be30d857-f06f-48e2-87b8-c9dd43207ea1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695521616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.695521616
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.4046611587
Short name T346
Test name
Test status
Simulation time 4578327117 ps
CPU time 4.12 seconds
Started Apr 02 12:39:24 PM PDT 24
Finished Apr 02 12:39:28 PM PDT 24
Peak memory 201944 kb
Host smart-001eead4-0a3d-430b-b2c2-e83317a9f6e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046611587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.4046611587
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.3174452353
Short name T895
Test name
Test status
Simulation time 383948856 ps
CPU time 1.08 seconds
Started Apr 02 12:39:49 PM PDT 24
Finished Apr 02 12:39:50 PM PDT 24
Peak memory 201704 kb
Host smart-cc6f44ed-c407-4f7b-bb0d-142e1cf3d38f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174452353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.3174452353
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1351178818
Short name T903
Test name
Test status
Simulation time 372816001 ps
CPU time 1.43 seconds
Started Apr 02 12:39:59 PM PDT 24
Finished Apr 02 12:40:01 PM PDT 24
Peak memory 201700 kb
Host smart-6008f02f-10c6-4494-a77f-53b1b3445f01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351178818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1351178818
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.886817620
Short name T804
Test name
Test status
Simulation time 398593010 ps
CPU time 1.1 seconds
Started Apr 02 12:40:07 PM PDT 24
Finished Apr 02 12:40:08 PM PDT 24
Peak memory 201212 kb
Host smart-abdaaca6-5789-4b9a-976e-4e18f4719b14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886817620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.886817620
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2912823102
Short name T833
Test name
Test status
Simulation time 327963923 ps
CPU time 1.43 seconds
Started Apr 02 12:40:07 PM PDT 24
Finished Apr 02 12:40:09 PM PDT 24
Peak memory 201064 kb
Host smart-b92a31da-0df6-4e16-8729-133c82125f1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912823102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2912823102
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.919615864
Short name T913
Test name
Test status
Simulation time 393146505 ps
CPU time 1.53 seconds
Started Apr 02 12:39:55 PM PDT 24
Finished Apr 02 12:39:57 PM PDT 24
Peak memory 201600 kb
Host smart-53da4241-d47b-4247-b173-04159111435a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919615864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.919615864
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.1513771129
Short name T897
Test name
Test status
Simulation time 363576311 ps
CPU time 0.84 seconds
Started Apr 02 12:39:53 PM PDT 24
Finished Apr 02 12:39:54 PM PDT 24
Peak memory 201700 kb
Host smart-54ebdc9c-cabc-4150-9f9f-24f7c840a99f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513771129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.1513771129
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.923530122
Short name T867
Test name
Test status
Simulation time 468535971 ps
CPU time 0.81 seconds
Started Apr 02 12:40:07 PM PDT 24
Finished Apr 02 12:40:08 PM PDT 24
Peak memory 201668 kb
Host smart-13a840bc-0bf4-4485-8013-03c689b226c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923530122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.923530122
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.841412102
Short name T797
Test name
Test status
Simulation time 308605979 ps
CPU time 0.98 seconds
Started Apr 02 12:40:05 PM PDT 24
Finished Apr 02 12:40:07 PM PDT 24
Peak memory 201680 kb
Host smart-2a6d6cb8-a1d6-44c3-a9d4-f52fa1b3e7af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841412102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.841412102
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.4075045352
Short name T844
Test name
Test status
Simulation time 530043584 ps
CPU time 0.99 seconds
Started Apr 02 12:39:51 PM PDT 24
Finished Apr 02 12:39:52 PM PDT 24
Peak memory 201588 kb
Host smart-c935b0e5-3e2f-4ae6-9af2-d5f6c2a743f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075045352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.4075045352
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.2434720887
Short name T805
Test name
Test status
Simulation time 343305533 ps
CPU time 0.85 seconds
Started Apr 02 12:40:05 PM PDT 24
Finished Apr 02 12:40:07 PM PDT 24
Peak memory 201688 kb
Host smart-5d60e8ec-8308-4109-b14a-e923abb80102
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434720887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.2434720887
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2360887364
Short name T875
Test name
Test status
Simulation time 614985115 ps
CPU time 1.4 seconds
Started Apr 02 12:39:25 PM PDT 24
Finished Apr 02 12:39:27 PM PDT 24
Peak memory 201680 kb
Host smart-22d9212b-5c20-4d4e-b854-909bc14e7cd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360887364 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2360887364
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1341586822
Short name T128
Test name
Test status
Simulation time 555502629 ps
CPU time 1.38 seconds
Started Apr 02 12:39:34 PM PDT 24
Finished Apr 02 12:39:39 PM PDT 24
Peak memory 201664 kb
Host smart-7cd77bff-4619-4dac-a675-0572076664f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341586822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.1341586822
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2359843575
Short name T839
Test name
Test status
Simulation time 297745032 ps
CPU time 1.25 seconds
Started Apr 02 12:39:36 PM PDT 24
Finished Apr 02 12:39:38 PM PDT 24
Peak memory 201708 kb
Host smart-d7824ed4-331d-4792-ac9a-b6cd04cc814a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359843575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2359843575
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.955062528
Short name T859
Test name
Test status
Simulation time 2279069997 ps
CPU time 4.07 seconds
Started Apr 02 12:39:28 PM PDT 24
Finished Apr 02 12:39:32 PM PDT 24
Peak memory 201728 kb
Host smart-1fa52a75-6b47-4085-a259-060d27ffacfd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955062528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.955062528
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2261092246
Short name T872
Test name
Test status
Simulation time 681915239 ps
CPU time 1.97 seconds
Started Apr 02 12:39:26 PM PDT 24
Finished Apr 02 12:39:28 PM PDT 24
Peak memory 201972 kb
Host smart-fc7c7bdf-95f8-408a-9afe-d681efd45ae8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261092246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.2261092246
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1808102203
Short name T51
Test name
Test status
Simulation time 4517607868 ps
CPU time 3.59 seconds
Started Apr 02 12:39:25 PM PDT 24
Finished Apr 02 12:39:29 PM PDT 24
Peak memory 201916 kb
Host smart-fdad6688-61fc-48db-a3db-8b0a2a70f5da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808102203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1808102203
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.1214235790
Short name T894
Test name
Test status
Simulation time 576418056 ps
CPU time 2.11 seconds
Started Apr 02 12:39:28 PM PDT 24
Finished Apr 02 12:39:30 PM PDT 24
Peak memory 201756 kb
Host smart-a2dbf369-be83-4f25-ae8e-96955c9bd604
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214235790 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.1214235790
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3253709511
Short name T121
Test name
Test status
Simulation time 495058608 ps
CPU time 0.91 seconds
Started Apr 02 12:39:25 PM PDT 24
Finished Apr 02 12:39:26 PM PDT 24
Peak memory 201628 kb
Host smart-d24a294d-568d-42a6-a4e4-a3cc6955d80f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253709511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3253709511
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3183154524
Short name T896
Test name
Test status
Simulation time 464690167 ps
CPU time 1.15 seconds
Started Apr 02 12:39:28 PM PDT 24
Finished Apr 02 12:39:29 PM PDT 24
Peak memory 201680 kb
Host smart-8b9809de-2a7e-46de-8c73-9a4c125f7393
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183154524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3183154524
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.3534394713
Short name T44
Test name
Test status
Simulation time 4616834649 ps
CPU time 8.29 seconds
Started Apr 02 12:39:26 PM PDT 24
Finished Apr 02 12:39:35 PM PDT 24
Peak memory 201920 kb
Host smart-70e6108e-fb17-42cc-97e2-a41bc0a39108
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534394713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.3534394713
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3501179070
Short name T900
Test name
Test status
Simulation time 438084339 ps
CPU time 2.29 seconds
Started Apr 02 12:39:25 PM PDT 24
Finished Apr 02 12:39:28 PM PDT 24
Peak memory 201960 kb
Host smart-0c865380-76d3-42c3-8740-4cd1576f0dfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501179070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.3501179070
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1565823048
Short name T348
Test name
Test status
Simulation time 8306283950 ps
CPU time 22.19 seconds
Started Apr 02 12:39:27 PM PDT 24
Finished Apr 02 12:39:50 PM PDT 24
Peak memory 201952 kb
Host smart-f4990b85-481a-467f-8b7d-7d4677a9938a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565823048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1565823048
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.1538943576
Short name T837
Test name
Test status
Simulation time 390020137 ps
CPU time 1.24 seconds
Started Apr 02 12:39:31 PM PDT 24
Finished Apr 02 12:39:38 PM PDT 24
Peak memory 201740 kb
Host smart-57ba1e71-f3e4-4a41-8f52-ba0eaef6dfad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538943576 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.1538943576
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.11219779
Short name T120
Test name
Test status
Simulation time 420487295 ps
CPU time 0.86 seconds
Started Apr 02 12:39:40 PM PDT 24
Finished Apr 02 12:39:41 PM PDT 24
Peak memory 201668 kb
Host smart-f82c301e-05a6-46eb-95fe-7a286e3f6b37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11219779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.11219779
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2175697989
Short name T915
Test name
Test status
Simulation time 342228255 ps
CPU time 1.06 seconds
Started Apr 02 12:39:29 PM PDT 24
Finished Apr 02 12:39:31 PM PDT 24
Peak memory 201728 kb
Host smart-162afea2-dd45-4970-bb5c-0b74ae47e1e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175697989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2175697989
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.4227174188
Short name T866
Test name
Test status
Simulation time 5034980791 ps
CPU time 6.99 seconds
Started Apr 02 12:39:48 PM PDT 24
Finished Apr 02 12:39:56 PM PDT 24
Peak memory 201828 kb
Host smart-c492cd39-51ba-4506-86b3-53749ff946c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227174188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.4227174188
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.1860579746
Short name T818
Test name
Test status
Simulation time 556282596 ps
CPU time 3.02 seconds
Started Apr 02 12:39:26 PM PDT 24
Finished Apr 02 12:39:29 PM PDT 24
Peak memory 218276 kb
Host smart-19f47f48-5d90-474f-8cd3-f68d173784ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860579746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.1860579746
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1676707819
Short name T824
Test name
Test status
Simulation time 4552681663 ps
CPU time 11.52 seconds
Started Apr 02 12:39:33 PM PDT 24
Finished Apr 02 12:39:49 PM PDT 24
Peak memory 202000 kb
Host smart-8bafd518-0e48-4c75-bc6b-13db0db34a89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676707819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1676707819
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.3345000065
Short name T886
Test name
Test status
Simulation time 506099156 ps
CPU time 1.11 seconds
Started Apr 02 12:39:41 PM PDT 24
Finished Apr 02 12:39:42 PM PDT 24
Peak memory 201764 kb
Host smart-379a00f2-1d87-458b-ba2d-43df4d142cb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345000065 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.3345000065
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3291707956
Short name T119
Test name
Test status
Simulation time 437613412 ps
CPU time 1.05 seconds
Started Apr 02 12:39:38 PM PDT 24
Finished Apr 02 12:39:39 PM PDT 24
Peak memory 201696 kb
Host smart-ea7ac568-4101-4225-b3f0-ec061ed6b0fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291707956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3291707956
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.182999502
Short name T814
Test name
Test status
Simulation time 546543877 ps
CPU time 0.82 seconds
Started Apr 02 12:39:29 PM PDT 24
Finished Apr 02 12:39:30 PM PDT 24
Peak memory 201720 kb
Host smart-8acd0a22-86be-4d18-b1d6-24d64f6242da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182999502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.182999502
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.747015891
Short name T887
Test name
Test status
Simulation time 2453988355 ps
CPU time 5.88 seconds
Started Apr 02 12:39:40 PM PDT 24
Finished Apr 02 12:39:46 PM PDT 24
Peak memory 201768 kb
Host smart-1590ece1-c336-4347-8788-9da8043c8965
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747015891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ct
rl_same_csr_outstanding.747015891
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.3648686855
Short name T858
Test name
Test status
Simulation time 584972676 ps
CPU time 2.19 seconds
Started Apr 02 12:39:33 PM PDT 24
Finished Apr 02 12:39:39 PM PDT 24
Peak memory 202024 kb
Host smart-013de7ba-e845-488b-b910-db6d2ea05c45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648686855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.3648686855
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.846232082
Short name T914
Test name
Test status
Simulation time 4673290889 ps
CPU time 11.36 seconds
Started Apr 02 12:39:29 PM PDT 24
Finished Apr 02 12:39:40 PM PDT 24
Peak memory 201948 kb
Host smart-3e2f073c-d213-419b-a378-a49c4afff289
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846232082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_int
g_err.846232082
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.3461823998
Short name T912
Test name
Test status
Simulation time 522178157 ps
CPU time 2.18 seconds
Started Apr 02 12:39:32 PM PDT 24
Finished Apr 02 12:39:39 PM PDT 24
Peak memory 201748 kb
Host smart-68c83154-28f3-408a-9b73-7599c129fae1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461823998 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.3461823998
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.941538915
Short name T115
Test name
Test status
Simulation time 380713274 ps
CPU time 0.99 seconds
Started Apr 02 12:39:29 PM PDT 24
Finished Apr 02 12:39:30 PM PDT 24
Peak memory 201668 kb
Host smart-56772c92-aa69-43d2-bf4f-4ee6eb9b3aef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941538915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.941538915
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.1636053269
Short name T819
Test name
Test status
Simulation time 405312685 ps
CPU time 0.86 seconds
Started Apr 02 12:39:37 PM PDT 24
Finished Apr 02 12:39:38 PM PDT 24
Peak memory 201712 kb
Host smart-4c4d52dc-c77f-4481-b48b-2b5a715537c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636053269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.1636053269
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.4052280375
Short name T849
Test name
Test status
Simulation time 3225554500 ps
CPU time 4.06 seconds
Started Apr 02 12:39:33 PM PDT 24
Finished Apr 02 12:39:41 PM PDT 24
Peak memory 201924 kb
Host smart-5a4bf462-3c4a-4f5f-81fa-965040d61d4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052280375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.4052280375
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3899523177
Short name T899
Test name
Test status
Simulation time 599284070 ps
CPU time 3.74 seconds
Started Apr 02 12:39:37 PM PDT 24
Finished Apr 02 12:39:41 PM PDT 24
Peak memory 218288 kb
Host smart-82250f5d-a1ff-41dc-904f-6659cb2a3448
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899523177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3899523177
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.914553365
Short name T50
Test name
Test status
Simulation time 7954738340 ps
CPU time 11.9 seconds
Started Apr 02 12:39:42 PM PDT 24
Finished Apr 02 12:39:54 PM PDT 24
Peak memory 201976 kb
Host smart-e05fafc0-1986-497c-b2c3-ab0359fac5cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914553365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_int
g_err.914553365
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.1688708269
Short name T332
Test name
Test status
Simulation time 185738690219 ps
CPU time 203.65 seconds
Started Apr 02 01:51:19 PM PDT 24
Finished Apr 02 01:54:43 PM PDT 24
Peak memory 201856 kb
Host smart-ae605f6a-ee76-4fd8-9287-523ecc8375ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688708269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1688708269
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.2152474521
Short name T148
Test name
Test status
Simulation time 491979018164 ps
CPU time 1060.62 seconds
Started Apr 02 01:51:18 PM PDT 24
Finished Apr 02 02:08:59 PM PDT 24
Peak memory 201868 kb
Host smart-2054b92d-c420-4997-aad2-3ec43065f947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152474521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.2152474521
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2495064507
Short name T607
Test name
Test status
Simulation time 489551550597 ps
CPU time 287.37 seconds
Started Apr 02 01:51:17 PM PDT 24
Finished Apr 02 01:56:05 PM PDT 24
Peak memory 201876 kb
Host smart-a9a20703-d89a-4ee0-b6d2-677c25bcda23
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495064507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2495064507
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.3059584299
Short name T326
Test name
Test status
Simulation time 329790796995 ps
CPU time 365.96 seconds
Started Apr 02 01:51:14 PM PDT 24
Finished Apr 02 01:57:20 PM PDT 24
Peak memory 201808 kb
Host smart-b4479d61-7bb4-4a8b-8847-84765ff7c427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059584299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3059584299
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2290173650
Short name T69
Test name
Test status
Simulation time 318548353294 ps
CPU time 184.03 seconds
Started Apr 02 01:51:17 PM PDT 24
Finished Apr 02 01:54:22 PM PDT 24
Peak memory 201968 kb
Host smart-37df5feb-2a44-4c62-aa3e-e9b5097a1ab7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290173650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2290173650
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3654030423
Short name T184
Test name
Test status
Simulation time 391523903785 ps
CPU time 120.29 seconds
Started Apr 02 01:51:19 PM PDT 24
Finished Apr 02 01:53:19 PM PDT 24
Peak memory 201896 kb
Host smart-ee4c755d-e83c-490a-b1ca-aa634ce098ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654030423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3654030423
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2778233747
Short name T461
Test name
Test status
Simulation time 592126385214 ps
CPU time 405.11 seconds
Started Apr 02 01:51:18 PM PDT 24
Finished Apr 02 01:58:04 PM PDT 24
Peak memory 201900 kb
Host smart-9a1cd414-f3d3-4038-8080-2da258778ebd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778233747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2778233747
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2615359595
Short name T350
Test name
Test status
Simulation time 90065543132 ps
CPU time 360.27 seconds
Started Apr 02 01:51:31 PM PDT 24
Finished Apr 02 01:57:31 PM PDT 24
Peak memory 202188 kb
Host smart-4a32ea25-73d4-4f25-a906-8c9559581b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615359595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2615359595
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2802329599
Short name T666
Test name
Test status
Simulation time 31062218780 ps
CPU time 6.97 seconds
Started Apr 02 01:51:24 PM PDT 24
Finished Apr 02 01:51:31 PM PDT 24
Peak memory 201632 kb
Host smart-1f1973bd-61a8-454a-8d13-e438fd1f96da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802329599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2802329599
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.1076449512
Short name T692
Test name
Test status
Simulation time 5149662425 ps
CPU time 3.71 seconds
Started Apr 02 01:51:18 PM PDT 24
Finished Apr 02 01:51:21 PM PDT 24
Peak memory 201712 kb
Host smart-6e618619-3b62-4e41-a134-067f84f1464d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076449512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.1076449512
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.1772068476
Short name T66
Test name
Test status
Simulation time 4418428337 ps
CPU time 6.34 seconds
Started Apr 02 01:51:24 PM PDT 24
Finished Apr 02 01:51:31 PM PDT 24
Peak memory 217304 kb
Host smart-1415d10b-4b80-4967-9e4b-ac3eae394b96
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772068476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.1772068476
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.506243320
Short name T726
Test name
Test status
Simulation time 6237694618 ps
CPU time 5.95 seconds
Started Apr 02 01:51:16 PM PDT 24
Finished Apr 02 01:51:23 PM PDT 24
Peak memory 201716 kb
Host smart-ecb49a58-f811-4831-8668-7aaa4510c7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506243320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.506243320
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.4163385088
Short name T592
Test name
Test status
Simulation time 203729008068 ps
CPU time 38.59 seconds
Started Apr 02 01:51:18 PM PDT 24
Finished Apr 02 01:51:57 PM PDT 24
Peak memory 201896 kb
Host smart-1c391c41-3859-4075-912d-98fa87bb184f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163385088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
4163385088
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2649529292
Short name T29
Test name
Test status
Simulation time 45078399061 ps
CPU time 122.64 seconds
Started Apr 02 01:51:18 PM PDT 24
Finished Apr 02 01:53:21 PM PDT 24
Peak memory 217760 kb
Host smart-8617b548-930c-473d-992d-8cb77307f583
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649529292 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2649529292
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3225173573
Short name T549
Test name
Test status
Simulation time 387322931 ps
CPU time 1.56 seconds
Started Apr 02 01:51:23 PM PDT 24
Finished Apr 02 01:51:25 PM PDT 24
Peak memory 201588 kb
Host smart-d2b17acc-a990-4f26-8e4b-123744c1411b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225173573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3225173573
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.4184839790
Short name T95
Test name
Test status
Simulation time 171337321420 ps
CPU time 377.73 seconds
Started Apr 02 01:51:21 PM PDT 24
Finished Apr 02 01:57:39 PM PDT 24
Peak memory 201884 kb
Host smart-cc2fd679-fa5a-4476-83fe-0a30e19eb126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184839790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.4184839790
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3349779852
Short name T377
Test name
Test status
Simulation time 164057778487 ps
CPU time 113.21 seconds
Started Apr 02 01:51:20 PM PDT 24
Finished Apr 02 01:53:13 PM PDT 24
Peak memory 201860 kb
Host smart-345f1284-3ae3-40a8-b743-e3901a2c64f2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349779852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3349779852
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2636063784
Short name T265
Test name
Test status
Simulation time 484632328229 ps
CPU time 1114.68 seconds
Started Apr 02 01:51:23 PM PDT 24
Finished Apr 02 02:09:58 PM PDT 24
Peak memory 201884 kb
Host smart-eb38eb83-ac1e-4ff3-8630-ae63698f7d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636063784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2636063784
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2087062255
Short name T513
Test name
Test status
Simulation time 166539458429 ps
CPU time 74.66 seconds
Started Apr 02 01:51:24 PM PDT 24
Finished Apr 02 01:52:39 PM PDT 24
Peak memory 201792 kb
Host smart-41cfe777-c545-428f-bf7b-a525630cad9f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087062255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2087062255
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.2706583016
Short name T94
Test name
Test status
Simulation time 553217820277 ps
CPU time 1306.04 seconds
Started Apr 02 01:51:21 PM PDT 24
Finished Apr 02 02:13:07 PM PDT 24
Peak memory 201852 kb
Host smart-569611a8-695c-4dd4-b278-1691c71003bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706583016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.2706583016
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1205478966
Short name T422
Test name
Test status
Simulation time 391547148432 ps
CPU time 452.08 seconds
Started Apr 02 01:51:24 PM PDT 24
Finished Apr 02 01:58:56 PM PDT 24
Peak memory 201848 kb
Host smart-18eff51a-0369-4d0a-b3d5-d6492ea5008c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205478966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1205478966
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1777870774
Short name T394
Test name
Test status
Simulation time 140272088500 ps
CPU time 658.05 seconds
Started Apr 02 01:51:20 PM PDT 24
Finished Apr 02 02:02:18 PM PDT 24
Peak memory 202240 kb
Host smart-418aaf4b-6e6b-406f-9d23-644bc3618657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777870774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1777870774
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2437725561
Short name T791
Test name
Test status
Simulation time 36595075843 ps
CPU time 23.48 seconds
Started Apr 02 01:51:21 PM PDT 24
Finished Apr 02 01:51:44 PM PDT 24
Peak memory 201620 kb
Host smart-f535378c-8496-4807-ba9a-5e8cd4765686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437725561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2437725561
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2088017401
Short name T442
Test name
Test status
Simulation time 4493656274 ps
CPU time 2.73 seconds
Started Apr 02 01:51:23 PM PDT 24
Finished Apr 02 01:51:26 PM PDT 24
Peak memory 201696 kb
Host smart-a4443a46-8544-4520-a1ec-ad2c256bf26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088017401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2088017401
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.2188165647
Short name T6
Test name
Test status
Simulation time 6064789127 ps
CPU time 7.8 seconds
Started Apr 02 01:51:19 PM PDT 24
Finished Apr 02 01:51:27 PM PDT 24
Peak memory 201616 kb
Host smart-5ca0ac84-5aa4-4164-a7e9-a500c0bd6f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188165647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2188165647
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.2534547861
Short name T769
Test name
Test status
Simulation time 458387871003 ps
CPU time 928.86 seconds
Started Apr 02 01:51:21 PM PDT 24
Finished Apr 02 02:06:50 PM PDT 24
Peak memory 202272 kb
Host smart-8844d1fc-35ce-4775-b698-99639cbdc7d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534547861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
2534547861
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.1588891099
Short name T271
Test name
Test status
Simulation time 79287079035 ps
CPU time 53.8 seconds
Started Apr 02 01:51:22 PM PDT 24
Finished Apr 02 01:52:16 PM PDT 24
Peak memory 210308 kb
Host smart-8366098d-0a40-481c-87a3-4f13bb81d17a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588891099 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.1588891099
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.1431835315
Short name T752
Test name
Test status
Simulation time 593251022 ps
CPU time 0.76 seconds
Started Apr 02 01:52:01 PM PDT 24
Finished Apr 02 01:52:02 PM PDT 24
Peak memory 201584 kb
Host smart-7a40301c-2057-4a1f-902e-2e70ba9b9f0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431835315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.1431835315
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.2183541239
Short name T322
Test name
Test status
Simulation time 498933872785 ps
CPU time 1101.91 seconds
Started Apr 02 01:51:59 PM PDT 24
Finished Apr 02 02:10:21 PM PDT 24
Peak memory 201900 kb
Host smart-3f631596-301d-4f73-95b5-8e112a3a6a94
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183541239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.2183541239
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.1999723185
Short name T624
Test name
Test status
Simulation time 351090196069 ps
CPU time 793.23 seconds
Started Apr 02 01:52:02 PM PDT 24
Finished Apr 02 02:05:15 PM PDT 24
Peak memory 201896 kb
Host smart-942d6fec-3ef1-45c4-8af3-eaebc714c856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999723185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.1999723185
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2827267754
Short name T599
Test name
Test status
Simulation time 327526084269 ps
CPU time 699.52 seconds
Started Apr 02 01:51:57 PM PDT 24
Finished Apr 02 02:03:37 PM PDT 24
Peak memory 201832 kb
Host smart-75e0db55-fc89-4a2b-b3fc-fd33991a7279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827267754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2827267754
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2221474433
Short name T167
Test name
Test status
Simulation time 325899346197 ps
CPU time 713.54 seconds
Started Apr 02 01:51:57 PM PDT 24
Finished Apr 02 02:03:51 PM PDT 24
Peak memory 201852 kb
Host smart-9e1e4196-acf3-4958-a03e-33b93d73d098
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221474433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2221474433
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.921400182
Short name T181
Test name
Test status
Simulation time 163047369409 ps
CPU time 395.93 seconds
Started Apr 02 01:51:57 PM PDT 24
Finished Apr 02 01:58:33 PM PDT 24
Peak memory 201868 kb
Host smart-89150a03-50cf-414b-a768-940c84e5150c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=921400182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe
d.921400182
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.4006742695
Short name T171
Test name
Test status
Simulation time 544103946864 ps
CPU time 224.33 seconds
Started Apr 02 01:51:57 PM PDT 24
Finished Apr 02 01:55:42 PM PDT 24
Peak memory 201880 kb
Host smart-3a892460-90fc-412b-9a8a-16a0ff71956d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006742695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.4006742695
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3785144572
Short name T462
Test name
Test status
Simulation time 204347333678 ps
CPU time 522.94 seconds
Started Apr 02 01:52:01 PM PDT 24
Finished Apr 02 02:00:44 PM PDT 24
Peak memory 201892 kb
Host smart-c94bffcb-87e0-449f-a8ee-ffe9b094ca80
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785144572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3785144572
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1377467341
Short name T511
Test name
Test status
Simulation time 119561007268 ps
CPU time 575.65 seconds
Started Apr 02 01:52:01 PM PDT 24
Finished Apr 02 02:01:37 PM PDT 24
Peak memory 202236 kb
Host smart-16c78868-3446-48f6-ab7f-a68154f2905d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377467341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1377467341
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1060293874
Short name T491
Test name
Test status
Simulation time 30687754919 ps
CPU time 21.83 seconds
Started Apr 02 01:52:03 PM PDT 24
Finished Apr 02 01:52:25 PM PDT 24
Peak memory 201684 kb
Host smart-b1d704a3-e58d-468a-a698-33bdb2d141b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060293874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1060293874
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2396808719
Short name T543
Test name
Test status
Simulation time 2763154787 ps
CPU time 1.26 seconds
Started Apr 02 01:52:00 PM PDT 24
Finished Apr 02 01:52:02 PM PDT 24
Peak memory 201692 kb
Host smart-82c72803-6e23-435f-8b19-e2188dca628d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396808719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2396808719
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.2685837355
Short name T131
Test name
Test status
Simulation time 5750195408 ps
CPU time 7.89 seconds
Started Apr 02 01:51:58 PM PDT 24
Finished Apr 02 01:52:06 PM PDT 24
Peak memory 201632 kb
Host smart-a412ef73-6bda-4d35-b281-98b68683b0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685837355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2685837355
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.2808574688
Short name T501
Test name
Test status
Simulation time 11865065057 ps
CPU time 7.5 seconds
Started Apr 02 01:52:00 PM PDT 24
Finished Apr 02 01:52:08 PM PDT 24
Peak memory 201936 kb
Host smart-7a185c04-0848-445c-a79d-7ed8080d9744
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808574688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.2808574688
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2764229142
Short name T622
Test name
Test status
Simulation time 147176543842 ps
CPU time 339.02 seconds
Started Apr 02 01:52:00 PM PDT 24
Finished Apr 02 01:57:39 PM PDT 24
Peak memory 210432 kb
Host smart-66f8721e-0d01-4380-8080-e0872d931f7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764229142 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2764229142
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.1497004383
Short name T93
Test name
Test status
Simulation time 420032915 ps
CPU time 1.49 seconds
Started Apr 02 01:52:08 PM PDT 24
Finished Apr 02 01:52:10 PM PDT 24
Peak memory 201520 kb
Host smart-86857382-83f8-41a2-88cd-a076f652376b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497004383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1497004383
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3007471778
Short name T317
Test name
Test status
Simulation time 356822012100 ps
CPU time 199.75 seconds
Started Apr 02 01:52:04 PM PDT 24
Finished Apr 02 01:55:24 PM PDT 24
Peak memory 201812 kb
Host smart-4b3c36c8-bdd5-4382-97f9-892de337b2a4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007471778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3007471778
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3183595721
Short name T268
Test name
Test status
Simulation time 325949755864 ps
CPU time 327.39 seconds
Started Apr 02 01:52:03 PM PDT 24
Finished Apr 02 01:57:31 PM PDT 24
Peak memory 201864 kb
Host smart-16c3d747-9003-4dc6-91e7-850c6345fa79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183595721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3183595721
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1764572025
Short name T674
Test name
Test status
Simulation time 332127688113 ps
CPU time 189.66 seconds
Started Apr 02 01:52:06 PM PDT 24
Finished Apr 02 01:55:16 PM PDT 24
Peak memory 201864 kb
Host smart-0343ecbf-5de9-4948-9892-4fb608bc2b7f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764572025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1764572025
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.972388584
Short name T165
Test name
Test status
Simulation time 164585723629 ps
CPU time 395.8 seconds
Started Apr 02 01:52:01 PM PDT 24
Finished Apr 02 01:58:37 PM PDT 24
Peak memory 201892 kb
Host smart-d91413f0-d1ca-4b7e-a18d-f456537d8f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972388584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.972388584
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2628856906
Short name T542
Test name
Test status
Simulation time 164351611717 ps
CPU time 69.1 seconds
Started Apr 02 01:52:02 PM PDT 24
Finished Apr 02 01:53:12 PM PDT 24
Peak memory 201848 kb
Host smart-3ed182be-cd6f-4be8-8004-f7d836aff915
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628856906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2628856906
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.316003448
Short name T331
Test name
Test status
Simulation time 546762737870 ps
CPU time 1284.27 seconds
Started Apr 02 01:52:03 PM PDT 24
Finished Apr 02 02:13:28 PM PDT 24
Peak memory 201984 kb
Host smart-62b1ead4-651c-42f9-bec0-d70e7448cf32
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316003448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_
wakeup.316003448
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.2334600050
Short name T485
Test name
Test status
Simulation time 585742050449 ps
CPU time 1402.09 seconds
Started Apr 02 01:52:04 PM PDT 24
Finished Apr 02 02:15:27 PM PDT 24
Peak memory 201864 kb
Host smart-615a5c5d-0d82-4ce0-bfe5-09c03fb43fc1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334600050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.2334600050
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3249352029
Short name T544
Test name
Test status
Simulation time 96177169778 ps
CPU time 538.56 seconds
Started Apr 02 01:52:06 PM PDT 24
Finished Apr 02 02:01:05 PM PDT 24
Peak memory 202240 kb
Host smart-aa0160a9-733c-445f-b50e-e0c8928d1375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249352029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3249352029
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.413603080
Short name T694
Test name
Test status
Simulation time 21910765722 ps
CPU time 52.34 seconds
Started Apr 02 01:52:06 PM PDT 24
Finished Apr 02 01:52:59 PM PDT 24
Peak memory 201688 kb
Host smart-f5a1f30a-d04d-404a-ab2f-d877ec0584b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413603080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.413603080
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1852306074
Short name T737
Test name
Test status
Simulation time 5295344231 ps
CPU time 6.65 seconds
Started Apr 02 01:52:04 PM PDT 24
Finished Apr 02 01:52:11 PM PDT 24
Peak memory 201700 kb
Host smart-577a0baa-6060-4e06-a362-545fc495084c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852306074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1852306074
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.62422104
Short name T788
Test name
Test status
Simulation time 5479490695 ps
CPU time 7.05 seconds
Started Apr 02 01:52:03 PM PDT 24
Finished Apr 02 01:52:10 PM PDT 24
Peak memory 201700 kb
Host smart-90b7dfe8-bdab-4dcd-8279-8335288bd872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62422104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.62422104
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.4083092743
Short name T286
Test name
Test status
Simulation time 515496461885 ps
CPU time 1065.46 seconds
Started Apr 02 01:52:11 PM PDT 24
Finished Apr 02 02:09:56 PM PDT 24
Peak memory 201852 kb
Host smart-0dae8f7a-5a04-4002-a541-11adc0592545
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083092743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.4083092743
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1805047319
Short name T308
Test name
Test status
Simulation time 305437571806 ps
CPU time 361.1 seconds
Started Apr 02 01:52:09 PM PDT 24
Finished Apr 02 01:58:10 PM PDT 24
Peak memory 211528 kb
Host smart-136a7e21-f2ae-4cb4-b495-66c1d54cdbaf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805047319 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.1805047319
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3222039135
Short name T680
Test name
Test status
Simulation time 394184889 ps
CPU time 0.79 seconds
Started Apr 02 01:52:14 PM PDT 24
Finished Apr 02 01:52:15 PM PDT 24
Peak memory 201580 kb
Host smart-97166190-494a-4094-94f8-c2b81c2338e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222039135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3222039135
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3673576414
Short name T782
Test name
Test status
Simulation time 337728362208 ps
CPU time 362.34 seconds
Started Apr 02 01:52:14 PM PDT 24
Finished Apr 02 01:58:16 PM PDT 24
Peak memory 201868 kb
Host smart-302a5547-cdb3-4657-9521-59eab9271f10
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673576414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3673576414
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.362078517
Short name T163
Test name
Test status
Simulation time 163803839192 ps
CPU time 343.13 seconds
Started Apr 02 01:52:11 PM PDT 24
Finished Apr 02 01:57:54 PM PDT 24
Peak memory 201976 kb
Host smart-b7e141b9-0011-47f5-a65d-474aaab0855a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362078517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.362078517
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.1311196030
Short name T201
Test name
Test status
Simulation time 500960608932 ps
CPU time 276.38 seconds
Started Apr 02 01:52:14 PM PDT 24
Finished Apr 02 01:56:50 PM PDT 24
Peak memory 201852 kb
Host smart-c8af69f4-1a78-45ff-87c9-c4853f79dca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311196030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1311196030
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.3367870098
Short name T562
Test name
Test status
Simulation time 331139882612 ps
CPU time 206.28 seconds
Started Apr 02 01:52:10 PM PDT 24
Finished Apr 02 01:55:37 PM PDT 24
Peak memory 201832 kb
Host smart-042ce6f0-385b-499b-a7b7-7f73c890a0b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367870098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.3367870098
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.3510934728
Short name T304
Test name
Test status
Simulation time 330941882848 ps
CPU time 774.17 seconds
Started Apr 02 01:52:07 PM PDT 24
Finished Apr 02 02:05:01 PM PDT 24
Peak memory 201956 kb
Host smart-074217d4-9bb2-4462-9887-8dd29c35aa63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510934728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3510934728
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1407866626
Short name T632
Test name
Test status
Simulation time 498657698356 ps
CPU time 1132.08 seconds
Started Apr 02 01:52:11 PM PDT 24
Finished Apr 02 02:11:04 PM PDT 24
Peak memory 201872 kb
Host smart-4e657f5f-99c9-4bd0-b37e-5d3a7c2c2ad9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407866626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1407866626
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1202471349
Short name T174
Test name
Test status
Simulation time 364937153171 ps
CPU time 405.54 seconds
Started Apr 02 01:52:10 PM PDT 24
Finished Apr 02 01:58:55 PM PDT 24
Peak memory 201860 kb
Host smart-2e593ccf-72a6-4dc4-abfa-d49a3b3e82f4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202471349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1202471349
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3868477202
Short name T424
Test name
Test status
Simulation time 402819241541 ps
CPU time 630.03 seconds
Started Apr 02 01:52:09 PM PDT 24
Finished Apr 02 02:02:40 PM PDT 24
Peak memory 201924 kb
Host smart-2b408771-7f99-4793-b1e0-e004a8ac0231
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868477202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.3868477202
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.2495754283
Short name T492
Test name
Test status
Simulation time 98144564872 ps
CPU time 357.06 seconds
Started Apr 02 01:52:12 PM PDT 24
Finished Apr 02 01:58:09 PM PDT 24
Peak memory 202196 kb
Host smart-1de08062-9be3-44d2-8d4c-23d809bacc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495754283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.2495754283
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3587890150
Short name T702
Test name
Test status
Simulation time 26373971079 ps
CPU time 28.57 seconds
Started Apr 02 01:52:11 PM PDT 24
Finished Apr 02 01:52:39 PM PDT 24
Peak memory 201712 kb
Host smart-81f2b264-48f6-4c08-adff-28afdb15508e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587890150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3587890150
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.3053320872
Short name T534
Test name
Test status
Simulation time 3032269525 ps
CPU time 2.4 seconds
Started Apr 02 01:52:14 PM PDT 24
Finished Apr 02 01:52:16 PM PDT 24
Peak memory 201712 kb
Host smart-43605257-4bce-46c2-982d-6369fe54a018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053320872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.3053320872
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.180087550
Short name T569
Test name
Test status
Simulation time 6105231381 ps
CPU time 2.87 seconds
Started Apr 02 01:52:07 PM PDT 24
Finished Apr 02 01:52:10 PM PDT 24
Peak memory 201592 kb
Host smart-a0491a20-a86a-4de3-8e70-d045c63c32ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180087550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.180087550
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.3069295929
Short name T374
Test name
Test status
Simulation time 507842533 ps
CPU time 0.97 seconds
Started Apr 02 01:52:32 PM PDT 24
Finished Apr 02 01:52:33 PM PDT 24
Peak memory 201608 kb
Host smart-b36e625e-2b87-4d28-ae3f-1949870d43c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069295929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3069295929
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3556856930
Short name T258
Test name
Test status
Simulation time 525267187726 ps
CPU time 447.08 seconds
Started Apr 02 01:52:20 PM PDT 24
Finished Apr 02 01:59:47 PM PDT 24
Peak memory 201908 kb
Host smart-c1f7884c-2b64-471a-828a-820e1ed4b5f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556856930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3556856930
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.2436797098
Short name T321
Test name
Test status
Simulation time 559410374908 ps
CPU time 455.63 seconds
Started Apr 02 01:52:19 PM PDT 24
Finished Apr 02 01:59:55 PM PDT 24
Peak memory 201932 kb
Host smart-c65b2cba-7793-4639-b131-349f37efdb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436797098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.2436797098
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3796408295
Short name T771
Test name
Test status
Simulation time 328871629129 ps
CPU time 205.79 seconds
Started Apr 02 01:52:18 PM PDT 24
Finished Apr 02 01:55:44 PM PDT 24
Peak memory 201924 kb
Host smart-344e4165-57b8-457d-a6bf-d05b785c8615
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796408295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3796408295
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.2748258501
Short name T267
Test name
Test status
Simulation time 339004804640 ps
CPU time 398.15 seconds
Started Apr 02 01:52:14 PM PDT 24
Finished Apr 02 01:58:53 PM PDT 24
Peak memory 201880 kb
Host smart-5445d933-f03d-43bf-ac68-acfa34bc5945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748258501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.2748258501
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.2325528397
Short name T720
Test name
Test status
Simulation time 164361712384 ps
CPU time 376.52 seconds
Started Apr 02 01:52:20 PM PDT 24
Finished Apr 02 01:58:37 PM PDT 24
Peak memory 201812 kb
Host smart-5ac0d2f1-15fa-4e52-935e-9e19a34a8522
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325528397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.2325528397
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.1461884567
Short name T275
Test name
Test status
Simulation time 185132747287 ps
CPU time 210.26 seconds
Started Apr 02 01:52:19 PM PDT 24
Finished Apr 02 01:55:51 PM PDT 24
Peak memory 201984 kb
Host smart-22b7dcc5-92d9-430f-96d9-ded0b13bd771
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461884567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.1461884567
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.4076096236
Short name T43
Test name
Test status
Simulation time 130609334952 ps
CPU time 418.23 seconds
Started Apr 02 01:52:25 PM PDT 24
Finished Apr 02 01:59:24 PM PDT 24
Peak memory 202236 kb
Host smart-9c4d2200-b810-4062-9896-e44e1c50ff8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076096236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.4076096236
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3918853695
Short name T630
Test name
Test status
Simulation time 47332619341 ps
CPU time 26.11 seconds
Started Apr 02 01:52:25 PM PDT 24
Finished Apr 02 01:52:52 PM PDT 24
Peak memory 201720 kb
Host smart-1b3a7958-74ed-4516-8171-f070c6f7a72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918853695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3918853695
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.370946194
Short name T676
Test name
Test status
Simulation time 4673822433 ps
CPU time 2.1 seconds
Started Apr 02 01:52:23 PM PDT 24
Finished Apr 02 01:52:25 PM PDT 24
Peak memory 201620 kb
Host smart-6d9bbc09-f0a6-4656-8a7b-23c826549286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370946194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.370946194
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.3226114313
Short name T766
Test name
Test status
Simulation time 5672488767 ps
CPU time 14.32 seconds
Started Apr 02 01:52:13 PM PDT 24
Finished Apr 02 01:52:27 PM PDT 24
Peak memory 201700 kb
Host smart-d8a3a552-1c08-4271-907a-53def35c38a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226114313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.3226114313
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3311475180
Short name T717
Test name
Test status
Simulation time 466462397371 ps
CPU time 466.32 seconds
Started Apr 02 01:52:23 PM PDT 24
Finished Apr 02 02:00:11 PM PDT 24
Peak memory 210524 kb
Host smart-9e114124-f909-4b22-abac-ea87ea838700
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311475180 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3311475180
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.1132837985
Short name T664
Test name
Test status
Simulation time 337135295 ps
CPU time 1.36 seconds
Started Apr 02 01:52:34 PM PDT 24
Finished Apr 02 01:52:35 PM PDT 24
Peak memory 201584 kb
Host smart-44c19a11-4848-4b63-8352-a72b2f668bf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132837985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1132837985
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.924433845
Short name T751
Test name
Test status
Simulation time 512149840939 ps
CPU time 321.59 seconds
Started Apr 02 01:52:30 PM PDT 24
Finished Apr 02 01:57:52 PM PDT 24
Peak memory 201832 kb
Host smart-23125344-7afe-4346-8d7b-44c6400a71a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924433845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.924433845
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.2108435730
Short name T773
Test name
Test status
Simulation time 335157544708 ps
CPU time 765.29 seconds
Started Apr 02 01:52:31 PM PDT 24
Finished Apr 02 02:05:17 PM PDT 24
Peak memory 201880 kb
Host smart-65b6e66d-26bc-4e53-b04f-d98955dcac91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108435730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2108435730
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.742363507
Short name T298
Test name
Test status
Simulation time 500932632179 ps
CPU time 1191.39 seconds
Started Apr 02 01:52:32 PM PDT 24
Finished Apr 02 02:12:24 PM PDT 24
Peak memory 201984 kb
Host smart-c0acf28b-3b10-4548-90c4-060ff31c8028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742363507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.742363507
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.3619350659
Short name T780
Test name
Test status
Simulation time 323411176990 ps
CPU time 745.69 seconds
Started Apr 02 01:52:28 PM PDT 24
Finished Apr 02 02:04:54 PM PDT 24
Peak memory 201872 kb
Host smart-20005fc6-3ce3-4bcc-b268-4c96d2393269
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619350659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.3619350659
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.1241845286
Short name T179
Test name
Test status
Simulation time 387232676072 ps
CPU time 234.49 seconds
Started Apr 02 01:52:32 PM PDT 24
Finished Apr 02 01:56:26 PM PDT 24
Peak memory 201896 kb
Host smart-5dd22eff-5473-4b14-ad78-3d7d44ed2e7c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241845286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.1241845286
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.186257810
Short name T366
Test name
Test status
Simulation time 603120628653 ps
CPU time 1226.3 seconds
Started Apr 02 01:52:32 PM PDT 24
Finished Apr 02 02:12:59 PM PDT 24
Peak memory 201892 kb
Host smart-423bddbf-e5f3-4d3d-bdb1-7be87d25dc8d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186257810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
adc_ctrl_filters_wakeup_fixed.186257810
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1150719240
Short name T671
Test name
Test status
Simulation time 99518951424 ps
CPU time 465.9 seconds
Started Apr 02 01:52:31 PM PDT 24
Finished Apr 02 02:00:17 PM PDT 24
Peak memory 202204 kb
Host smart-9bec09dd-7aaf-470e-aefc-9796f7a507dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150719240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1150719240
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.4067546565
Short name T583
Test name
Test status
Simulation time 40273575277 ps
CPU time 25.36 seconds
Started Apr 02 01:52:31 PM PDT 24
Finished Apr 02 01:52:57 PM PDT 24
Peak memory 201704 kb
Host smart-5850fbfc-057c-4b9b-a3ac-7431e2a91dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067546565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.4067546565
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.320344825
Short name T458
Test name
Test status
Simulation time 4018249126 ps
CPU time 10.8 seconds
Started Apr 02 01:52:31 PM PDT 24
Finished Apr 02 01:52:42 PM PDT 24
Peak memory 201648 kb
Host smart-7d97ae47-9d73-4e9b-a518-2d58565df3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320344825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.320344825
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2462116681
Short name T559
Test name
Test status
Simulation time 5974941312 ps
CPU time 9.37 seconds
Started Apr 02 01:52:29 PM PDT 24
Finished Apr 02 01:52:38 PM PDT 24
Peak memory 201620 kb
Host smart-64256fa7-c52b-4e4b-900f-392e4191d47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462116681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2462116681
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.1933905890
Short name T636
Test name
Test status
Simulation time 519706578241 ps
CPU time 1685.65 seconds
Started Apr 02 01:52:35 PM PDT 24
Finished Apr 02 02:20:41 PM PDT 24
Peak memory 212920 kb
Host smart-7fac0bd0-e56a-446f-97ab-fdae8c9d9f40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933905890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.1933905890
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2134658162
Short name T239
Test name
Test status
Simulation time 955583897824 ps
CPU time 497.68 seconds
Started Apr 02 01:52:35 PM PDT 24
Finished Apr 02 02:00:53 PM PDT 24
Peak memory 210508 kb
Host smart-e6daa841-bacb-4aca-8afa-274ca16b9ff7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134658162 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.2134658162
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.140337974
Short name T380
Test name
Test status
Simulation time 352462203 ps
CPU time 0.73 seconds
Started Apr 02 01:52:46 PM PDT 24
Finished Apr 02 01:52:47 PM PDT 24
Peak memory 201544 kb
Host smart-8580b4f8-34da-45d8-b7ce-71718bb04a55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140337974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.140337974
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.1667274697
Short name T770
Test name
Test status
Simulation time 559496573638 ps
CPU time 256.47 seconds
Started Apr 02 01:52:41 PM PDT 24
Finished Apr 02 01:56:58 PM PDT 24
Peak memory 201948 kb
Host smart-6294acd9-4e06-42f8-8cba-bf02250c5964
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667274697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.1667274697
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.1235946185
Short name T693
Test name
Test status
Simulation time 550043883843 ps
CPU time 714.17 seconds
Started Apr 02 01:52:43 PM PDT 24
Finished Apr 02 02:04:37 PM PDT 24
Peak memory 201860 kb
Host smart-9e4a3528-c2eb-482b-ab96-e8402ebc5e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235946185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1235946185
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.4274657477
Short name T617
Test name
Test status
Simulation time 162904920286 ps
CPU time 181.11 seconds
Started Apr 02 01:52:38 PM PDT 24
Finished Apr 02 01:55:39 PM PDT 24
Peak memory 201832 kb
Host smart-2ae3769b-e7b3-43c0-a789-d4356ae6ff2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274657477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.4274657477
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3258023938
Short name T399
Test name
Test status
Simulation time 325895937053 ps
CPU time 205.63 seconds
Started Apr 02 01:52:40 PM PDT 24
Finished Apr 02 01:56:05 PM PDT 24
Peak memory 201828 kb
Host smart-b6ea1c06-5902-4429-8acc-23691c831f30
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258023938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3258023938
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3715618732
Short name T723
Test name
Test status
Simulation time 166710569051 ps
CPU time 379.82 seconds
Started Apr 02 01:52:35 PM PDT 24
Finished Apr 02 01:58:55 PM PDT 24
Peak memory 201856 kb
Host smart-751ee83f-d406-4757-b4ff-d3174722dd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715618732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3715618732
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2427715173
Short name T359
Test name
Test status
Simulation time 159308364616 ps
CPU time 196.23 seconds
Started Apr 02 01:52:39 PM PDT 24
Finished Apr 02 01:55:56 PM PDT 24
Peak memory 201780 kb
Host smart-e84578b3-d679-4e91-828f-5bec18da839a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427715173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2427715173
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.144813321
Short name T309
Test name
Test status
Simulation time 504722723984 ps
CPU time 144.15 seconds
Started Apr 02 01:52:38 PM PDT 24
Finished Apr 02 01:55:02 PM PDT 24
Peak memory 201884 kb
Host smart-1372d839-bf5f-48a8-81d0-90531fac2626
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144813321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.144813321
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.4135514792
Short name T397
Test name
Test status
Simulation time 201924658272 ps
CPU time 491.95 seconds
Started Apr 02 01:52:42 PM PDT 24
Finished Apr 02 02:00:54 PM PDT 24
Peak memory 201808 kb
Host smart-5035777e-64c6-43ec-9778-42ae0c048642
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135514792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.4135514792
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.2325597817
Short name T576
Test name
Test status
Simulation time 123219776670 ps
CPU time 686.98 seconds
Started Apr 02 01:52:44 PM PDT 24
Finished Apr 02 02:04:11 PM PDT 24
Peak memory 202080 kb
Host smart-c7eb5964-8dac-4ad4-890a-ba900fb13adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325597817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.2325597817
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1443733377
Short name T478
Test name
Test status
Simulation time 25405882303 ps
CPU time 57.13 seconds
Started Apr 02 01:52:41 PM PDT 24
Finished Apr 02 01:53:39 PM PDT 24
Peak memory 201612 kb
Host smart-2156571a-12c8-4a8d-9585-5d4853f42abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443733377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1443733377
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.596552251
Short name T747
Test name
Test status
Simulation time 5066256740 ps
CPU time 2.13 seconds
Started Apr 02 01:52:41 PM PDT 24
Finished Apr 02 01:52:44 PM PDT 24
Peak memory 201700 kb
Host smart-29427f1b-7419-462e-8d5f-8f8423d40918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596552251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.596552251
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.948649814
Short name T486
Test name
Test status
Simulation time 5973928558 ps
CPU time 13.84 seconds
Started Apr 02 01:52:34 PM PDT 24
Finished Apr 02 01:52:48 PM PDT 24
Peak memory 201676 kb
Host smart-c48dcd24-f546-4431-8470-bc842c72c7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948649814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.948649814
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1609555196
Short name T573
Test name
Test status
Simulation time 315610667249 ps
CPU time 246.4 seconds
Started Apr 02 01:52:44 PM PDT 24
Finished Apr 02 01:56:51 PM PDT 24
Peak memory 218016 kb
Host smart-ec0c1f7b-78b4-4d2f-a3f0-d206a4214853
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609555196 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1609555196
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1278521308
Short name T437
Test name
Test status
Simulation time 514555676 ps
CPU time 1.72 seconds
Started Apr 02 01:53:07 PM PDT 24
Finished Apr 02 01:53:09 PM PDT 24
Peak memory 201588 kb
Host smart-65a23478-327f-45a7-b1a7-891edfe9f7c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278521308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1278521308
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.4188812628
Short name T337
Test name
Test status
Simulation time 160910335803 ps
CPU time 48.96 seconds
Started Apr 02 01:52:54 PM PDT 24
Finished Apr 02 01:53:43 PM PDT 24
Peak memory 201908 kb
Host smart-8c059f5b-cb88-4b96-8880-96c09727984c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188812628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.4188812628
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3151038213
Short name T306
Test name
Test status
Simulation time 326902984981 ps
CPU time 735.07 seconds
Started Apr 02 01:52:49 PM PDT 24
Finished Apr 02 02:05:04 PM PDT 24
Peak memory 201796 kb
Host smart-0a055058-a10d-46cf-be8b-dbe1e2b51667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151038213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3151038213
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3444120978
Short name T202
Test name
Test status
Simulation time 333905965096 ps
CPU time 798.21 seconds
Started Apr 02 01:52:48 PM PDT 24
Finished Apr 02 02:06:07 PM PDT 24
Peak memory 201844 kb
Host smart-ae887347-c090-40c4-84aa-2c9567ede6a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444120978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.3444120978
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2074273496
Short name T152
Test name
Test status
Simulation time 495547432734 ps
CPU time 559.55 seconds
Started Apr 02 01:52:45 PM PDT 24
Finished Apr 02 02:02:05 PM PDT 24
Peak memory 201800 kb
Host smart-758dc5cc-9b5d-49b3-810e-1e02a118790b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074273496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2074273496
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1260076466
Short name T1
Test name
Test status
Simulation time 158471472535 ps
CPU time 368.86 seconds
Started Apr 02 01:52:49 PM PDT 24
Finished Apr 02 01:58:58 PM PDT 24
Peak memory 201856 kb
Host smart-a740d3b4-5749-4545-9141-1e45a6308fd3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260076466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1260076466
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.3176230087
Short name T198
Test name
Test status
Simulation time 528533478809 ps
CPU time 307.17 seconds
Started Apr 02 01:52:51 PM PDT 24
Finished Apr 02 01:57:59 PM PDT 24
Peak memory 201900 kb
Host smart-1dfc647e-5a9f-43ab-a38d-157612fc4a69
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176230087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.3176230087
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.789594429
Short name T564
Test name
Test status
Simulation time 605943575960 ps
CPU time 1413.37 seconds
Started Apr 02 01:52:55 PM PDT 24
Finished Apr 02 02:16:29 PM PDT 24
Peak memory 201884 kb
Host smart-80616841-981a-4255-abb5-83e538b39137
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789594429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
adc_ctrl_filters_wakeup_fixed.789594429
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1218171224
Short name T591
Test name
Test status
Simulation time 33394198541 ps
CPU time 20.78 seconds
Started Apr 02 01:52:57 PM PDT 24
Finished Apr 02 01:53:18 PM PDT 24
Peak memory 201716 kb
Host smart-1683ee8c-7309-4354-b0a9-53eaabe4f673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218171224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1218171224
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.1439688015
Short name T512
Test name
Test status
Simulation time 3648322650 ps
CPU time 8.74 seconds
Started Apr 02 01:53:00 PM PDT 24
Finished Apr 02 01:53:10 PM PDT 24
Peak memory 201608 kb
Host smart-52d0e02d-00a5-44eb-967b-82dd548d63cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439688015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1439688015
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.2206272570
Short name T648
Test name
Test status
Simulation time 6165144521 ps
CPU time 4.4 seconds
Started Apr 02 01:52:44 PM PDT 24
Finished Apr 02 01:52:49 PM PDT 24
Peak memory 201700 kb
Host smart-da38ed95-c3e6-4fe5-8aa3-09f3e7382e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206272570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2206272570
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.3108807186
Short name T669
Test name
Test status
Simulation time 294206786000 ps
CPU time 1102.26 seconds
Started Apr 02 01:53:08 PM PDT 24
Finished Apr 02 02:11:31 PM PDT 24
Peak memory 202264 kb
Host smart-d75af578-5685-4171-9eff-6101f58a73d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108807186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.3108807186
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1050538538
Short name T21
Test name
Test status
Simulation time 243328468872 ps
CPU time 233.16 seconds
Started Apr 02 01:53:02 PM PDT 24
Finished Apr 02 01:56:55 PM PDT 24
Peak memory 210452 kb
Host smart-91a0ffc9-7cea-4c4d-a1b7-599d80e6d10f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050538538 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.1050538538
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3819423797
Short name T482
Test name
Test status
Simulation time 478608048 ps
CPU time 0.83 seconds
Started Apr 02 01:53:23 PM PDT 24
Finished Apr 02 01:53:24 PM PDT 24
Peak memory 201568 kb
Host smart-6ae0c989-6764-4ce5-8c70-eb18a52422a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819423797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3819423797
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1562651839
Short name T291
Test name
Test status
Simulation time 334000394806 ps
CPU time 94.86 seconds
Started Apr 02 01:53:17 PM PDT 24
Finished Apr 02 01:54:52 PM PDT 24
Peak memory 201896 kb
Host smart-e9a8ec31-578e-4cde-94c3-84e1f6241721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562651839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1562651839
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1591045967
Short name T376
Test name
Test status
Simulation time 336646728404 ps
CPU time 797.32 seconds
Started Apr 02 01:53:10 PM PDT 24
Finished Apr 02 02:06:28 PM PDT 24
Peak memory 201844 kb
Host smart-6ffef45d-2cf6-488e-9255-4ac802501e20
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591045967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1591045967
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.207010245
Short name T484
Test name
Test status
Simulation time 493374299373 ps
CPU time 285.11 seconds
Started Apr 02 01:53:08 PM PDT 24
Finished Apr 02 01:57:53 PM PDT 24
Peak memory 201828 kb
Host smart-88c154c8-159e-410b-a198-15a544910ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207010245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.207010245
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1592974001
Short name T536
Test name
Test status
Simulation time 324634452864 ps
CPU time 81.08 seconds
Started Apr 02 01:53:08 PM PDT 24
Finished Apr 02 01:54:29 PM PDT 24
Peak memory 201848 kb
Host smart-f09daafe-b6fc-48b3-8e5e-315cc6340fd3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592974001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.1592974001
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.1649342820
Short name T762
Test name
Test status
Simulation time 175187510440 ps
CPU time 102.11 seconds
Started Apr 02 01:53:10 PM PDT 24
Finished Apr 02 01:54:52 PM PDT 24
Peak memory 201968 kb
Host smart-9e5d87ef-3662-4d8c-b545-c07dfa4382b1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649342820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.1649342820
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.557516899
Short name T489
Test name
Test status
Simulation time 604479469684 ps
CPU time 246.34 seconds
Started Apr 02 01:53:12 PM PDT 24
Finished Apr 02 01:57:18 PM PDT 24
Peak memory 201980 kb
Host smart-711b5099-b3e6-473c-bf89-7072b7f96a14
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557516899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.557516899
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.1671625656
Short name T38
Test name
Test status
Simulation time 70720996426 ps
CPU time 254.19 seconds
Started Apr 02 01:53:21 PM PDT 24
Finished Apr 02 01:57:36 PM PDT 24
Peak memory 202204 kb
Host smart-567d1a28-6917-49df-97fa-dde85f62ce86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671625656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1671625656
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.874023672
Short name T560
Test name
Test status
Simulation time 36365054313 ps
CPU time 33.07 seconds
Started Apr 02 01:53:22 PM PDT 24
Finished Apr 02 01:53:56 PM PDT 24
Peak memory 201668 kb
Host smart-eb5f6620-4884-4f3d-b732-c87a5d450ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874023672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.874023672
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.66371445
Short name T713
Test name
Test status
Simulation time 5190280678 ps
CPU time 12.75 seconds
Started Apr 02 01:53:16 PM PDT 24
Finished Apr 02 01:53:29 PM PDT 24
Peak memory 201628 kb
Host smart-1b6b1f67-abe9-47b8-8fa8-ed6af626265c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66371445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.66371445
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3417496025
Short name T82
Test name
Test status
Simulation time 5729092002 ps
CPU time 15.65 seconds
Started Apr 02 01:53:08 PM PDT 24
Finished Apr 02 01:53:24 PM PDT 24
Peak memory 201700 kb
Host smart-8f3a4b50-aae7-4c33-86fc-13a698963434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417496025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3417496025
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.16262318
Short name T678
Test name
Test status
Simulation time 94915552395 ps
CPU time 388.45 seconds
Started Apr 02 01:53:25 PM PDT 24
Finished Apr 02 01:59:53 PM PDT 24
Peak memory 210392 kb
Host smart-c0a62dd9-1425-4516-9e02-bfd75725765d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16262318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all.16262318
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1955680090
Short name T786
Test name
Test status
Simulation time 56497076024 ps
CPU time 156.4 seconds
Started Apr 02 01:53:20 PM PDT 24
Finished Apr 02 01:55:57 PM PDT 24
Peak memory 210460 kb
Host smart-eb77f56e-55f4-45a4-96f4-703fbf59c7f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955680090 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1955680090
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.4234201071
Short name T765
Test name
Test status
Simulation time 346424038 ps
CPU time 1.34 seconds
Started Apr 02 01:53:42 PM PDT 24
Finished Apr 02 01:53:43 PM PDT 24
Peak memory 201588 kb
Host smart-694d83dc-5967-4947-b258-7f49e99e479f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234201071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.4234201071
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.3199147705
Short name T130
Test name
Test status
Simulation time 217275830619 ps
CPU time 128.89 seconds
Started Apr 02 01:53:33 PM PDT 24
Finished Apr 02 01:55:43 PM PDT 24
Peak memory 201888 kb
Host smart-f5e154eb-5a48-4f16-9abd-12d430d31648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199147705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.3199147705
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.973758383
Short name T251
Test name
Test status
Simulation time 491217636878 ps
CPU time 1101.04 seconds
Started Apr 02 01:53:28 PM PDT 24
Finished Apr 02 02:11:49 PM PDT 24
Peak memory 201792 kb
Host smart-a292350f-2e44-42af-8c47-395561edfdc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973758383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.973758383
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1241751937
Short name T468
Test name
Test status
Simulation time 498597939618 ps
CPU time 982.24 seconds
Started Apr 02 01:53:28 PM PDT 24
Finished Apr 02 02:09:50 PM PDT 24
Peak memory 201836 kb
Host smart-e30bdea4-06ae-436e-9cfb-8f615da20247
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241751937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1241751937
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.3261209876
Short name T430
Test name
Test status
Simulation time 168192277798 ps
CPU time 389.98 seconds
Started Apr 02 01:53:29 PM PDT 24
Finished Apr 02 01:59:59 PM PDT 24
Peak memory 201948 kb
Host smart-eee0a211-ad7a-4ecd-a176-9c1059522f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261209876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3261209876
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2845170533
Short name T466
Test name
Test status
Simulation time 331843356003 ps
CPU time 329.52 seconds
Started Apr 02 01:53:28 PM PDT 24
Finished Apr 02 01:58:57 PM PDT 24
Peak memory 201788 kb
Host smart-b9c0c6ca-a59e-4aa5-bfd3-bce07961ea22
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845170533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2845170533
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.2700598208
Short name T194
Test name
Test status
Simulation time 348088243144 ps
CPU time 212.37 seconds
Started Apr 02 01:53:26 PM PDT 24
Finished Apr 02 01:56:59 PM PDT 24
Peak memory 201996 kb
Host smart-f5d78cbe-a8ea-4a1a-9338-773940c775d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700598208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.2700598208
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.3600407396
Short name T750
Test name
Test status
Simulation time 406358693884 ps
CPU time 240.86 seconds
Started Apr 02 01:53:29 PM PDT 24
Finished Apr 02 01:57:30 PM PDT 24
Peak memory 201884 kb
Host smart-3f1a332b-0442-489d-acc3-8c5ac969991a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600407396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.3600407396
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.561027741
Short name T753
Test name
Test status
Simulation time 107727146895 ps
CPU time 310.26 seconds
Started Apr 02 01:53:40 PM PDT 24
Finished Apr 02 01:58:50 PM PDT 24
Peak memory 202216 kb
Host smart-ad009be1-0100-4eed-b689-86f17da85469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561027741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.561027741
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2468868316
Short name T432
Test name
Test status
Simulation time 23670505986 ps
CPU time 54.94 seconds
Started Apr 02 01:53:39 PM PDT 24
Finished Apr 02 01:54:34 PM PDT 24
Peak memory 201684 kb
Host smart-7512003e-5eb4-4d38-9deb-23feaba62e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468868316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2468868316
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2233495732
Short name T647
Test name
Test status
Simulation time 4048620568 ps
CPU time 1.95 seconds
Started Apr 02 01:53:35 PM PDT 24
Finished Apr 02 01:53:37 PM PDT 24
Peak memory 201696 kb
Host smart-76c18d95-942f-4e7a-a671-ef8ee165d116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233495732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2233495732
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.3416302339
Short name T571
Test name
Test status
Simulation time 5857613675 ps
CPU time 13.65 seconds
Started Apr 02 01:53:23 PM PDT 24
Finished Apr 02 01:53:37 PM PDT 24
Peak memory 201716 kb
Host smart-bcf2cb32-9e88-4c86-8faa-fd5298a3871a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416302339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3416302339
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.2291287460
Short name T18
Test name
Test status
Simulation time 223940906961 ps
CPU time 244.02 seconds
Started Apr 02 01:53:41 PM PDT 24
Finished Apr 02 01:57:45 PM PDT 24
Peak memory 210496 kb
Host smart-4682ba4f-32c4-4d18-a5fb-bae50df480d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291287460 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.2291287460
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2574513334
Short name T640
Test name
Test status
Simulation time 585525233 ps
CPU time 0.71 seconds
Started Apr 02 01:53:59 PM PDT 24
Finished Apr 02 01:54:00 PM PDT 24
Peak memory 201572 kb
Host smart-e0f2fbea-fa73-438a-b97d-e7413c21d551
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574513334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2574513334
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2831631714
Short name T344
Test name
Test status
Simulation time 327604696431 ps
CPU time 211.88 seconds
Started Apr 02 01:53:46 PM PDT 24
Finished Apr 02 01:57:18 PM PDT 24
Peak memory 201864 kb
Host smart-4742972c-1c92-4420-b34b-53e28aae68ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831631714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2831631714
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2924381358
Short name T386
Test name
Test status
Simulation time 160558161177 ps
CPU time 359.2 seconds
Started Apr 02 01:53:49 PM PDT 24
Finished Apr 02 01:59:49 PM PDT 24
Peak memory 201868 kb
Host smart-eb320757-aa26-475c-9b1a-61d3d6c1fddc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924381358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2924381358
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.282842530
Short name T488
Test name
Test status
Simulation time 325120195805 ps
CPU time 384.26 seconds
Started Apr 02 01:53:44 PM PDT 24
Finished Apr 02 02:00:08 PM PDT 24
Peak memory 201892 kb
Host smart-8dedf334-48bf-4fd9-90df-040788c7dafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282842530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.282842530
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1916184190
Short name T419
Test name
Test status
Simulation time 329210140979 ps
CPU time 115.86 seconds
Started Apr 02 01:53:47 PM PDT 24
Finished Apr 02 01:55:43 PM PDT 24
Peak memory 201864 kb
Host smart-c4685cd4-f661-4272-b68a-e23e0204f157
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916184190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1916184190
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2682388767
Short name T247
Test name
Test status
Simulation time 401068319938 ps
CPU time 856.8 seconds
Started Apr 02 01:53:50 PM PDT 24
Finished Apr 02 02:08:08 PM PDT 24
Peak memory 201896 kb
Host smart-d726a886-e653-4a69-997a-199c7caec90b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682388767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2682388767
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3460914812
Short name T643
Test name
Test status
Simulation time 603755104326 ps
CPU time 1314.8 seconds
Started Apr 02 01:53:53 PM PDT 24
Finished Apr 02 02:15:48 PM PDT 24
Peak memory 201896 kb
Host smart-129f010c-262c-4308-a9c6-6f173c404952
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460914812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3460914812
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.781887218
Short name T353
Test name
Test status
Simulation time 116178632659 ps
CPU time 532.9 seconds
Started Apr 02 01:53:56 PM PDT 24
Finished Apr 02 02:02:49 PM PDT 24
Peak memory 202232 kb
Host smart-40c22bdf-5c7e-40fa-933d-34636da09eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781887218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.781887218
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2763920893
Short name T371
Test name
Test status
Simulation time 47748712036 ps
CPU time 59.23 seconds
Started Apr 02 01:53:56 PM PDT 24
Finished Apr 02 01:54:55 PM PDT 24
Peak memory 201696 kb
Host smart-207a2202-88b1-4518-ad0c-97e73e7d8efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763920893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2763920893
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3494976053
Short name T133
Test name
Test status
Simulation time 4874627171 ps
CPU time 2.54 seconds
Started Apr 02 01:53:54 PM PDT 24
Finished Apr 02 01:53:56 PM PDT 24
Peak memory 201716 kb
Host smart-209b4094-5e67-453d-96e4-9eb2e6b496f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494976053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3494976053
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.832866162
Short name T379
Test name
Test status
Simulation time 5926968772 ps
CPU time 13.45 seconds
Started Apr 02 01:53:44 PM PDT 24
Finished Apr 02 01:53:58 PM PDT 24
Peak memory 201692 kb
Host smart-4baa10dd-15c8-475b-b80d-8d34e47f2232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832866162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.832866162
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.465051151
Short name T262
Test name
Test status
Simulation time 485346602161 ps
CPU time 308.66 seconds
Started Apr 02 01:53:59 PM PDT 24
Finished Apr 02 01:59:07 PM PDT 24
Peak memory 201860 kb
Host smart-b9a06a58-e5e7-4ff3-912a-713aa60b63bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465051151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
465051151
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1920927553
Short name T324
Test name
Test status
Simulation time 259230735895 ps
CPU time 342.9 seconds
Started Apr 02 01:53:56 PM PDT 24
Finished Apr 02 01:59:39 PM PDT 24
Peak memory 218156 kb
Host smart-e23a0947-5c88-4fda-ab6c-e44a06f1cef3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920927553 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1920927553
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1503709830
Short name T744
Test name
Test status
Simulation time 385561323 ps
CPU time 1.53 seconds
Started Apr 02 01:51:23 PM PDT 24
Finished Apr 02 01:51:25 PM PDT 24
Peak memory 201584 kb
Host smart-7ef63c46-b286-4a6c-a304-9bd65bb6b5da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503709830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1503709830
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.4108513893
Short name T722
Test name
Test status
Simulation time 512649660420 ps
CPU time 296.56 seconds
Started Apr 02 01:51:23 PM PDT 24
Finished Apr 02 01:56:20 PM PDT 24
Peak memory 201792 kb
Host smart-cd94eb5d-7f23-41fd-baeb-a54aa62b78c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108513893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.4108513893
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2106137083
Short name T295
Test name
Test status
Simulation time 167396335175 ps
CPU time 41.33 seconds
Started Apr 02 01:51:20 PM PDT 24
Finished Apr 02 01:52:02 PM PDT 24
Peak memory 201972 kb
Host smart-cdb65e26-357a-415f-ac87-202c9ea45f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106137083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2106137083
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2108333676
Short name T528
Test name
Test status
Simulation time 493032759115 ps
CPU time 602.46 seconds
Started Apr 02 01:51:23 PM PDT 24
Finished Apr 02 02:01:26 PM PDT 24
Peak memory 201880 kb
Host smart-4925534b-0f8e-4311-97f6-4dfc3a28c9d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108333676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2108333676
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.3471688090
Short name T305
Test name
Test status
Simulation time 325853575277 ps
CPU time 213.1 seconds
Started Apr 02 01:51:23 PM PDT 24
Finished Apr 02 01:54:56 PM PDT 24
Peak memory 201896 kb
Host smart-53b197e7-6692-409a-b2e5-ab1510cc70d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471688090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.3471688090
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2009896757
Short name T616
Test name
Test status
Simulation time 329728643302 ps
CPU time 777.14 seconds
Started Apr 02 01:51:20 PM PDT 24
Finished Apr 02 02:04:17 PM PDT 24
Peak memory 201812 kb
Host smart-2c1faae1-1858-4a95-b631-480d46f3cc33
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009896757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.2009896757
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1465899204
Short name T668
Test name
Test status
Simulation time 652327076561 ps
CPU time 319.95 seconds
Started Apr 02 01:51:23 PM PDT 24
Finished Apr 02 01:56:43 PM PDT 24
Peak memory 201808 kb
Host smart-cb6f4f73-a5ea-4e1a-aac0-82adbfd95bdf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465899204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1465899204
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.28778942
Short name T423
Test name
Test status
Simulation time 402374764426 ps
CPU time 231.03 seconds
Started Apr 02 01:51:26 PM PDT 24
Finished Apr 02 01:55:17 PM PDT 24
Peak memory 201780 kb
Host smart-0aa2fa5b-755b-443f-929c-304165359132
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28778942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.ad
c_ctrl_filters_wakeup_fixed.28778942
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3263672002
Short name T532
Test name
Test status
Simulation time 124687146431 ps
CPU time 493.26 seconds
Started Apr 02 01:51:25 PM PDT 24
Finished Apr 02 01:59:39 PM PDT 24
Peak memory 202152 kb
Host smart-e3cb3c39-842b-4f64-938e-48b4607a4dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263672002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3263672002
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2880838058
Short name T677
Test name
Test status
Simulation time 36385549611 ps
CPU time 39.68 seconds
Started Apr 02 01:51:25 PM PDT 24
Finished Apr 02 01:52:05 PM PDT 24
Peak memory 201672 kb
Host smart-5112719f-935a-4683-b680-021e8c020fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880838058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2880838058
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3802541688
Short name T134
Test name
Test status
Simulation time 4914280368 ps
CPU time 3.34 seconds
Started Apr 02 01:51:22 PM PDT 24
Finished Apr 02 01:51:25 PM PDT 24
Peak memory 201688 kb
Host smart-38c72247-6f72-4379-b1eb-306f79a259bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802541688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3802541688
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2798428446
Short name T67
Test name
Test status
Simulation time 4050553486 ps
CPU time 2.75 seconds
Started Apr 02 01:51:25 PM PDT 24
Finished Apr 02 01:51:28 PM PDT 24
Peak memory 217368 kb
Host smart-62439b68-e94f-43b7-bf7b-5f602d2e878e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798428446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2798428446
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.281849634
Short name T436
Test name
Test status
Simulation time 6094567306 ps
CPU time 16.52 seconds
Started Apr 02 01:51:20 PM PDT 24
Finished Apr 02 01:51:37 PM PDT 24
Peak memory 201724 kb
Host smart-44ba3bd9-5784-4e0b-af96-acccdcfd491f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281849634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.281849634
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.4110311822
Short name T685
Test name
Test status
Simulation time 670599062140 ps
CPU time 1524.83 seconds
Started Apr 02 01:51:23 PM PDT 24
Finished Apr 02 02:16:48 PM PDT 24
Peak memory 201880 kb
Host smart-24c5fc9b-62d8-44db-ad0e-6bfd7e0c03be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110311822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
4110311822
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3673373561
Short name T77
Test name
Test status
Simulation time 325866495024 ps
CPU time 314.78 seconds
Started Apr 02 01:51:24 PM PDT 24
Finished Apr 02 01:56:39 PM PDT 24
Peak memory 210612 kb
Host smart-00fd8b3a-d473-420f-a8f7-4b26b4d5a172
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673373561 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3673373561
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2515476155
Short name T623
Test name
Test status
Simulation time 316316923 ps
CPU time 1.41 seconds
Started Apr 02 01:54:14 PM PDT 24
Finished Apr 02 01:54:15 PM PDT 24
Peak memory 201536 kb
Host smart-2ea00286-7a2b-40f5-b889-87fdad548ded
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515476155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2515476155
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2541143925
Short name T281
Test name
Test status
Simulation time 346771927659 ps
CPU time 842.96 seconds
Started Apr 02 01:54:11 PM PDT 24
Finished Apr 02 02:08:15 PM PDT 24
Peak memory 201804 kb
Host smart-d97c42da-7cf6-4d5d-9b20-278357183a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541143925 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2541143925
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.4088901373
Short name T631
Test name
Test status
Simulation time 333964404140 ps
CPU time 186.07 seconds
Started Apr 02 01:54:09 PM PDT 24
Finished Apr 02 01:57:16 PM PDT 24
Peak memory 201852 kb
Host smart-5e77257a-b460-4f0c-8723-716258334766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088901373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.4088901373
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.670856265
Short name T11
Test name
Test status
Simulation time 161129842475 ps
CPU time 373.77 seconds
Started Apr 02 01:54:07 PM PDT 24
Finished Apr 02 02:00:21 PM PDT 24
Peak memory 201832 kb
Host smart-54cd802e-091b-4962-ab77-08c527a46c9d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=670856265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrup
t_fixed.670856265
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.2032310510
Short name T313
Test name
Test status
Simulation time 495994310002 ps
CPU time 1137.75 seconds
Started Apr 02 01:54:05 PM PDT 24
Finished Apr 02 02:13:03 PM PDT 24
Peak memory 201880 kb
Host smart-b4c468cd-6557-4dee-8473-3406cfc68abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032310510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.2032310510
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2976043630
Short name T604
Test name
Test status
Simulation time 500840085368 ps
CPU time 595.82 seconds
Started Apr 02 01:54:06 PM PDT 24
Finished Apr 02 02:04:02 PM PDT 24
Peak memory 201848 kb
Host smart-1b5b6525-a6c7-46f3-9f41-7df66a3b9ef6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976043630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2976043630
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.115573146
Short name T730
Test name
Test status
Simulation time 190555182301 ps
CPU time 219.84 seconds
Started Apr 02 01:54:09 PM PDT 24
Finished Apr 02 01:57:49 PM PDT 24
Peak memory 201904 kb
Host smart-4dd1e2f3-951f-4c5c-85f4-710475574df0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115573146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.115573146
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.4120883229
Short name T711
Test name
Test status
Simulation time 200106949798 ps
CPU time 475.43 seconds
Started Apr 02 01:54:11 PM PDT 24
Finished Apr 02 02:02:07 PM PDT 24
Peak memory 201860 kb
Host smart-4fbd4e80-9563-4e81-a51f-ec979b870395
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120883229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.4120883229
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3102162444
Short name T493
Test name
Test status
Simulation time 85361013720 ps
CPU time 384.24 seconds
Started Apr 02 01:54:15 PM PDT 24
Finished Apr 02 02:00:40 PM PDT 24
Peak memory 202180 kb
Host smart-8218ffea-148e-4896-895d-0d47c0b20353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102162444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3102162444
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1257947891
Short name T180
Test name
Test status
Simulation time 23130459748 ps
CPU time 51.25 seconds
Started Apr 02 01:54:15 PM PDT 24
Finished Apr 02 01:55:06 PM PDT 24
Peak memory 201624 kb
Host smart-81737743-ebdd-4394-967a-83af29b7a1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257947891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1257947891
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.3819396322
Short name T620
Test name
Test status
Simulation time 3765021651 ps
CPU time 10 seconds
Started Apr 02 01:54:11 PM PDT 24
Finished Apr 02 01:54:21 PM PDT 24
Peak memory 201668 kb
Host smart-f3726cee-fd05-4367-bc3e-d3d67cd61a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819396322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.3819396322
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.419944374
Short name T719
Test name
Test status
Simulation time 6005374169 ps
CPU time 14.57 seconds
Started Apr 02 01:54:00 PM PDT 24
Finished Apr 02 01:54:15 PM PDT 24
Peak memory 201720 kb
Host smart-40cae202-61dd-416f-964e-9d4a40c909d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419944374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.419944374
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3128932984
Short name T336
Test name
Test status
Simulation time 194487570375 ps
CPU time 238.77 seconds
Started Apr 02 01:54:16 PM PDT 24
Finished Apr 02 01:58:15 PM PDT 24
Peak memory 201868 kb
Host smart-05e20933-147a-47a2-a0d0-2be6184c51f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128932984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3128932984
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2034152648
Short name T746
Test name
Test status
Simulation time 548515220 ps
CPU time 0.94 seconds
Started Apr 02 01:54:41 PM PDT 24
Finished Apr 02 01:54:42 PM PDT 24
Peak memory 201496 kb
Host smart-ea0d4167-7463-4e3d-a0a3-4931670cbd6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034152648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2034152648
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.4134424566
Short name T229
Test name
Test status
Simulation time 162279858045 ps
CPU time 57.98 seconds
Started Apr 02 01:54:28 PM PDT 24
Finished Apr 02 01:55:27 PM PDT 24
Peak memory 201900 kb
Host smart-29f8789c-cca8-4469-a241-f778d0941d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134424566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.4134424566
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.331062763
Short name T683
Test name
Test status
Simulation time 161500365099 ps
CPU time 328.1 seconds
Started Apr 02 01:54:19 PM PDT 24
Finished Apr 02 01:59:47 PM PDT 24
Peak memory 201964 kb
Host smart-7a02e7a0-c4de-4a5b-b4ed-e51c4e37e750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331062763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.331062763
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3210485364
Short name T438
Test name
Test status
Simulation time 486304379560 ps
CPU time 1051.86 seconds
Started Apr 02 01:54:19 PM PDT 24
Finished Apr 02 02:11:51 PM PDT 24
Peak memory 201948 kb
Host smart-2b2164d3-096e-40d6-8c0c-005709b07c40
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210485364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3210485364
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2234532466
Short name T329
Test name
Test status
Simulation time 324570684351 ps
CPU time 757.48 seconds
Started Apr 02 01:54:18 PM PDT 24
Finished Apr 02 02:06:56 PM PDT 24
Peak memory 201896 kb
Host smart-f16bef85-7a2e-4a7c-8504-aca2e2e7237e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234532466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2234532466
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.3595254680
Short name T554
Test name
Test status
Simulation time 493155691788 ps
CPU time 545.85 seconds
Started Apr 02 01:54:17 PM PDT 24
Finished Apr 02 02:03:23 PM PDT 24
Peak memory 201892 kb
Host smart-3dcb53e0-3304-492c-981a-f6de1a6a30d7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595254680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.3595254680
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.1749541605
Short name T736
Test name
Test status
Simulation time 561461575796 ps
CPU time 1327.33 seconds
Started Apr 02 01:54:22 PM PDT 24
Finished Apr 02 02:16:29 PM PDT 24
Peak memory 201900 kb
Host smart-1f5ea627-9e3b-45a4-a63d-7f5e47b5d096
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749541605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.1749541605
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.546275992
Short name T553
Test name
Test status
Simulation time 208238290926 ps
CPU time 123.7 seconds
Started Apr 02 01:54:21 PM PDT 24
Finished Apr 02 01:56:25 PM PDT 24
Peak memory 201964 kb
Host smart-d8d78d0a-3ff1-4bfc-9355-9b7379e3860d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546275992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.546275992
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.2835187430
Short name T382
Test name
Test status
Simulation time 40048777136 ps
CPU time 19.97 seconds
Started Apr 02 01:54:31 PM PDT 24
Finished Apr 02 01:54:52 PM PDT 24
Peak memory 201720 kb
Host smart-8e4db317-ef41-45bd-a4b7-0323ce2915c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835187430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.2835187430
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3051407731
Short name T731
Test name
Test status
Simulation time 5180773796 ps
CPU time 5.87 seconds
Started Apr 02 01:54:30 PM PDT 24
Finished Apr 02 01:54:37 PM PDT 24
Peak memory 201696 kb
Host smart-69245179-d15f-446a-8237-8745976d7d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051407731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3051407731
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.521716209
Short name T606
Test name
Test status
Simulation time 6100483100 ps
CPU time 11.89 seconds
Started Apr 02 01:54:18 PM PDT 24
Finished Apr 02 01:54:30 PM PDT 24
Peak memory 201676 kb
Host smart-21e8b18c-a426-4e5f-b597-d1f3c57acc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521716209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.521716209
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2900073174
Short name T460
Test name
Test status
Simulation time 236526851431 ps
CPU time 308.62 seconds
Started Apr 02 01:54:42 PM PDT 24
Finished Apr 02 01:59:50 PM PDT 24
Peak memory 201940 kb
Host smart-ea505644-1bdf-4cda-858d-a064c40fb107
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900073174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2900073174
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.1065759040
Short name T743
Test name
Test status
Simulation time 527701190 ps
CPU time 1.91 seconds
Started Apr 02 01:55:05 PM PDT 24
Finished Apr 02 01:55:07 PM PDT 24
Peak memory 201592 kb
Host smart-d9e442f8-1820-4a73-9fdf-3d47765e3fa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065759040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1065759040
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.450216776
Short name T161
Test name
Test status
Simulation time 178426994120 ps
CPU time 65.58 seconds
Started Apr 02 01:54:49 PM PDT 24
Finished Apr 02 01:55:56 PM PDT 24
Peak memory 201892 kb
Host smart-bee88499-5706-4c31-89e3-35ff00fbdb20
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450216776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gati
ng.450216776
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.1250447534
Short name T297
Test name
Test status
Simulation time 555513960239 ps
CPU time 385.44 seconds
Started Apr 02 01:54:54 PM PDT 24
Finished Apr 02 02:01:20 PM PDT 24
Peak memory 201836 kb
Host smart-b3c57603-5b3a-4d8b-9310-231aa5e22c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250447534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.1250447534
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3039002359
Short name T480
Test name
Test status
Simulation time 169425231533 ps
CPU time 106.65 seconds
Started Apr 02 01:54:48 PM PDT 24
Finished Apr 02 01:56:35 PM PDT 24
Peak memory 201840 kb
Host smart-f9ab4e0f-8263-4b36-9498-f2ea20fdf5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039002359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3039002359
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.766047635
Short name T527
Test name
Test status
Simulation time 333191254406 ps
CPU time 365.11 seconds
Started Apr 02 01:54:48 PM PDT 24
Finished Apr 02 02:00:55 PM PDT 24
Peak memory 201828 kb
Host smart-305a820d-90c1-4a09-9d48-c59ea8d61c98
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=766047635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.766047635
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1691761857
Short name T312
Test name
Test status
Simulation time 490851101477 ps
CPU time 304.69 seconds
Started Apr 02 01:54:44 PM PDT 24
Finished Apr 02 01:59:49 PM PDT 24
Peak memory 201900 kb
Host smart-50ad3f91-aadb-4029-8c9e-d7077246f9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691761857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1691761857
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2174329289
Short name T497
Test name
Test status
Simulation time 494486677890 ps
CPU time 1188.49 seconds
Started Apr 02 01:54:44 PM PDT 24
Finished Apr 02 02:14:33 PM PDT 24
Peak memory 201876 kb
Host smart-e04df7f7-7bc1-41d7-a8b2-8534937268e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174329289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2174329289
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.1377920299
Short name T339
Test name
Test status
Simulation time 178752575609 ps
CPU time 43.32 seconds
Started Apr 02 01:54:47 PM PDT 24
Finished Apr 02 01:55:31 PM PDT 24
Peak memory 201896 kb
Host smart-e714a295-66f5-4047-8181-ca05cfca6d71
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377920299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.1377920299
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1711865985
Short name T405
Test name
Test status
Simulation time 605372898864 ps
CPU time 104.96 seconds
Started Apr 02 01:54:50 PM PDT 24
Finished Apr 02 01:56:36 PM PDT 24
Peak memory 201772 kb
Host smart-e34cdfd4-9a28-4cc7-a59e-4d0efb781c76
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711865985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1711865985
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.728283594
Short name T602
Test name
Test status
Simulation time 70569536461 ps
CPU time 211.54 seconds
Started Apr 02 01:54:55 PM PDT 24
Finished Apr 02 01:58:27 PM PDT 24
Peak memory 202268 kb
Host smart-d443db60-5e0e-4b34-ae37-12a9aacd7c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728283594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.728283594
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1964245255
Short name T594
Test name
Test status
Simulation time 27032975042 ps
CPU time 60.77 seconds
Started Apr 02 01:54:53 PM PDT 24
Finished Apr 02 01:55:54 PM PDT 24
Peak memory 201604 kb
Host smart-7d49a8e9-0e89-461f-ba9f-d9834ea83098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964245255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1964245255
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1510296550
Short name T505
Test name
Test status
Simulation time 2752791746 ps
CPU time 6.02 seconds
Started Apr 02 01:54:53 PM PDT 24
Finished Apr 02 01:55:00 PM PDT 24
Peak memory 201700 kb
Host smart-5062c08c-61e6-4914-ae1d-58f05127f25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510296550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1510296550
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3696149597
Short name T598
Test name
Test status
Simulation time 5831119099 ps
CPU time 2.91 seconds
Started Apr 02 01:54:44 PM PDT 24
Finished Apr 02 01:54:47 PM PDT 24
Peak memory 201676 kb
Host smart-2a189817-d6e2-4f41-a0fb-2457ee90a924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696149597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3696149597
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.3112943684
Short name T303
Test name
Test status
Simulation time 337677381378 ps
CPU time 379.84 seconds
Started Apr 02 01:54:59 PM PDT 24
Finished Apr 02 02:01:19 PM PDT 24
Peak memory 202000 kb
Host smart-88e10ebd-a733-4f0d-b96e-476b99b62ce4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112943684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.3112943684
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3225905882
Short name T784
Test name
Test status
Simulation time 26053310856 ps
CPU time 43.06 seconds
Started Apr 02 01:55:00 PM PDT 24
Finished Apr 02 01:55:44 PM PDT 24
Peak memory 210572 kb
Host smart-c8e6f58d-e01e-434a-bba2-9b1522a56bdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225905882 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.3225905882
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1745096457
Short name T373
Test name
Test status
Simulation time 386934454 ps
CPU time 1.06 seconds
Started Apr 02 01:55:15 PM PDT 24
Finished Apr 02 01:55:17 PM PDT 24
Peak memory 201596 kb
Host smart-8b6ad7e5-56b0-4729-aed1-a1960f28eb8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745096457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1745096457
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.2106735191
Short name T768
Test name
Test status
Simulation time 526845874535 ps
CPU time 84.9 seconds
Started Apr 02 01:55:12 PM PDT 24
Finished Apr 02 01:56:38 PM PDT 24
Peak memory 201864 kb
Host smart-866858a2-6c86-4441-99c8-9d33eca09b17
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106735191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.2106735191
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.989375773
Short name T679
Test name
Test status
Simulation time 324139110031 ps
CPU time 366.12 seconds
Started Apr 02 01:55:11 PM PDT 24
Finished Apr 02 02:01:17 PM PDT 24
Peak memory 201896 kb
Host smart-3f5e26c2-3bb0-4c99-9631-b366c4fbccd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989375773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.989375773
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3356278606
Short name T728
Test name
Test status
Simulation time 165344964660 ps
CPU time 39.81 seconds
Started Apr 02 01:55:08 PM PDT 24
Finished Apr 02 01:55:48 PM PDT 24
Peak memory 201964 kb
Host smart-69d57705-7d22-4fed-a636-f5670505a960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356278606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3356278606
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.356622315
Short name T675
Test name
Test status
Simulation time 337567467757 ps
CPU time 802.59 seconds
Started Apr 02 01:55:10 PM PDT 24
Finished Apr 02 02:08:33 PM PDT 24
Peak memory 201876 kb
Host smart-e1b940e1-5157-4307-8ac8-ee5c1757edca
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=356622315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.356622315
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2618994268
Short name T642
Test name
Test status
Simulation time 326394401681 ps
CPU time 185.38 seconds
Started Apr 02 01:55:07 PM PDT 24
Finished Apr 02 01:58:13 PM PDT 24
Peak memory 201960 kb
Host smart-956ffcfd-be97-4f60-9b64-5f0daa6984bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618994268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2618994268
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.2603716076
Short name T446
Test name
Test status
Simulation time 499875203282 ps
CPU time 377.8 seconds
Started Apr 02 01:55:08 PM PDT 24
Finished Apr 02 02:01:26 PM PDT 24
Peak memory 201848 kb
Host smart-ee2a42af-b333-4085-b442-1327253b1f6f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603716076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.2603716076
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.170290402
Short name T159
Test name
Test status
Simulation time 391391937920 ps
CPU time 938.95 seconds
Started Apr 02 01:55:09 PM PDT 24
Finished Apr 02 02:10:49 PM PDT 24
Peak memory 201908 kb
Host smart-aac6f321-54de-481e-8694-d49b633eed87
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170290402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_
wakeup.170290402
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.3197696855
Short name T525
Test name
Test status
Simulation time 192574796650 ps
CPU time 219.19 seconds
Started Apr 02 01:55:09 PM PDT 24
Finished Apr 02 01:58:48 PM PDT 24
Peak memory 201864 kb
Host smart-4579e5e5-0866-4acb-97e2-022be2b02ac3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197696855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.3197696855
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.4114314066
Short name T352
Test name
Test status
Simulation time 78009266000 ps
CPU time 425.29 seconds
Started Apr 02 01:55:20 PM PDT 24
Finished Apr 02 02:02:26 PM PDT 24
Peak memory 202168 kb
Host smart-e75049c8-9804-4880-b7a4-763c169449a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114314066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.4114314066
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.3856598619
Short name T392
Test name
Test status
Simulation time 37434250450 ps
CPU time 41.68 seconds
Started Apr 02 01:55:20 PM PDT 24
Finished Apr 02 01:56:02 PM PDT 24
Peak memory 201700 kb
Host smart-d7330069-b479-4454-b11b-3180e6c64cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856598619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.3856598619
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.4163193014
Short name T794
Test name
Test status
Simulation time 3074700986 ps
CPU time 4.46 seconds
Started Apr 02 01:55:12 PM PDT 24
Finished Apr 02 01:55:16 PM PDT 24
Peak memory 201660 kb
Host smart-3055054d-be12-4e16-97ce-d852a83fb448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163193014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.4163193014
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.44995137
Short name T767
Test name
Test status
Simulation time 5732638276 ps
CPU time 14.09 seconds
Started Apr 02 01:55:06 PM PDT 24
Finished Apr 02 01:55:20 PM PDT 24
Peak memory 201684 kb
Host smart-126a1c3c-b67f-4081-9f93-746a734a17f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44995137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.44995137
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.3968894190
Short name T340
Test name
Test status
Simulation time 260184139084 ps
CPU time 373.58 seconds
Started Apr 02 01:55:16 PM PDT 24
Finished Apr 02 02:01:31 PM PDT 24
Peak memory 210380 kb
Host smart-94eae3fc-8fcc-4a47-a043-7bf9acacdd41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968894190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.3968894190
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.645242921
Short name T775
Test name
Test status
Simulation time 56572764710 ps
CPU time 62.53 seconds
Started Apr 02 01:55:14 PM PDT 24
Finished Apr 02 01:56:17 PM PDT 24
Peak memory 202016 kb
Host smart-ca8d30f0-3c74-48bb-96c5-a493c53b798d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645242921 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.645242921
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.966223007
Short name T479
Test name
Test status
Simulation time 298634914 ps
CPU time 0.92 seconds
Started Apr 02 01:55:39 PM PDT 24
Finished Apr 02 01:55:40 PM PDT 24
Peak memory 201600 kb
Host smart-d886b82d-c87e-4d61-a9cb-815d59010abd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966223007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.966223007
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3547909181
Short name T235
Test name
Test status
Simulation time 381140927434 ps
CPU time 795.59 seconds
Started Apr 02 01:55:29 PM PDT 24
Finished Apr 02 02:08:45 PM PDT 24
Peak memory 201996 kb
Host smart-aa6a54b3-8363-4c36-9063-27ad4ef84367
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547909181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3547909181
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2843354616
Short name T605
Test name
Test status
Simulation time 162043712780 ps
CPU time 30.03 seconds
Started Apr 02 01:55:26 PM PDT 24
Finished Apr 02 01:55:56 PM PDT 24
Peak memory 201812 kb
Host smart-b97b6a2e-a267-4db3-9c85-818f0eab86d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843354616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2843354616
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.692513614
Short name T403
Test name
Test status
Simulation time 329642789525 ps
CPU time 759.33 seconds
Started Apr 02 01:55:24 PM PDT 24
Finished Apr 02 02:08:03 PM PDT 24
Peak memory 201856 kb
Host smart-7471621f-cc33-423b-b913-220b7a935076
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=692513614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.692513614
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.988899896
Short name T687
Test name
Test status
Simulation time 168787756839 ps
CPU time 108.55 seconds
Started Apr 02 01:55:23 PM PDT 24
Finished Apr 02 01:57:12 PM PDT 24
Peak memory 201900 kb
Host smart-0126f657-961b-405a-8a7f-2150fe6e0d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988899896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.988899896
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2189202682
Short name T395
Test name
Test status
Simulation time 164151380098 ps
CPU time 90.01 seconds
Started Apr 02 01:55:24 PM PDT 24
Finished Apr 02 01:56:54 PM PDT 24
Peak memory 201844 kb
Host smart-c488e79f-3110-4f17-8bbe-63f634d86ecf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189202682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2189202682
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.1455809650
Short name T367
Test name
Test status
Simulation time 595923180598 ps
CPU time 681.4 seconds
Started Apr 02 01:55:26 PM PDT 24
Finished Apr 02 02:06:48 PM PDT 24
Peak memory 201900 kb
Host smart-f385b32c-c690-44a0-a4f7-d76cb23e09f7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455809650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.1455809650
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1442780993
Short name T696
Test name
Test status
Simulation time 115315394976 ps
CPU time 591.03 seconds
Started Apr 02 01:55:37 PM PDT 24
Finished Apr 02 02:05:28 PM PDT 24
Peak memory 202112 kb
Host smart-5862586f-a6ca-4270-af23-bf4a8e18b63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442780993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1442780993
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.4065737219
Short name T378
Test name
Test status
Simulation time 22313593135 ps
CPU time 50.85 seconds
Started Apr 02 01:55:37 PM PDT 24
Finished Apr 02 01:56:28 PM PDT 24
Peak memory 201720 kb
Host smart-e1d021a6-ff67-4136-a35d-f4bcd1a0eacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065737219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.4065737219
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.405130297
Short name T408
Test name
Test status
Simulation time 4667635518 ps
CPU time 3.92 seconds
Started Apr 02 01:55:38 PM PDT 24
Finished Apr 02 01:55:42 PM PDT 24
Peak memory 201688 kb
Host smart-86347c7f-82e0-447f-8e51-a6af98260846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405130297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.405130297
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.4079184911
Short name T670
Test name
Test status
Simulation time 5820106511 ps
CPU time 15.14 seconds
Started Apr 02 01:55:19 PM PDT 24
Finished Apr 02 01:55:34 PM PDT 24
Peak memory 201612 kb
Host smart-ab313414-c904-4db0-bdca-5704e0ff60f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079184911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.4079184911
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.2895556647
Short name T288
Test name
Test status
Simulation time 174505213327 ps
CPU time 404.18 seconds
Started Apr 02 01:55:35 PM PDT 24
Finished Apr 02 02:02:20 PM PDT 24
Peak memory 201948 kb
Host smart-6895ad78-c9c5-442f-9cb8-029e00e6e0df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895556647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.2895556647
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3890381661
Short name T721
Test name
Test status
Simulation time 92792915559 ps
CPU time 57.6 seconds
Started Apr 02 01:55:36 PM PDT 24
Finished Apr 02 01:56:34 PM PDT 24
Peak memory 210528 kb
Host smart-586ba0e8-8f7f-4a06-9eef-4baa8e43a1cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890381661 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3890381661
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.2762280482
Short name T673
Test name
Test status
Simulation time 452863309 ps
CPU time 1.06 seconds
Started Apr 02 01:56:11 PM PDT 24
Finished Apr 02 01:56:12 PM PDT 24
Peak memory 201604 kb
Host smart-27be72ea-a59d-444e-bd84-54cd9bacb570
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762280482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.2762280482
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3519290646
Short name T659
Test name
Test status
Simulation time 365575872650 ps
CPU time 504.43 seconds
Started Apr 02 01:55:50 PM PDT 24
Finished Apr 02 02:04:15 PM PDT 24
Peak memory 201884 kb
Host smart-1bed34ba-4933-4424-bd5a-81bffca2e65d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519290646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3519290646
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2798923546
Short name T292
Test name
Test status
Simulation time 335043184368 ps
CPU time 210.81 seconds
Started Apr 02 01:55:51 PM PDT 24
Finished Apr 02 01:59:22 PM PDT 24
Peak memory 201876 kb
Host smart-3cd2376b-00ae-4e9c-b207-1e5841e121d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798923546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2798923546
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.3813444178
Short name T231
Test name
Test status
Simulation time 172256496428 ps
CPU time 32.78 seconds
Started Apr 02 01:55:47 PM PDT 24
Finished Apr 02 01:56:20 PM PDT 24
Peak memory 201776 kb
Host smart-17da83ac-4aac-450f-810c-531a3f2e5b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813444178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.3813444178
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1853557968
Short name T499
Test name
Test status
Simulation time 335416555358 ps
CPU time 340.05 seconds
Started Apr 02 01:55:47 PM PDT 24
Finished Apr 02 02:01:27 PM PDT 24
Peak memory 201876 kb
Host smart-b499b9e7-3b19-482c-8a7a-173e1101867d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853557968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1853557968
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.4066425591
Short name T778
Test name
Test status
Simulation time 327843925186 ps
CPU time 373 seconds
Started Apr 02 01:55:38 PM PDT 24
Finished Apr 02 02:01:52 PM PDT 24
Peak memory 201884 kb
Host smart-a788c267-c14a-44eb-b65b-82b27bbda60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066425591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.4066425591
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.113435414
Short name T164
Test name
Test status
Simulation time 323949729705 ps
CPU time 492.36 seconds
Started Apr 02 01:55:43 PM PDT 24
Finished Apr 02 02:03:55 PM PDT 24
Peak memory 201876 kb
Host smart-f6cdc772-82f1-49f8-b6fa-638aa2823cd1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=113435414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixe
d.113435414
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.2159776306
Short name T595
Test name
Test status
Simulation time 176853955671 ps
CPU time 99.78 seconds
Started Apr 02 01:55:52 PM PDT 24
Finished Apr 02 01:57:31 PM PDT 24
Peak memory 201852 kb
Host smart-d24c3c45-1b14-439d-912a-68c3c3e86ded
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159776306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.2159776306
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2548514030
Short name T464
Test name
Test status
Simulation time 603275252218 ps
CPU time 1391.42 seconds
Started Apr 02 01:55:51 PM PDT 24
Finished Apr 02 02:19:03 PM PDT 24
Peak memory 201792 kb
Host smart-4424a157-3ad3-40d3-88b9-de5032453da2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548514030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.2548514030
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2076893088
Short name T502
Test name
Test status
Simulation time 95053555797 ps
CPU time 328.64 seconds
Started Apr 02 01:55:56 PM PDT 24
Finished Apr 02 02:01:25 PM PDT 24
Peak memory 202172 kb
Host smart-e48e09d8-ac97-4d50-8697-dbc53606ccda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076893088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2076893088
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.726453644
Short name T407
Test name
Test status
Simulation time 30552006591 ps
CPU time 67.83 seconds
Started Apr 02 01:55:59 PM PDT 24
Finished Apr 02 01:57:07 PM PDT 24
Peak memory 201704 kb
Host smart-6df53f59-0801-48c3-b9bc-8c26191b8d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726453644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.726453644
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1798550008
Short name T498
Test name
Test status
Simulation time 3786899770 ps
CPU time 8.97 seconds
Started Apr 02 01:55:55 PM PDT 24
Finished Apr 02 01:56:05 PM PDT 24
Peak memory 201608 kb
Host smart-745d7d45-48ec-4f96-bbfd-7288aaf75f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798550008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1798550008
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1266604270
Short name T431
Test name
Test status
Simulation time 5879100527 ps
CPU time 4.17 seconds
Started Apr 02 01:55:38 PM PDT 24
Finished Apr 02 01:55:43 PM PDT 24
Peak memory 201676 kb
Host smart-6122d18d-aaa4-424b-8c93-ca7a39945e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266604270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1266604270
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.2741641004
Short name T216
Test name
Test status
Simulation time 248312221642 ps
CPU time 570.28 seconds
Started Apr 02 01:55:59 PM PDT 24
Finished Apr 02 02:05:30 PM PDT 24
Peak memory 202236 kb
Host smart-5de4d100-ddd1-4940-b893-7d2179152287
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741641004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.2741641004
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.4126807981
Short name T87
Test name
Test status
Simulation time 185640677660 ps
CPU time 161.57 seconds
Started Apr 02 01:56:02 PM PDT 24
Finished Apr 02 01:58:44 PM PDT 24
Peak memory 218412 kb
Host smart-815b73e9-76e5-4e5a-92a9-5a81f5903f5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126807981 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.4126807981
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.605320629
Short name T538
Test name
Test status
Simulation time 490205643 ps
CPU time 0.85 seconds
Started Apr 02 01:56:14 PM PDT 24
Finished Apr 02 01:56:15 PM PDT 24
Peak memory 201596 kb
Host smart-51cdc9d8-8d2a-4a83-8632-cd6c47942785
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605320629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.605320629
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.933555694
Short name T646
Test name
Test status
Simulation time 356819786600 ps
CPU time 106.8 seconds
Started Apr 02 01:56:12 PM PDT 24
Finished Apr 02 01:57:59 PM PDT 24
Peak memory 201800 kb
Host smart-d318d873-56c2-4224-b2a5-85f5e3a3327a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933555694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gati
ng.933555694
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2296126914
Short name T73
Test name
Test status
Simulation time 159223556127 ps
CPU time 59.24 seconds
Started Apr 02 01:56:08 PM PDT 24
Finished Apr 02 01:57:08 PM PDT 24
Peak memory 201844 kb
Host smart-f531559a-0d0b-4c45-9d6f-413e900b4af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296126914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2296126914
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.1095807117
Short name T473
Test name
Test status
Simulation time 487282543957 ps
CPU time 302.9 seconds
Started Apr 02 01:56:11 PM PDT 24
Finished Apr 02 02:01:14 PM PDT 24
Peak memory 201880 kb
Host smart-2226d090-650c-459e-b637-45d7377ed779
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095807117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.1095807117
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2703543606
Short name T667
Test name
Test status
Simulation time 319796056509 ps
CPU time 754.74 seconds
Started Apr 02 01:56:09 PM PDT 24
Finished Apr 02 02:08:44 PM PDT 24
Peak memory 201884 kb
Host smart-ecdedf75-3065-4f56-a504-0fdfe40b61a7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703543606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2703543606
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2249977666
Short name T391
Test name
Test status
Simulation time 205768845205 ps
CPU time 223.14 seconds
Started Apr 02 01:56:12 PM PDT 24
Finished Apr 02 01:59:55 PM PDT 24
Peak memory 201960 kb
Host smart-a5054378-da3a-4774-82f2-6bf17c08fda5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249977666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2249977666
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1075458657
Short name T556
Test name
Test status
Simulation time 77909296686 ps
CPU time 277.82 seconds
Started Apr 02 01:56:15 PM PDT 24
Finished Apr 02 02:00:53 PM PDT 24
Peak memory 202244 kb
Host smart-d75ede50-11a0-4b15-b985-006886ba0eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075458657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1075458657
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3183078792
Short name T519
Test name
Test status
Simulation time 30300654574 ps
CPU time 72.53 seconds
Started Apr 02 01:56:16 PM PDT 24
Finished Apr 02 01:57:29 PM PDT 24
Peak memory 201604 kb
Host smart-9bdb8d6a-f6ba-4ec1-b0f4-cc37248eb735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183078792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3183078792
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3878240352
Short name T99
Test name
Test status
Simulation time 4023343425 ps
CPU time 9.72 seconds
Started Apr 02 01:56:15 PM PDT 24
Finished Apr 02 01:56:25 PM PDT 24
Peak memory 201620 kb
Host smart-8bc9fa05-82c0-49dd-95ee-8e5a7ac21af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878240352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3878240352
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.200905429
Short name T787
Test name
Test status
Simulation time 5770437045 ps
CPU time 14.19 seconds
Started Apr 02 01:56:05 PM PDT 24
Finished Apr 02 01:56:19 PM PDT 24
Peak memory 201680 kb
Host smart-a1747d61-0800-409d-8e46-333b7732c150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200905429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.200905429
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2245519424
Short name T203
Test name
Test status
Simulation time 373286701250 ps
CPU time 173.63 seconds
Started Apr 02 01:56:14 PM PDT 24
Finished Apr 02 01:59:09 PM PDT 24
Peak memory 210188 kb
Host smart-9deba10f-1771-40f4-9246-cc656aa9a86c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245519424 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.2245519424
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.1244711602
Short name T520
Test name
Test status
Simulation time 552975489 ps
CPU time 0.91 seconds
Started Apr 02 01:56:37 PM PDT 24
Finished Apr 02 01:56:38 PM PDT 24
Peak memory 201604 kb
Host smart-bd8966fa-3c98-48c2-93b0-bae44766f9e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244711602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.1244711602
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1859255383
Short name T774
Test name
Test status
Simulation time 353022771309 ps
CPU time 668.36 seconds
Started Apr 02 01:56:30 PM PDT 24
Finished Apr 02 02:07:39 PM PDT 24
Peak memory 201936 kb
Host smart-184b9f8b-d170-4508-8ee6-9eb4732ab98a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859255383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1859255383
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.3179500545
Short name T343
Test name
Test status
Simulation time 506506697922 ps
CPU time 1128.12 seconds
Started Apr 02 01:56:27 PM PDT 24
Finished Apr 02 02:15:15 PM PDT 24
Peak memory 201916 kb
Host smart-20c6d542-b06e-4f46-961e-d3604a881bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179500545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3179500545
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.4271278436
Short name T561
Test name
Test status
Simulation time 167592313065 ps
CPU time 113.88 seconds
Started Apr 02 01:56:22 PM PDT 24
Finished Apr 02 01:58:17 PM PDT 24
Peak memory 201900 kb
Host smart-e7680198-a37d-4202-b16f-6f91384c4666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271278436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.4271278436
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2462516807
Short name T724
Test name
Test status
Simulation time 483095438122 ps
CPU time 97.37 seconds
Started Apr 02 01:56:22 PM PDT 24
Finished Apr 02 01:58:00 PM PDT 24
Peak memory 201808 kb
Host smart-86a2f658-0140-4e08-b98a-3e758c79a0c9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462516807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.2462516807
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1340465811
Short name T5
Test name
Test status
Simulation time 482980176640 ps
CPU time 1189.02 seconds
Started Apr 02 01:56:19 PM PDT 24
Finished Apr 02 02:16:08 PM PDT 24
Peak memory 201852 kb
Host smart-e27e367e-4c92-4192-aed9-d05dd644402b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340465811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1340465811
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2842798157
Short name T572
Test name
Test status
Simulation time 492658969022 ps
CPU time 276.52 seconds
Started Apr 02 01:56:18 PM PDT 24
Finished Apr 02 02:00:55 PM PDT 24
Peak memory 201852 kb
Host smart-278a5ddc-6730-4704-b727-c04c133374c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842798157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.2842798157
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2504252692
Short name T3
Test name
Test status
Simulation time 613854511878 ps
CPU time 1399.59 seconds
Started Apr 02 01:56:30 PM PDT 24
Finished Apr 02 02:19:50 PM PDT 24
Peak memory 201884 kb
Host smart-d6519dc6-2178-4e87-a813-6209c0b2b8c3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504252692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2504252692
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2173078474
Short name T81
Test name
Test status
Simulation time 129943472129 ps
CPU time 390.18 seconds
Started Apr 02 01:56:28 PM PDT 24
Finished Apr 02 02:02:59 PM PDT 24
Peak memory 202136 kb
Host smart-2a0299b1-ce59-4203-b109-32201acc6dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173078474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2173078474
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.3172228949
Short name T761
Test name
Test status
Simulation time 43075964100 ps
CPU time 96.53 seconds
Started Apr 02 01:56:32 PM PDT 24
Finished Apr 02 01:58:09 PM PDT 24
Peak memory 201644 kb
Host smart-ec960ba6-787f-4bed-b114-68c1b4e8cfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172228949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3172228949
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.1158758295
Short name T421
Test name
Test status
Simulation time 2996170396 ps
CPU time 2.26 seconds
Started Apr 02 01:56:28 PM PDT 24
Finished Apr 02 01:56:30 PM PDT 24
Peak memory 201604 kb
Host smart-0287b96a-8060-4ce9-96ba-e4930f160107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158758295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.1158758295
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3381667306
Short name T546
Test name
Test status
Simulation time 5690328738 ps
CPU time 7.65 seconds
Started Apr 02 01:56:19 PM PDT 24
Finished Apr 02 01:56:26 PM PDT 24
Peak memory 201688 kb
Host smart-037fa406-6a7b-4e0c-ad30-b95b6c0c192d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381667306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3381667306
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.4025906995
Short name T248
Test name
Test status
Simulation time 241302132973 ps
CPU time 529.4 seconds
Started Apr 02 01:56:35 PM PDT 24
Finished Apr 02 02:05:25 PM PDT 24
Peak memory 210348 kb
Host smart-41a3fa3c-f79f-4ca7-8c2b-0f26442d7eac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025906995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.4025906995
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2698986676
Short name T36
Test name
Test status
Simulation time 87320292515 ps
CPU time 178.25 seconds
Started Apr 02 01:56:32 PM PDT 24
Finished Apr 02 01:59:31 PM PDT 24
Peak memory 210128 kb
Host smart-99b6b9dc-5661-4dcc-a7e4-c7217e916c5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698986676 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2698986676
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1216772126
Short name T443
Test name
Test status
Simulation time 297847705 ps
CPU time 0.82 seconds
Started Apr 02 01:56:55 PM PDT 24
Finished Apr 02 01:56:56 PM PDT 24
Peak memory 201604 kb
Host smart-716c9d64-8167-4691-930c-11c73c5ee32a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216772126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1216772126
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.80833632
Short name T710
Test name
Test status
Simulation time 499047497286 ps
CPU time 214.58 seconds
Started Apr 02 01:56:43 PM PDT 24
Finished Apr 02 02:00:18 PM PDT 24
Peak memory 201860 kb
Host smart-b850e8b6-b3af-4321-82ba-50054fcd94cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80833632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gatin
g.80833632
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.569022611
Short name T738
Test name
Test status
Simulation time 482234598880 ps
CPU time 269.87 seconds
Started Apr 02 01:56:43 PM PDT 24
Finished Apr 02 02:01:13 PM PDT 24
Peak memory 201848 kb
Host smart-4295e04b-39e1-4efe-bf23-86935eff8aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569022611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.569022611
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2390074952
Short name T742
Test name
Test status
Simulation time 165448245284 ps
CPU time 183.91 seconds
Started Apr 02 01:56:44 PM PDT 24
Finished Apr 02 01:59:48 PM PDT 24
Peak memory 201920 kb
Host smart-20d15c68-8ac4-46e4-ad21-ca85a200e429
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390074952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2390074952
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.2296022032
Short name T637
Test name
Test status
Simulation time 323616433141 ps
CPU time 342.32 seconds
Started Apr 02 01:56:38 PM PDT 24
Finished Apr 02 02:02:21 PM PDT 24
Peak memory 201880 kb
Host smart-d2befca2-32c5-4441-aa34-51c87f9c60a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296022032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2296022032
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.1279069392
Short name T555
Test name
Test status
Simulation time 492290646795 ps
CPU time 353.5 seconds
Started Apr 02 01:56:45 PM PDT 24
Finished Apr 02 02:02:38 PM PDT 24
Peak memory 201872 kb
Host smart-4d773cc5-6fbf-4653-b58b-ed893f7115a0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279069392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.1279069392
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.3006180998
Short name T490
Test name
Test status
Simulation time 401502836057 ps
CPU time 926.01 seconds
Started Apr 02 01:56:41 PM PDT 24
Finished Apr 02 02:12:07 PM PDT 24
Peak memory 201884 kb
Host smart-05ca859f-ea26-47b9-a585-ad3c60124138
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006180998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.3006180998
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3033367611
Short name T613
Test name
Test status
Simulation time 82779200107 ps
CPU time 281.21 seconds
Started Apr 02 01:56:49 PM PDT 24
Finished Apr 02 02:01:32 PM PDT 24
Peak memory 202132 kb
Host smart-03e83304-b789-41c0-9ff2-b46036e885a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033367611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3033367611
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.661780317
Short name T495
Test name
Test status
Simulation time 27004926084 ps
CPU time 8.32 seconds
Started Apr 02 01:56:48 PM PDT 24
Finished Apr 02 01:56:56 PM PDT 24
Peak memory 201700 kb
Host smart-3ba2fdcd-fb7e-4a27-97b4-399d88a9e824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661780317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.661780317
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.752068480
Short name T106
Test name
Test status
Simulation time 2576478270 ps
CPU time 5.87 seconds
Started Apr 02 01:56:47 PM PDT 24
Finished Apr 02 01:56:53 PM PDT 24
Peak memory 201720 kb
Host smart-e825ade2-da8a-426b-afcd-171309e5dddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752068480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.752068480
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1366641350
Short name T577
Test name
Test status
Simulation time 5832305969 ps
CPU time 4.26 seconds
Started Apr 02 01:56:34 PM PDT 24
Finished Apr 02 01:56:39 PM PDT 24
Peak memory 201704 kb
Host smart-fbd23bfa-f06e-448c-a0e2-a2572d7c253f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366641350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1366641350
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.3305622710
Short name T453
Test name
Test status
Simulation time 124183912099 ps
CPU time 353.87 seconds
Started Apr 02 01:56:49 PM PDT 24
Finished Apr 02 02:02:43 PM PDT 24
Peak memory 202288 kb
Host smart-9db47220-3d52-4d9b-8533-2d99c611a304
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305622710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.3305622710
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2202633236
Short name T241
Test name
Test status
Simulation time 103240080160 ps
CPU time 156.51 seconds
Started Apr 02 01:56:49 PM PDT 24
Finished Apr 02 01:59:27 PM PDT 24
Peak memory 202684 kb
Host smart-90224d2c-667c-4a70-b000-a348041b1780
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202633236 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2202633236
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3762239758
Short name T61
Test name
Test status
Simulation time 322833950 ps
CPU time 0.82 seconds
Started Apr 02 01:57:08 PM PDT 24
Finished Apr 02 01:57:09 PM PDT 24
Peak memory 201596 kb
Host smart-5b67bcf1-bcbb-481f-9a8d-eced4d11df17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762239758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3762239758
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3429688770
Short name T715
Test name
Test status
Simulation time 161376886070 ps
CPU time 100.52 seconds
Started Apr 02 01:56:57 PM PDT 24
Finished Apr 02 01:58:38 PM PDT 24
Peak memory 201776 kb
Host smart-64339c35-d3da-4329-8f63-11d08945a736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429688770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3429688770
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.503706941
Short name T718
Test name
Test status
Simulation time 162358641825 ps
CPU time 356.2 seconds
Started Apr 02 01:56:56 PM PDT 24
Finished Apr 02 02:02:54 PM PDT 24
Peak memory 201884 kb
Host smart-7b4b4b7e-d2a0-4a75-b552-3e08ce42d7ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=503706941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrup
t_fixed.503706941
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.2928470720
Short name T757
Test name
Test status
Simulation time 486911002507 ps
CPU time 1132.44 seconds
Started Apr 02 01:56:56 PM PDT 24
Finished Apr 02 02:15:50 PM PDT 24
Peak memory 201880 kb
Host smart-84b124cb-5587-4476-92a6-7891c0088bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928470720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2928470720
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.435074439
Short name T416
Test name
Test status
Simulation time 164498151405 ps
CPU time 192.93 seconds
Started Apr 02 01:56:56 PM PDT 24
Finished Apr 02 02:00:10 PM PDT 24
Peak memory 201860 kb
Host smart-96176d43-544d-44eb-9aef-ff9cfbf24b6b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=435074439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.435074439
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.3428277682
Short name T508
Test name
Test status
Simulation time 169162794197 ps
CPU time 395.34 seconds
Started Apr 02 01:56:58 PM PDT 24
Finished Apr 02 02:03:34 PM PDT 24
Peak memory 201880 kb
Host smart-786cafda-cba5-483b-886d-86025ea07c9a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428277682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.3428277682
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.4033006803
Short name T588
Test name
Test status
Simulation time 595106480422 ps
CPU time 1250.85 seconds
Started Apr 02 01:57:00 PM PDT 24
Finished Apr 02 02:17:51 PM PDT 24
Peak memory 201900 kb
Host smart-e038ff4f-51a5-4c5d-aee4-8d02673eb6e4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033006803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.4033006803
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.773988531
Short name T701
Test name
Test status
Simulation time 109690421710 ps
CPU time 383.8 seconds
Started Apr 02 01:57:04 PM PDT 24
Finished Apr 02 02:03:28 PM PDT 24
Peak memory 202260 kb
Host smart-a2af57be-19f6-4cfe-8bee-49e65f8cbe41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773988531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.773988531
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.1235888224
Short name T727
Test name
Test status
Simulation time 25618737127 ps
CPU time 28.56 seconds
Started Apr 02 01:57:03 PM PDT 24
Finished Apr 02 01:57:32 PM PDT 24
Peak memory 201752 kb
Host smart-4fa68f1f-249c-4856-8b29-91f93b95b730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235888224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.1235888224
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.18797377
Short name T793
Test name
Test status
Simulation time 5506502281 ps
CPU time 15.67 seconds
Started Apr 02 01:57:00 PM PDT 24
Finished Apr 02 01:57:16 PM PDT 24
Peak memory 201608 kb
Host smart-af4c0136-8d2e-4db4-897d-cba77a3c49f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18797377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.18797377
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3186671836
Short name T365
Test name
Test status
Simulation time 6097446620 ps
CPU time 7.48 seconds
Started Apr 02 01:56:54 PM PDT 24
Finished Apr 02 01:57:02 PM PDT 24
Peak memory 201680 kb
Host smart-fcab6646-af1b-4414-bf60-6298261c1ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186671836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3186671836
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.1125760584
Short name T690
Test name
Test status
Simulation time 171221748437 ps
CPU time 25.2 seconds
Started Apr 02 01:57:07 PM PDT 24
Finished Apr 02 01:57:32 PM PDT 24
Peak memory 201940 kb
Host smart-ac3546c2-340b-4765-bbbc-7cc02052cab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125760584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.1125760584
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.1696576835
Short name T102
Test name
Test status
Simulation time 227817130136 ps
CPU time 143.42 seconds
Started Apr 02 01:57:07 PM PDT 24
Finished Apr 02 01:59:30 PM PDT 24
Peak memory 210244 kb
Host smart-ac2d0742-cbd9-43c7-8f44-a229b431b05d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696576835 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.1696576835
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1821058844
Short name T709
Test name
Test status
Simulation time 318485555 ps
CPU time 0.78 seconds
Started Apr 02 01:51:29 PM PDT 24
Finished Apr 02 01:51:30 PM PDT 24
Peak memory 201576 kb
Host smart-a7dfc9f0-92ff-4b65-a84a-e37bdf2ba6aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821058844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1821058844
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.94368891
Short name T729
Test name
Test status
Simulation time 350659380818 ps
CPU time 382.78 seconds
Started Apr 02 01:51:26 PM PDT 24
Finished Apr 02 01:57:49 PM PDT 24
Peak memory 201876 kb
Host smart-1fbd83d1-0859-4af3-8874-5d7a21180561
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94368891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gating
.94368891
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.1779600247
Short name T217
Test name
Test status
Simulation time 341407226802 ps
CPU time 503.1 seconds
Started Apr 02 01:51:28 PM PDT 24
Finished Apr 02 01:59:51 PM PDT 24
Peak memory 201852 kb
Host smart-8574b336-a75d-4a7d-b8c8-d4519386e9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779600247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1779600247
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1232973532
Short name T665
Test name
Test status
Simulation time 326471380371 ps
CPU time 756.06 seconds
Started Apr 02 01:51:30 PM PDT 24
Finished Apr 02 02:04:06 PM PDT 24
Peak memory 201872 kb
Host smart-c7b70b89-47fe-4460-b1e7-702541e74fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232973532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1232973532
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2582710660
Short name T686
Test name
Test status
Simulation time 160340533744 ps
CPU time 384.04 seconds
Started Apr 02 01:51:28 PM PDT 24
Finished Apr 02 01:57:52 PM PDT 24
Peak memory 201804 kb
Host smart-e3c53890-5db1-4c65-bf37-184a49ab8681
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582710660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.2582710660
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.452364216
Short name T689
Test name
Test status
Simulation time 160470814179 ps
CPU time 99.76 seconds
Started Apr 02 01:51:28 PM PDT 24
Finished Apr 02 01:53:08 PM PDT 24
Peak memory 201940 kb
Host smart-4b155456-8c2d-477e-ab0d-57786d129a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452364216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.452364216
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1389480097
Short name T567
Test name
Test status
Simulation time 336665629829 ps
CPU time 415.28 seconds
Started Apr 02 01:51:27 PM PDT 24
Finished Apr 02 01:58:22 PM PDT 24
Peak memory 201952 kb
Host smart-0de0d42e-1f35-4c9c-bbb5-0ccfb20be3b3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389480097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1389480097
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2429569864
Short name T524
Test name
Test status
Simulation time 422010215123 ps
CPU time 460.84 seconds
Started Apr 02 01:51:29 PM PDT 24
Finished Apr 02 01:59:10 PM PDT 24
Peak memory 201864 kb
Host smart-287d5c3c-9074-4dee-825a-5e37c333a120
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429569864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.2429569864
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3375829371
Short name T211
Test name
Test status
Simulation time 82409644079 ps
CPU time 383.75 seconds
Started Apr 02 01:51:27 PM PDT 24
Finished Apr 02 01:57:51 PM PDT 24
Peak memory 202252 kb
Host smart-f62d2d2a-8b5e-40e1-aa11-dca8f6ec4663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375829371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3375829371
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3118988541
Short name T503
Test name
Test status
Simulation time 24172325693 ps
CPU time 46.53 seconds
Started Apr 02 01:51:27 PM PDT 24
Finished Apr 02 01:52:14 PM PDT 24
Peak memory 201688 kb
Host smart-a115f625-018e-4a33-bc59-87dadbbfd649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118988541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3118988541
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3290549221
Short name T570
Test name
Test status
Simulation time 5218805009 ps
CPU time 4.1 seconds
Started Apr 02 01:51:28 PM PDT 24
Finished Apr 02 01:51:33 PM PDT 24
Peak memory 201616 kb
Host smart-69ad63f3-cde3-4fe1-8852-11986cbbcea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290549221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3290549221
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.1954357575
Short name T58
Test name
Test status
Simulation time 8460746650 ps
CPU time 1.88 seconds
Started Apr 02 01:51:30 PM PDT 24
Finished Apr 02 01:51:32 PM PDT 24
Peak memory 218016 kb
Host smart-114702fb-871b-4d81-b471-627611197859
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954357575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.1954357575
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.15739277
Short name T176
Test name
Test status
Simulation time 5855533508 ps
CPU time 7.96 seconds
Started Apr 02 01:51:26 PM PDT 24
Finished Apr 02 01:51:34 PM PDT 24
Peak memory 201668 kb
Host smart-42d46122-cd17-4baa-8786-25d73ac2e776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15739277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.15739277
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.18485795
Short name T435
Test name
Test status
Simulation time 527786053 ps
CPU time 1.2 seconds
Started Apr 02 01:57:26 PM PDT 24
Finished Apr 02 01:57:27 PM PDT 24
Peak memory 201552 kb
Host smart-136c6560-2557-4ac1-a0e6-4585bc61703f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18485795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.18485795
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1393689102
Short name T684
Test name
Test status
Simulation time 331483552721 ps
CPU time 381.09 seconds
Started Apr 02 01:57:14 PM PDT 24
Finished Apr 02 02:03:35 PM PDT 24
Peak memory 201804 kb
Host smart-cf6268f9-149f-4d45-8de4-774e31bebfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393689102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1393689102
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2035424662
Short name T245
Test name
Test status
Simulation time 164002493310 ps
CPU time 97.59 seconds
Started Apr 02 01:57:11 PM PDT 24
Finished Apr 02 01:58:48 PM PDT 24
Peak memory 201840 kb
Host smart-b0fe211f-a99d-44df-866f-579229542584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035424662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2035424662
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3237759151
Short name T777
Test name
Test status
Simulation time 163449072458 ps
CPU time 356.6 seconds
Started Apr 02 01:57:12 PM PDT 24
Finished Apr 02 02:03:08 PM PDT 24
Peak memory 201836 kb
Host smart-e8e13d4f-1a9c-4b08-8406-ad35193ecd4f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237759151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3237759151
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2262053359
Short name T716
Test name
Test status
Simulation time 166807419872 ps
CPU time 209.07 seconds
Started Apr 02 01:57:11 PM PDT 24
Finished Apr 02 02:00:40 PM PDT 24
Peak memory 201780 kb
Host smart-bc746cb4-3194-4b83-b646-74f76f6eb1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262053359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2262053359
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2380592161
Short name T361
Test name
Test status
Simulation time 487706029147 ps
CPU time 1015.49 seconds
Started Apr 02 01:57:12 PM PDT 24
Finished Apr 02 02:14:07 PM PDT 24
Peak memory 201848 kb
Host smart-6efdffea-0e5f-48c6-89c1-c12ff609b0c4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380592161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2380592161
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.936776203
Short name T500
Test name
Test status
Simulation time 171916410766 ps
CPU time 103.63 seconds
Started Apr 02 01:57:10 PM PDT 24
Finished Apr 02 01:58:54 PM PDT 24
Peak memory 201896 kb
Host smart-d8131389-2d84-4126-97c1-a8c5cb45c5a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936776203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_
wakeup.936776203
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3330994531
Short name T441
Test name
Test status
Simulation time 397547885004 ps
CPU time 280.12 seconds
Started Apr 02 01:57:12 PM PDT 24
Finished Apr 02 02:01:52 PM PDT 24
Peak memory 201868 kb
Host smart-1caa060c-e165-4736-97f2-5e7479131272
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330994531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3330994531
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.646912150
Short name T651
Test name
Test status
Simulation time 79441290911 ps
CPU time 333.36 seconds
Started Apr 02 01:57:22 PM PDT 24
Finished Apr 02 02:02:56 PM PDT 24
Peak memory 202236 kb
Host smart-dcf37964-77a0-43cb-8d10-ef6d9f4f952e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646912150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.646912150
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.333930497
Short name T539
Test name
Test status
Simulation time 23932519038 ps
CPU time 12.87 seconds
Started Apr 02 01:57:18 PM PDT 24
Finished Apr 02 01:57:31 PM PDT 24
Peak memory 201716 kb
Host smart-b9a87747-64f4-402d-9eeb-03004628fdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333930497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.333930497
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3367415244
Short name T404
Test name
Test status
Simulation time 3835622038 ps
CPU time 8.85 seconds
Started Apr 02 01:57:17 PM PDT 24
Finished Apr 02 01:57:27 PM PDT 24
Peak memory 201712 kb
Host smart-bff63916-df0f-4355-9c89-3ebcabeab926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367415244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3367415244
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1062485097
Short name T396
Test name
Test status
Simulation time 6030004790 ps
CPU time 1.97 seconds
Started Apr 02 01:57:08 PM PDT 24
Finished Apr 02 01:57:10 PM PDT 24
Peak memory 201744 kb
Host smart-f5322a3a-c2a2-4172-be68-874fbe8e3280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062485097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1062485097
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3138330168
Short name T755
Test name
Test status
Simulation time 180441282027 ps
CPU time 224.26 seconds
Started Apr 02 01:57:26 PM PDT 24
Finished Apr 02 02:01:11 PM PDT 24
Peak memory 201920 kb
Host smart-06960a2a-e213-48ef-a5ae-7c2c2e6e2a94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138330168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3138330168
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2995071758
Short name T285
Test name
Test status
Simulation time 287279980309 ps
CPU time 177.3 seconds
Started Apr 02 01:57:21 PM PDT 24
Finished Apr 02 02:00:19 PM PDT 24
Peak memory 210500 kb
Host smart-7bc94c4c-25c6-46db-9a71-070b26b2308e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995071758 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2995071758
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.1315419054
Short name T434
Test name
Test status
Simulation time 510523831 ps
CPU time 1.83 seconds
Started Apr 02 01:57:41 PM PDT 24
Finished Apr 02 01:57:43 PM PDT 24
Peak memory 201572 kb
Host smart-47a43473-88be-4795-9d9c-35d7d565473d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315419054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.1315419054
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.200547051
Short name T294
Test name
Test status
Simulation time 195224420904 ps
CPU time 79.56 seconds
Started Apr 02 01:57:33 PM PDT 24
Finished Apr 02 01:58:52 PM PDT 24
Peak memory 201808 kb
Host smart-b2293605-35ef-4989-8793-4677d45f1410
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200547051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gati
ng.200547051
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1598966940
Short name T97
Test name
Test status
Simulation time 324250400789 ps
CPU time 773.8 seconds
Started Apr 02 01:57:33 PM PDT 24
Finished Apr 02 02:10:27 PM PDT 24
Peak memory 201912 kb
Host smart-06eb58aa-2acf-4517-b4c4-73d28b4e002c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598966940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1598966940
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1383264109
Short name T506
Test name
Test status
Simulation time 490633732120 ps
CPU time 314.61 seconds
Started Apr 02 01:57:29 PM PDT 24
Finished Apr 02 02:02:43 PM PDT 24
Peak memory 201872 kb
Host smart-97e7b370-dd6b-4531-922d-78a127577d8c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383264109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.1383264109
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2698547083
Short name T533
Test name
Test status
Simulation time 161506412468 ps
CPU time 335.51 seconds
Started Apr 02 01:57:28 PM PDT 24
Finished Apr 02 02:03:04 PM PDT 24
Peak memory 201888 kb
Host smart-e0d80c40-0101-4936-a918-102a1c676b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698547083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2698547083
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3037129813
Short name T375
Test name
Test status
Simulation time 165886868133 ps
CPU time 418.93 seconds
Started Apr 02 01:57:29 PM PDT 24
Finished Apr 02 02:04:28 PM PDT 24
Peak memory 201844 kb
Host smart-a222d26f-3cd7-41f8-92cf-8600b9fcb73a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037129813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3037129813
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.818184276
Short name T310
Test name
Test status
Simulation time 455486852860 ps
CPU time 564.31 seconds
Started Apr 02 01:57:34 PM PDT 24
Finished Apr 02 02:06:58 PM PDT 24
Peak memory 201896 kb
Host smart-46196bb0-b37d-4ece-ba07-12387c90f6da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818184276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_
wakeup.818184276
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.745833019
Short name T168
Test name
Test status
Simulation time 403301194568 ps
CPU time 210.48 seconds
Started Apr 02 01:57:31 PM PDT 24
Finished Apr 02 02:01:01 PM PDT 24
Peak memory 201876 kb
Host smart-aabccba9-8fbb-4596-9f62-b27cb031a93c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745833019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
adc_ctrl_filters_wakeup_fixed.745833019
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.1543374953
Short name T783
Test name
Test status
Simulation time 102916875701 ps
CPU time 530.2 seconds
Started Apr 02 01:57:40 PM PDT 24
Finished Apr 02 02:06:30 PM PDT 24
Peak memory 202220 kb
Host smart-c3f9bbd5-a774-4dc6-bb01-9acd99f182bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543374953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1543374953
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.421080708
Short name T358
Test name
Test status
Simulation time 25083474030 ps
CPU time 4.37 seconds
Started Apr 02 01:57:37 PM PDT 24
Finished Apr 02 01:57:42 PM PDT 24
Peak memory 201608 kb
Host smart-ed588bfa-781e-4369-954a-a8f8bedd8c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421080708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.421080708
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.1735928212
Short name T688
Test name
Test status
Simulation time 4171017398 ps
CPU time 5.65 seconds
Started Apr 02 01:57:32 PM PDT 24
Finished Apr 02 01:57:37 PM PDT 24
Peak memory 201708 kb
Host smart-9c117a6c-b8e7-410e-af57-ca7e2e99944b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735928212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1735928212
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2570125935
Short name T691
Test name
Test status
Simulation time 5643831237 ps
CPU time 9.36 seconds
Started Apr 02 01:57:30 PM PDT 24
Finished Apr 02 01:57:39 PM PDT 24
Peak memory 201680 kb
Host smart-c3e9ad2f-1e38-4e29-901c-566b443a5fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570125935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2570125935
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.29989652
Short name T580
Test name
Test status
Simulation time 163854514573 ps
CPU time 386.87 seconds
Started Apr 02 01:57:40 PM PDT 24
Finished Apr 02 02:04:07 PM PDT 24
Peak memory 201852 kb
Host smart-6c5c97f2-715f-49cd-b61d-443c59937932
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29989652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.29989652
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3028855655
Short name T745
Test name
Test status
Simulation time 320112996 ps
CPU time 1.37 seconds
Started Apr 02 01:58:07 PM PDT 24
Finished Apr 02 01:58:08 PM PDT 24
Peak memory 201596 kb
Host smart-d328cfe5-fa25-4099-bcce-65be2ea6f6aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028855655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3028855655
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.2323740123
Short name T242
Test name
Test status
Simulation time 505507707661 ps
CPU time 169.99 seconds
Started Apr 02 01:57:51 PM PDT 24
Finished Apr 02 02:00:42 PM PDT 24
Peak memory 201856 kb
Host smart-41a5c69f-29f8-4e10-99fe-a78903c2d184
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323740123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.2323740123
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.2855186520
Short name T662
Test name
Test status
Simulation time 166081748974 ps
CPU time 49.97 seconds
Started Apr 02 01:57:51 PM PDT 24
Finished Apr 02 01:58:42 PM PDT 24
Peak memory 201980 kb
Host smart-94d2ec4d-8984-47be-8638-ee52258a3f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855186520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.2855186520
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.3228776184
Short name T621
Test name
Test status
Simulation time 325848559923 ps
CPU time 525.29 seconds
Started Apr 02 01:57:48 PM PDT 24
Finished Apr 02 02:06:34 PM PDT 24
Peak memory 201976 kb
Host smart-c9dc62b3-3519-43a1-9e30-c870878bbc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228776184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3228776184
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3920132185
Short name T96
Test name
Test status
Simulation time 486107408305 ps
CPU time 333.42 seconds
Started Apr 02 01:57:47 PM PDT 24
Finished Apr 02 02:03:21 PM PDT 24
Peak memory 201908 kb
Host smart-e06f80ed-0e1b-46fa-8cf5-3c8c9961e6c9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920132185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3920132185
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3354925103
Short name T147
Test name
Test status
Simulation time 489177324391 ps
CPU time 1190.27 seconds
Started Apr 02 01:57:43 PM PDT 24
Finished Apr 02 02:17:33 PM PDT 24
Peak memory 201812 kb
Host smart-5341d4b4-c169-4ce6-be02-c6d5b3e6693b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354925103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3354925103
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.1453140840
Short name T192
Test name
Test status
Simulation time 166482789808 ps
CPU time 94.6 seconds
Started Apr 02 01:57:43 PM PDT 24
Finished Apr 02 01:59:17 PM PDT 24
Peak memory 201844 kb
Host smart-89a7aff7-d364-46ee-a535-83edd893b75a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453140840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.1453140840
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2817029856
Short name T568
Test name
Test status
Simulation time 203281492595 ps
CPU time 249.47 seconds
Started Apr 02 01:58:21 PM PDT 24
Finished Apr 02 02:02:31 PM PDT 24
Peak memory 201912 kb
Host smart-059a1f42-d4ba-4522-bc89-6dfd645afd22
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817029856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2817029856
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2717084668
Short name T450
Test name
Test status
Simulation time 125126169571 ps
CPU time 495.55 seconds
Started Apr 02 01:58:03 PM PDT 24
Finished Apr 02 02:06:19 PM PDT 24
Peak memory 202176 kb
Host smart-26a8f302-c65b-427c-8c5e-12bdfdd498a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717084668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2717084668
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.1556691733
Short name T469
Test name
Test status
Simulation time 41050836464 ps
CPU time 94.11 seconds
Started Apr 02 01:57:59 PM PDT 24
Finished Apr 02 01:59:33 PM PDT 24
Peak memory 201708 kb
Host smart-31c77a31-14f7-4f44-a062-2b72712784da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556691733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1556691733
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.1388708422
Short name T739
Test name
Test status
Simulation time 4924015937 ps
CPU time 6.44 seconds
Started Apr 02 01:58:00 PM PDT 24
Finished Apr 02 01:58:07 PM PDT 24
Peak memory 201708 kb
Host smart-eb309b85-068a-46de-90d7-3015532bb766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388708422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1388708422
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.803219982
Short name T178
Test name
Test status
Simulation time 5955241231 ps
CPU time 8.1 seconds
Started Apr 02 01:57:43 PM PDT 24
Finished Apr 02 01:57:51 PM PDT 24
Peak memory 201700 kb
Host smart-c7943ec3-6920-4d54-9d2a-0d3760b54fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803219982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.803219982
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.251429192
Short name T103
Test name
Test status
Simulation time 186305701614 ps
CPU time 82.49 seconds
Started Apr 02 01:58:03 PM PDT 24
Finished Apr 02 01:59:25 PM PDT 24
Peak memory 201876 kb
Host smart-cdaac1e6-41dc-4803-80eb-b9aff41bb768
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251429192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.
251429192
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1430820652
Short name T175
Test name
Test status
Simulation time 28858405867 ps
CPU time 63.87 seconds
Started Apr 02 01:58:02 PM PDT 24
Finished Apr 02 01:59:06 PM PDT 24
Peak memory 210540 kb
Host smart-86121903-ddfb-415a-8c79-8f68863fead5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430820652 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1430820652
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.4265916080
Short name T649
Test name
Test status
Simulation time 450450761 ps
CPU time 0.78 seconds
Started Apr 02 01:58:14 PM PDT 24
Finished Apr 02 01:58:15 PM PDT 24
Peak memory 201528 kb
Host smart-ce566c33-aac9-4404-a1be-3b7374276516
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265916080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.4265916080
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.1456406507
Short name T578
Test name
Test status
Simulation time 588415232711 ps
CPU time 499.83 seconds
Started Apr 02 01:58:08 PM PDT 24
Finished Apr 02 02:06:28 PM PDT 24
Peak memory 201916 kb
Host smart-d1f0a34f-e817-4c34-9ba8-2eeec3cd051e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456406507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.1456406507
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.3183003016
Short name T596
Test name
Test status
Simulation time 195295707859 ps
CPU time 441.43 seconds
Started Apr 02 01:58:11 PM PDT 24
Finished Apr 02 02:05:33 PM PDT 24
Peak memory 201896 kb
Host smart-7ba32e3b-26ef-492c-807f-6fd79e5edb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183003016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3183003016
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.362348938
Short name T545
Test name
Test status
Simulation time 338758432326 ps
CPU time 387.29 seconds
Started Apr 02 01:58:01 PM PDT 24
Finished Apr 02 02:04:29 PM PDT 24
Peak memory 201860 kb
Host smart-65ecc0f0-ea4b-4001-afa0-6170851497ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=362348938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.362348938
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.3365493838
Short name T749
Test name
Test status
Simulation time 492945056133 ps
CPU time 594.85 seconds
Started Apr 02 01:58:00 PM PDT 24
Finished Apr 02 02:07:56 PM PDT 24
Peak memory 201796 kb
Host smart-ef9529f9-4eab-4376-bb9b-a306617d23fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365493838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3365493838
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1012666367
Short name T779
Test name
Test status
Simulation time 165742564434 ps
CPU time 102.9 seconds
Started Apr 02 01:58:01 PM PDT 24
Finished Apr 02 01:59:44 PM PDT 24
Peak memory 201868 kb
Host smart-2081fe9b-57ab-4567-a903-29371b264f06
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012666367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1012666367
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.2418060321
Short name T150
Test name
Test status
Simulation time 418459578181 ps
CPU time 951.2 seconds
Started Apr 02 01:58:06 PM PDT 24
Finished Apr 02 02:13:58 PM PDT 24
Peak memory 201920 kb
Host smart-fa8d8de9-107f-4bfd-9b9d-4b5b31ec8c30
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418060321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.2418060321
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1474557186
Short name T402
Test name
Test status
Simulation time 111442319854 ps
CPU time 457.98 seconds
Started Apr 02 01:58:13 PM PDT 24
Finished Apr 02 02:05:52 PM PDT 24
Peak memory 202172 kb
Host smart-e8b8f008-e1f7-4839-8194-6f0e473317d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474557186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1474557186
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3889009541
Short name T764
Test name
Test status
Simulation time 23296989076 ps
CPU time 13.36 seconds
Started Apr 02 01:58:10 PM PDT 24
Finished Apr 02 01:58:24 PM PDT 24
Peak memory 201604 kb
Host smart-e4f80aa7-6371-460f-b5fe-ef825f699e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889009541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3889009541
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.2572945369
Short name T454
Test name
Test status
Simulation time 3681512880 ps
CPU time 9.02 seconds
Started Apr 02 01:58:10 PM PDT 24
Finished Apr 02 01:58:20 PM PDT 24
Peak memory 201744 kb
Host smart-3a31d843-ccad-4a15-962b-2cd08d06cd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572945369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2572945369
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.1986407966
Short name T558
Test name
Test status
Simulation time 5791847654 ps
CPU time 14.12 seconds
Started Apr 02 01:58:06 PM PDT 24
Finished Apr 02 01:58:20 PM PDT 24
Peak memory 201704 kb
Host smart-a098ebc9-b7ee-40c6-9167-df7694b64920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986407966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.1986407966
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.461846503
Short name T328
Test name
Test status
Simulation time 213276189944 ps
CPU time 108.08 seconds
Started Apr 02 01:58:15 PM PDT 24
Finished Apr 02 02:00:04 PM PDT 24
Peak memory 201908 kb
Host smart-99c20be9-926c-4c17-bf43-91935247ea06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461846503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
461846503
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.370213127
Short name T17
Test name
Test status
Simulation time 71046737018 ps
CPU time 94.11 seconds
Started Apr 02 01:58:10 PM PDT 24
Finished Apr 02 01:59:45 PM PDT 24
Peak memory 210416 kb
Host smart-9e6dc557-d6f0-4fa6-b828-0d7715052671
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370213127 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.370213127
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.903088536
Short name T526
Test name
Test status
Simulation time 493068465 ps
CPU time 0.84 seconds
Started Apr 02 01:58:25 PM PDT 24
Finished Apr 02 01:58:26 PM PDT 24
Peak memory 201532 kb
Host smart-6ef40417-5e8f-4eb2-9c59-dba83e5f0804
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903088536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.903088536
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.33234493
Short name T754
Test name
Test status
Simulation time 216046976864 ps
CPU time 487.64 seconds
Started Apr 02 01:58:17 PM PDT 24
Finished Apr 02 02:06:25 PM PDT 24
Peak memory 201924 kb
Host smart-35b8a754-1522-4574-ad87-5002cc2ab41d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33234493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gatin
g.33234493
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.4229388335
Short name T597
Test name
Test status
Simulation time 328787415971 ps
CPU time 787.51 seconds
Started Apr 02 01:58:15 PM PDT 24
Finished Apr 02 02:11:22 PM PDT 24
Peak memory 201964 kb
Host smart-f7444f81-a5bc-41cd-b214-fd786e6f39fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229388335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.4229388335
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.554139098
Short name T601
Test name
Test status
Simulation time 330629818802 ps
CPU time 795.28 seconds
Started Apr 02 01:58:18 PM PDT 24
Finished Apr 02 02:11:34 PM PDT 24
Peak memory 201864 kb
Host smart-f879abbd-3793-464f-b9bd-72336c35c118
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=554139098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrup
t_fixed.554139098
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.423706151
Short name T334
Test name
Test status
Simulation time 324572247148 ps
CPU time 679.05 seconds
Started Apr 02 01:58:15 PM PDT 24
Finished Apr 02 02:09:34 PM PDT 24
Peak memory 201900 kb
Host smart-005b423a-dbe4-47c9-a950-3d7a9b8ca1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423706151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.423706151
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1152723704
Short name T704
Test name
Test status
Simulation time 161474198802 ps
CPU time 35.08 seconds
Started Apr 02 01:58:14 PM PDT 24
Finished Apr 02 01:58:49 PM PDT 24
Peak memory 201860 kb
Host smart-d4d1674c-f0f1-4309-8c41-a2e14daf80ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152723704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1152723704
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.183285618
Short name T523
Test name
Test status
Simulation time 528791317518 ps
CPU time 1180.53 seconds
Started Apr 02 01:58:16 PM PDT 24
Finished Apr 02 02:17:57 PM PDT 24
Peak memory 201832 kb
Host smart-69cfcac5-61d5-4776-9f8a-0e2a4daeae1c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183285618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_
wakeup.183285618
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2706720358
Short name T415
Test name
Test status
Simulation time 604214087408 ps
CPU time 1430.13 seconds
Started Apr 02 01:58:18 PM PDT 24
Finished Apr 02 02:22:09 PM PDT 24
Peak memory 201812 kb
Host smart-74072e06-a19a-4133-8c70-a5eb49cfb1e1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706720358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.2706720358
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.2815053256
Short name T427
Test name
Test status
Simulation time 41163705609 ps
CPU time 16.5 seconds
Started Apr 02 01:58:20 PM PDT 24
Finished Apr 02 01:58:36 PM PDT 24
Peak memory 201664 kb
Host smart-7ea812d1-f394-47d1-9c3e-80a653a3fd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815053256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.2815053256
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.563593827
Short name T516
Test name
Test status
Simulation time 3898960341 ps
CPU time 9.35 seconds
Started Apr 02 01:58:21 PM PDT 24
Finished Apr 02 01:58:30 PM PDT 24
Peak memory 201692 kb
Host smart-76dcdd51-fed7-42ab-b37f-7ec4f64e4792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563593827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.563593827
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.1027784799
Short name T363
Test name
Test status
Simulation time 5508916108 ps
CPU time 12.96 seconds
Started Apr 02 01:58:14 PM PDT 24
Finished Apr 02 01:58:27 PM PDT 24
Peak memory 201716 kb
Host smart-7cddce56-8719-4309-a98a-097a941138e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027784799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.1027784799
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1784521407
Short name T657
Test name
Test status
Simulation time 30583199366 ps
CPU time 19.26 seconds
Started Apr 02 01:58:26 PM PDT 24
Finished Apr 02 01:58:45 PM PDT 24
Peak memory 201636 kb
Host smart-97c90af4-41af-4d4a-b055-0add0588bb2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784521407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1784521407
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2984723700
Short name T4
Test name
Test status
Simulation time 488869242 ps
CPU time 1.66 seconds
Started Apr 02 01:58:45 PM PDT 24
Finished Apr 02 01:58:46 PM PDT 24
Peak memory 201508 kb
Host smart-acfdff39-2956-4497-8f68-5f5ae79d76b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984723700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2984723700
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3339168919
Short name T13
Test name
Test status
Simulation time 160898755597 ps
CPU time 92.76 seconds
Started Apr 02 01:58:41 PM PDT 24
Finished Apr 02 02:00:14 PM PDT 24
Peak memory 201988 kb
Host smart-9cc7cff1-0956-4174-bb89-757559673467
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339168919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3339168919
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2387861964
Short name T182
Test name
Test status
Simulation time 495449889570 ps
CPU time 343.75 seconds
Started Apr 02 01:58:34 PM PDT 24
Finished Apr 02 02:04:18 PM PDT 24
Peak memory 201840 kb
Host smart-4909faf5-724e-49ae-8fb7-f5976fb0bad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387861964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2387861964
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2366582156
Short name T474
Test name
Test status
Simulation time 164981954443 ps
CPU time 378.3 seconds
Started Apr 02 01:58:37 PM PDT 24
Finished Apr 02 02:04:55 PM PDT 24
Peak memory 201876 kb
Host smart-9e17734c-026c-4200-abe0-8b7a892a391e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366582156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.2366582156
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3359542864
Short name T541
Test name
Test status
Simulation time 490494061205 ps
CPU time 1136.76 seconds
Started Apr 02 01:58:27 PM PDT 24
Finished Apr 02 02:17:24 PM PDT 24
Peak memory 201888 kb
Host smart-db7f35f5-2ac1-4aec-8ac3-1512d5b61fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359542864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3359542864
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.4278337134
Short name T712
Test name
Test status
Simulation time 161733012461 ps
CPU time 98.6 seconds
Started Apr 02 01:58:29 PM PDT 24
Finished Apr 02 02:00:08 PM PDT 24
Peak memory 201856 kb
Host smart-01d269ab-0d26-4a49-9d4b-d5c77ed7e8eb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278337134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.4278337134
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1894069107
Short name T628
Test name
Test status
Simulation time 200502744921 ps
CPU time 241.26 seconds
Started Apr 02 01:58:38 PM PDT 24
Finished Apr 02 02:02:40 PM PDT 24
Peak memory 201840 kb
Host smart-acfcc10b-324c-4bf1-b0e3-cab424b081cd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894069107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1894069107
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.3639010285
Short name T756
Test name
Test status
Simulation time 119754536275 ps
CPU time 456.83 seconds
Started Apr 02 01:58:41 PM PDT 24
Finished Apr 02 02:06:18 PM PDT 24
Peak memory 202260 kb
Host smart-6315e12f-3833-4553-97a0-9e447edccece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639010285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3639010285
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.2322614526
Short name T8
Test name
Test status
Simulation time 26531146190 ps
CPU time 31.53 seconds
Started Apr 02 01:58:43 PM PDT 24
Finished Apr 02 01:59:15 PM PDT 24
Peak memory 201624 kb
Host smart-edd55be9-ce16-413f-8967-c9b7df4f576e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322614526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.2322614526
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3404225387
Short name T481
Test name
Test status
Simulation time 5341780382 ps
CPU time 13.79 seconds
Started Apr 02 01:58:39 PM PDT 24
Finished Apr 02 01:58:53 PM PDT 24
Peak memory 201636 kb
Host smart-34bfe82c-6d99-491b-99a8-89a6d7a3a56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404225387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3404225387
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.1090226069
Short name T452
Test name
Test status
Simulation time 5764475066 ps
CPU time 13.05 seconds
Started Apr 02 01:58:25 PM PDT 24
Finished Apr 02 01:58:38 PM PDT 24
Peak memory 201684 kb
Host smart-a9c2870b-877d-4cbb-81f4-ae6273bf9e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090226069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.1090226069
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.896141571
Short name T639
Test name
Test status
Simulation time 166975206119 ps
CPU time 483.69 seconds
Started Apr 02 01:58:45 PM PDT 24
Finished Apr 02 02:06:49 PM PDT 24
Peak memory 211444 kb
Host smart-a659cb98-d69c-40c5-8b74-6a1cadb8625a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896141571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.
896141571
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2875198455
Short name T734
Test name
Test status
Simulation time 449414294 ps
CPU time 1.56 seconds
Started Apr 02 01:59:00 PM PDT 24
Finished Apr 02 01:59:01 PM PDT 24
Peak memory 201564 kb
Host smart-3e433b28-f2f0-4c3c-8851-713d312053a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875198455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2875198455
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.3559341907
Short name T162
Test name
Test status
Simulation time 561208059794 ps
CPU time 100.63 seconds
Started Apr 02 01:58:52 PM PDT 24
Finished Apr 02 02:00:32 PM PDT 24
Peak memory 201880 kb
Host smart-c2bcbeab-76c2-47ca-b44a-8cde499f49d2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559341907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.3559341907
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.2222740956
Short name T319
Test name
Test status
Simulation time 326786202681 ps
CPU time 198.36 seconds
Started Apr 02 01:58:49 PM PDT 24
Finished Apr 02 02:02:08 PM PDT 24
Peak memory 201956 kb
Host smart-3c37c5d9-bb1a-425a-a64a-ff16d2d76d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222740956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.2222740956
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.4000327116
Short name T540
Test name
Test status
Simulation time 326812513844 ps
CPU time 177.43 seconds
Started Apr 02 01:58:49 PM PDT 24
Finished Apr 02 02:01:47 PM PDT 24
Peak memory 201804 kb
Host smart-270ea1b7-6859-4a70-800d-b070d67ba744
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000327116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.4000327116
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.678320401
Short name T795
Test name
Test status
Simulation time 486003277042 ps
CPU time 1039.64 seconds
Started Apr 02 01:58:50 PM PDT 24
Finished Apr 02 02:16:10 PM PDT 24
Peak memory 201888 kb
Host smart-585a82ad-45bb-4669-93aa-a4bab13126f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678320401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.678320401
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.1415227477
Short name T581
Test name
Test status
Simulation time 328805043489 ps
CPU time 775.8 seconds
Started Apr 02 01:58:49 PM PDT 24
Finished Apr 02 02:11:46 PM PDT 24
Peak memory 201848 kb
Host smart-ff3549aa-c428-4065-ba9c-ebda9846270e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415227477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.1415227477
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.817119475
Short name T135
Test name
Test status
Simulation time 175382148270 ps
CPU time 376.2 seconds
Started Apr 02 01:58:48 PM PDT 24
Finished Apr 02 02:05:05 PM PDT 24
Peak memory 201924 kb
Host smart-4b97782d-c2f7-4b4a-8d1b-1ef251616868
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817119475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.817119475
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1027855146
Short name T393
Test name
Test status
Simulation time 391166640532 ps
CPU time 240.58 seconds
Started Apr 02 01:58:53 PM PDT 24
Finished Apr 02 02:02:53 PM PDT 24
Peak memory 201968 kb
Host smart-71d3399a-83cc-4e45-994d-79e26041b17e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027855146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1027855146
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.146697585
Short name T566
Test name
Test status
Simulation time 71372514326 ps
CPU time 390.8 seconds
Started Apr 02 01:58:56 PM PDT 24
Finished Apr 02 02:05:27 PM PDT 24
Peak memory 202160 kb
Host smart-e9b57df8-97de-4ba5-b7a5-d8a15d30139a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146697585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.146697585
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2143906953
Short name T357
Test name
Test status
Simulation time 39371655182 ps
CPU time 89.63 seconds
Started Apr 02 01:58:57 PM PDT 24
Finished Apr 02 02:00:26 PM PDT 24
Peak memory 201688 kb
Host smart-82004356-4c8e-4bd1-bef2-4bbd50eb5696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143906953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2143906953
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.265016682
Short name T565
Test name
Test status
Simulation time 3582607778 ps
CPU time 9.12 seconds
Started Apr 02 01:58:52 PM PDT 24
Finished Apr 02 01:59:01 PM PDT 24
Peak memory 201724 kb
Host smart-4e14da48-d5fe-4eda-8d66-f2766fd91c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265016682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.265016682
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2587492510
Short name T372
Test name
Test status
Simulation time 5917289002 ps
CPU time 14.66 seconds
Started Apr 02 01:58:48 PM PDT 24
Finished Apr 02 01:59:03 PM PDT 24
Peak memory 201688 kb
Host smart-fb7e6f53-6b84-4472-ad37-074a7a0115b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587492510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2587492510
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3466294112
Short name T23
Test name
Test status
Simulation time 112413937186 ps
CPU time 202.3 seconds
Started Apr 02 01:58:57 PM PDT 24
Finished Apr 02 02:02:19 PM PDT 24
Peak memory 210516 kb
Host smart-30e2cf70-87f5-47b0-a850-d4682acf6c23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466294112 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.3466294112
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.80194559
Short name T387
Test name
Test status
Simulation time 348599305 ps
CPU time 1.47 seconds
Started Apr 02 01:59:17 PM PDT 24
Finished Apr 02 01:59:19 PM PDT 24
Peak memory 201500 kb
Host smart-ccd3178f-7e83-4836-a617-414445f1d59f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80194559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.80194559
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.2060616485
Short name T193
Test name
Test status
Simulation time 495382765277 ps
CPU time 251.9 seconds
Started Apr 02 01:59:07 PM PDT 24
Finished Apr 02 02:03:19 PM PDT 24
Peak memory 201912 kb
Host smart-17a80978-e766-4c87-812c-3d690ccb6ce2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060616485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.2060616485
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.783136395
Short name T314
Test name
Test status
Simulation time 327599075092 ps
CPU time 721.21 seconds
Started Apr 02 01:59:04 PM PDT 24
Finished Apr 02 02:11:05 PM PDT 24
Peak memory 201880 kb
Host smart-f1d0374f-49ac-42de-b4ff-6bef0020c78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783136395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.783136395
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.4261465625
Short name T584
Test name
Test status
Simulation time 325682401686 ps
CPU time 233.48 seconds
Started Apr 02 01:59:08 PM PDT 24
Finished Apr 02 02:03:01 PM PDT 24
Peak memory 201860 kb
Host smart-d6f10c00-e842-4bd5-a28e-386b93c38ae1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261465625 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.4261465625
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.129259534
Short name T471
Test name
Test status
Simulation time 163307080371 ps
CPU time 40.43 seconds
Started Apr 02 01:59:04 PM PDT 24
Finished Apr 02 01:59:45 PM PDT 24
Peak memory 201988 kb
Host smart-bd5ebb2f-6e20-4552-a477-dd28894ebe7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129259534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.129259534
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.840673519
Short name T426
Test name
Test status
Simulation time 489067231207 ps
CPU time 1051.64 seconds
Started Apr 02 01:59:04 PM PDT 24
Finished Apr 02 02:16:37 PM PDT 24
Peak memory 201800 kb
Host smart-1955e5a3-6877-4f43-b7d7-9ab5e80c2216
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=840673519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixe
d.840673519
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.2875743282
Short name T207
Test name
Test status
Simulation time 227312431886 ps
CPU time 120.02 seconds
Started Apr 02 01:59:08 PM PDT 24
Finished Apr 02 02:01:09 PM PDT 24
Peak memory 201800 kb
Host smart-66c2de54-8b6b-4c9e-bc54-f71e8e1ff7d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875743282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.2875743282
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1645698378
Short name T634
Test name
Test status
Simulation time 392622106458 ps
CPU time 943.75 seconds
Started Apr 02 01:59:08 PM PDT 24
Finished Apr 02 02:14:52 PM PDT 24
Peak memory 201892 kb
Host smart-47c76a40-987a-4c7a-b439-ab80b806ee44
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645698378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1645698378
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.251391843
Short name T763
Test name
Test status
Simulation time 127193376928 ps
CPU time 487.41 seconds
Started Apr 02 01:59:12 PM PDT 24
Finished Apr 02 02:07:20 PM PDT 24
Peak memory 202196 kb
Host smart-8f39c960-c7ff-482c-881c-693e01992553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251391843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.251391843
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1746335883
Short name T364
Test name
Test status
Simulation time 40255146655 ps
CPU time 24.71 seconds
Started Apr 02 01:59:16 PM PDT 24
Finished Apr 02 01:59:41 PM PDT 24
Peak memory 201648 kb
Host smart-97fd8c2a-ad51-470b-8e1f-2b23d9f48aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746335883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1746335883
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1037225122
Short name T475
Test name
Test status
Simulation time 5198176924 ps
CPU time 3.84 seconds
Started Apr 02 01:59:11 PM PDT 24
Finished Apr 02 01:59:15 PM PDT 24
Peak memory 201708 kb
Host smart-70502e15-2d0f-4d2e-b931-6abd26f874fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037225122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1037225122
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1613213164
Short name T645
Test name
Test status
Simulation time 5668894876 ps
CPU time 2.51 seconds
Started Apr 02 01:59:01 PM PDT 24
Finished Apr 02 01:59:04 PM PDT 24
Peak memory 201668 kb
Host smart-a5ce1633-f3e8-4520-8378-69f517732cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613213164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1613213164
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2341103790
Short name T785
Test name
Test status
Simulation time 117171550022 ps
CPU time 359.37 seconds
Started Apr 02 01:59:16 PM PDT 24
Finished Apr 02 02:05:16 PM PDT 24
Peak memory 202164 kb
Host smart-c00c6cdb-ab15-47b1-bc28-662aa98e93b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341103790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2341103790
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1863397890
Short name T19
Test name
Test status
Simulation time 374797140733 ps
CPU time 408.54 seconds
Started Apr 02 01:59:17 PM PDT 24
Finished Apr 02 02:06:06 PM PDT 24
Peak memory 210504 kb
Host smart-82a9d198-1efb-40a1-95d3-4bbc3d605e63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863397890 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1863397890
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3927725974
Short name T627
Test name
Test status
Simulation time 457725109 ps
CPU time 1.63 seconds
Started Apr 02 01:59:26 PM PDT 24
Finished Apr 02 01:59:28 PM PDT 24
Peak memory 201616 kb
Host smart-0039fb33-b9ff-4d61-a463-2793d9d1d5ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927725974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3927725974
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.3440701581
Short name T173
Test name
Test status
Simulation time 518413444483 ps
CPU time 553.13 seconds
Started Apr 02 01:59:22 PM PDT 24
Finished Apr 02 02:08:35 PM PDT 24
Peak memory 201820 kb
Host smart-16aca52e-bc85-44da-ae61-aeeb8e2f8895
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440701581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.3440701581
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.3960602198
Short name T187
Test name
Test status
Simulation time 496280064729 ps
CPU time 557.48 seconds
Started Apr 02 01:59:22 PM PDT 24
Finished Apr 02 02:08:40 PM PDT 24
Peak memory 201880 kb
Host smart-01c412cd-9380-4c20-be64-011fbefd1ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960602198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3960602198
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.299376635
Short name T222
Test name
Test status
Simulation time 321752054378 ps
CPU time 191.06 seconds
Started Apr 02 01:59:18 PM PDT 24
Finished Apr 02 02:02:31 PM PDT 24
Peak memory 201884 kb
Host smart-866e233f-3eb0-4673-9456-76e0afc6f962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299376635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.299376635
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1421022318
Short name T206
Test name
Test status
Simulation time 331162229589 ps
CPU time 405.01 seconds
Started Apr 02 01:59:19 PM PDT 24
Finished Apr 02 02:06:05 PM PDT 24
Peak memory 201796 kb
Host smart-04a27071-34d6-43e0-aeae-015857e656c3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421022318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1421022318
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3403691899
Short name T293
Test name
Test status
Simulation time 325752874812 ps
CPU time 372.35 seconds
Started Apr 02 01:59:16 PM PDT 24
Finished Apr 02 02:05:29 PM PDT 24
Peak memory 201928 kb
Host smart-0addcaaa-b7da-4ec3-aca3-52a93b4036a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403691899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3403691899
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.2152104628
Short name T733
Test name
Test status
Simulation time 166453103812 ps
CPU time 202.4 seconds
Started Apr 02 01:59:20 PM PDT 24
Finished Apr 02 02:02:42 PM PDT 24
Peak memory 201768 kb
Host smart-74fc0eb3-b7fc-4ef2-b86d-bf102cc014c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152104628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.2152104628
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.2738789309
Short name T260
Test name
Test status
Simulation time 627393916110 ps
CPU time 274.07 seconds
Started Apr 02 01:59:19 PM PDT 24
Finished Apr 02 02:03:54 PM PDT 24
Peak memory 201876 kb
Host smart-dc667ab9-535d-4486-9bab-db8660e6156e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738789309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.2738789309
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.1120970583
Short name T586
Test name
Test status
Simulation time 392968817367 ps
CPU time 480.57 seconds
Started Apr 02 01:59:24 PM PDT 24
Finished Apr 02 02:07:24 PM PDT 24
Peak memory 201876 kb
Host smart-44daf77d-e8bb-4111-891a-38cb7fa8c0b5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120970583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.1120970583
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.827254470
Short name T470
Test name
Test status
Simulation time 22479206795 ps
CPU time 13.6 seconds
Started Apr 02 01:59:24 PM PDT 24
Finished Apr 02 01:59:38 PM PDT 24
Peak memory 201716 kb
Host smart-28001126-2553-4d8b-82d6-9a4013c6b423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827254470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.827254470
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.3414476689
Short name T383
Test name
Test status
Simulation time 3670715964 ps
CPU time 9.75 seconds
Started Apr 02 01:59:23 PM PDT 24
Finished Apr 02 01:59:33 PM PDT 24
Peak memory 201672 kb
Host smart-af23d581-9421-4877-a5b5-ae38a02cb694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414476689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.3414476689
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3942618611
Short name T477
Test name
Test status
Simulation time 5924504465 ps
CPU time 12.92 seconds
Started Apr 02 01:59:15 PM PDT 24
Finished Apr 02 01:59:28 PM PDT 24
Peak memory 201716 kb
Host smart-70d5877d-fea8-4fae-8d3b-174f5dfe2f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942618611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3942618611
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3037276843
Short name T230
Test name
Test status
Simulation time 212946151006 ps
CPU time 505.99 seconds
Started Apr 02 01:59:28 PM PDT 24
Finished Apr 02 02:07:54 PM PDT 24
Peak memory 201920 kb
Host smart-de11fc5e-9709-4ea7-8e3a-77fec7d17445
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037276843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3037276843
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2598243960
Short name T661
Test name
Test status
Simulation time 383956274 ps
CPU time 1.51 seconds
Started Apr 02 01:59:46 PM PDT 24
Finished Apr 02 01:59:48 PM PDT 24
Peak memory 201612 kb
Host smart-1648915d-3396-455e-9efb-9168e5ab9359
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598243960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2598243960
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.3290741208
Short name T335
Test name
Test status
Simulation time 330469618656 ps
CPU time 710.34 seconds
Started Apr 02 01:59:31 PM PDT 24
Finished Apr 02 02:11:22 PM PDT 24
Peak memory 201952 kb
Host smart-0448617f-f926-4518-966b-37fbed095206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290741208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.3290741208
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.865813580
Short name T166
Test name
Test status
Simulation time 163429685403 ps
CPU time 203.88 seconds
Started Apr 02 01:59:35 PM PDT 24
Finished Apr 02 02:02:59 PM PDT 24
Peak memory 201828 kb
Host smart-b675f407-7e1e-49fd-8427-4a55dfc86254
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=865813580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrup
t_fixed.865813580
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.1359634981
Short name T146
Test name
Test status
Simulation time 482642294721 ps
CPU time 192.12 seconds
Started Apr 02 01:59:27 PM PDT 24
Finished Apr 02 02:02:39 PM PDT 24
Peak memory 201924 kb
Host smart-5d6210a1-3470-4a70-a41c-6cce0d3d548c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359634981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.1359634981
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1665693673
Short name T476
Test name
Test status
Simulation time 166465115211 ps
CPU time 373.71 seconds
Started Apr 02 01:59:30 PM PDT 24
Finished Apr 02 02:05:44 PM PDT 24
Peak memory 201944 kb
Host smart-e3afc0c8-4869-4a59-a6a1-dbc449dfec65
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665693673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1665693673
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3498084883
Short name T157
Test name
Test status
Simulation time 362984080514 ps
CPU time 807.92 seconds
Started Apr 02 01:59:35 PM PDT 24
Finished Apr 02 02:13:03 PM PDT 24
Peak memory 201908 kb
Host smart-18fccc4e-22b9-42db-bd90-c6553e487e5c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498084883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3498084883
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.407494015
Short name T550
Test name
Test status
Simulation time 207306000073 ps
CPU time 241.17 seconds
Started Apr 02 01:59:34 PM PDT 24
Finished Apr 02 02:03:35 PM PDT 24
Peak memory 201868 kb
Host smart-d6299183-0baa-4a11-9854-1428f7ae187e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407494015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
adc_ctrl_filters_wakeup_fixed.407494015
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.132240329
Short name T522
Test name
Test status
Simulation time 79418314546 ps
CPU time 402.88 seconds
Started Apr 02 01:59:42 PM PDT 24
Finished Apr 02 02:06:25 PM PDT 24
Peak memory 202092 kb
Host smart-b0989f21-3723-46b6-afaa-cc9d60bcb4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132240329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.132240329
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2913322
Short name T401
Test name
Test status
Simulation time 25279088178 ps
CPU time 14.2 seconds
Started Apr 02 01:59:38 PM PDT 24
Finished Apr 02 01:59:53 PM PDT 24
Peak memory 201696 kb
Host smart-27937ef4-8cd1-4654-bc83-a7a10f7fd10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2913322
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.3136606445
Short name T660
Test name
Test status
Simulation time 4434381716 ps
CPU time 5.66 seconds
Started Apr 02 01:59:38 PM PDT 24
Finished Apr 02 01:59:44 PM PDT 24
Peak memory 201684 kb
Host smart-db88b53a-1a59-4c03-ad0f-b727b832f6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136606445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.3136606445
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2426747299
Short name T132
Test name
Test status
Simulation time 5959648255 ps
CPU time 1.97 seconds
Started Apr 02 01:59:27 PM PDT 24
Finished Apr 02 01:59:29 PM PDT 24
Peak memory 201712 kb
Host smart-04210074-2e17-4acc-88f6-4abfb7e9b69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426747299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2426747299
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.2460651411
Short name T232
Test name
Test status
Simulation time 197742667473 ps
CPU time 421.72 seconds
Started Apr 02 01:59:42 PM PDT 24
Finished Apr 02 02:06:44 PM PDT 24
Peak memory 201924 kb
Host smart-338c2e2c-72c5-404a-9ac5-e4f320c49552
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460651411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.2460651411
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.3376351400
Short name T35
Test name
Test status
Simulation time 52857722367 ps
CPU time 68.75 seconds
Started Apr 02 01:59:41 PM PDT 24
Finished Apr 02 02:00:50 PM PDT 24
Peak memory 210524 kb
Host smart-d1dc5c6c-131d-466f-a508-991bf73db363
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376351400 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.3376351400
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.3296540108
Short name T741
Test name
Test status
Simulation time 470908296 ps
CPU time 1.41 seconds
Started Apr 02 01:51:35 PM PDT 24
Finished Apr 02 01:51:37 PM PDT 24
Peak memory 201572 kb
Host smart-15e309e1-358b-489d-a4f7-9f74225bc91b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296540108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.3296540108
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.4257895059
Short name T290
Test name
Test status
Simulation time 511550690516 ps
CPU time 968.74 seconds
Started Apr 02 01:51:30 PM PDT 24
Finished Apr 02 02:07:40 PM PDT 24
Peak memory 201908 kb
Host smart-86c84de1-b811-4ee4-a2a1-48c7cace836e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257895059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.4257895059
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.4259507209
Short name T259
Test name
Test status
Simulation time 371725194436 ps
CPU time 421.11 seconds
Started Apr 02 01:51:33 PM PDT 24
Finished Apr 02 01:58:34 PM PDT 24
Peak memory 201836 kb
Host smart-ff292292-0bb4-4e10-a7a1-cc2f7b50a593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259507209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.4259507209
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.958120692
Short name T626
Test name
Test status
Simulation time 327330632653 ps
CPU time 740.27 seconds
Started Apr 02 01:51:30 PM PDT 24
Finished Apr 02 02:03:50 PM PDT 24
Peak memory 201800 kb
Host smart-38f4414e-de30-42c6-9855-8d14d53df80d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=958120692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt
_fixed.958120692
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3335238691
Short name T68
Test name
Test status
Simulation time 163379301576 ps
CPU time 58.28 seconds
Started Apr 02 01:51:33 PM PDT 24
Finished Apr 02 01:52:31 PM PDT 24
Peak memory 201824 kb
Host smart-066a2ce9-7f40-4973-bfc6-67e1d95670b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335238691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3335238691
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1752341916
Short name T781
Test name
Test status
Simulation time 162996576014 ps
CPU time 338.85 seconds
Started Apr 02 01:51:33 PM PDT 24
Finished Apr 02 01:57:12 PM PDT 24
Peak memory 201896 kb
Host smart-f053eebc-c8fd-44e9-ae4a-efb51937641a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752341916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1752341916
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1286475195
Short name T261
Test name
Test status
Simulation time 529720979667 ps
CPU time 1183.35 seconds
Started Apr 02 01:51:30 PM PDT 24
Finished Apr 02 02:11:14 PM PDT 24
Peak memory 202000 kb
Host smart-b600de76-f039-4f91-a8c8-19768ead6744
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286475195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1286475195
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2219387494
Short name T204
Test name
Test status
Simulation time 408132699483 ps
CPU time 278.42 seconds
Started Apr 02 01:51:32 PM PDT 24
Finished Apr 02 01:56:10 PM PDT 24
Peak memory 201892 kb
Host smart-0845649b-1c51-42f4-9368-931948a26511
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219387494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2219387494
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.461841384
Short name T494
Test name
Test status
Simulation time 31444590896 ps
CPU time 12.34 seconds
Started Apr 02 01:51:32 PM PDT 24
Finished Apr 02 01:51:44 PM PDT 24
Peak memory 201720 kb
Host smart-4aea7446-7f7b-4119-8e86-5e53d712f998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461841384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.461841384
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3607822623
Short name T177
Test name
Test status
Simulation time 3178950529 ps
CPU time 8.13 seconds
Started Apr 02 01:51:33 PM PDT 24
Finished Apr 02 01:51:41 PM PDT 24
Peak memory 201688 kb
Host smart-0df5b853-3b36-45e8-8e7f-d09fe30a5fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607822623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3607822623
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.1487684580
Short name T57
Test name
Test status
Simulation time 8278960807 ps
CPU time 19.22 seconds
Started Apr 02 01:51:33 PM PDT 24
Finished Apr 02 01:51:52 PM PDT 24
Peak memory 218432 kb
Host smart-8f67db31-8388-41cf-b619-c60f84e41c21
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487684580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.1487684580
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.1912553222
Short name T697
Test name
Test status
Simulation time 6300773128 ps
CPU time 4.14 seconds
Started Apr 02 01:51:30 PM PDT 24
Finished Apr 02 01:51:34 PM PDT 24
Peak memory 201660 kb
Host smart-9373e64e-f7f7-493e-8a3a-43ef68fb7385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912553222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1912553222
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.3178129121
Short name T790
Test name
Test status
Simulation time 159745134048 ps
CPU time 95.36 seconds
Started Apr 02 01:51:35 PM PDT 24
Finished Apr 02 01:53:11 PM PDT 24
Peak memory 201800 kb
Host smart-3ad6efca-1e83-490c-8162-9bd835bdeff2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178129121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
3178129121
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3418327680
Short name T682
Test name
Test status
Simulation time 499099141 ps
CPU time 1.7 seconds
Started Apr 02 02:00:03 PM PDT 24
Finished Apr 02 02:00:05 PM PDT 24
Peak memory 201572 kb
Host smart-90f7b8c5-90d5-491a-8884-8949b84a8987
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418327680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3418327680
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.3976809505
Short name T246
Test name
Test status
Simulation time 328234150626 ps
CPU time 400.84 seconds
Started Apr 02 01:59:53 PM PDT 24
Finished Apr 02 02:06:34 PM PDT 24
Peak memory 201872 kb
Host smart-10312450-954f-46a2-8915-dad994744957
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976809505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.3976809505
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1808232474
Short name T615
Test name
Test status
Simulation time 166994006294 ps
CPU time 358.3 seconds
Started Apr 02 01:59:51 PM PDT 24
Finished Apr 02 02:05:50 PM PDT 24
Peak memory 201880 kb
Host smart-a86691b6-e1dc-4594-aac9-ee6c0bed909c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808232474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1808232474
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.203608135
Short name T417
Test name
Test status
Simulation time 161608520261 ps
CPU time 368.62 seconds
Started Apr 02 01:59:50 PM PDT 24
Finished Apr 02 02:05:59 PM PDT 24
Peak memory 201940 kb
Host smart-5a75c80d-6d92-4a7a-8616-c3a322f6ef6f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=203608135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.203608135
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.333609957
Short name T318
Test name
Test status
Simulation time 170300001044 ps
CPU time 58.36 seconds
Started Apr 02 01:59:46 PM PDT 24
Finished Apr 02 02:00:45 PM PDT 24
Peak memory 201888 kb
Host smart-d36cdc14-119e-4e95-be14-8d7b08b89eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333609957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.333609957
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.1064495229
Short name T681
Test name
Test status
Simulation time 482256253961 ps
CPU time 1083.97 seconds
Started Apr 02 01:59:50 PM PDT 24
Finished Apr 02 02:17:55 PM PDT 24
Peak memory 201808 kb
Host smart-4f478dc8-76a4-4f65-be30-920618126d0b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064495229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.1064495229
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3937077613
Short name T338
Test name
Test status
Simulation time 184657685685 ps
CPU time 115.24 seconds
Started Apr 02 01:59:55 PM PDT 24
Finished Apr 02 02:01:51 PM PDT 24
Peak memory 201816 kb
Host smart-976369e6-19e7-488b-a0f9-268d5e8e2f97
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937077613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3937077613
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2893569330
Short name T735
Test name
Test status
Simulation time 400192996967 ps
CPU time 807.79 seconds
Started Apr 02 01:59:54 PM PDT 24
Finished Apr 02 02:13:22 PM PDT 24
Peak memory 201868 kb
Host smart-3b1618e9-6091-4459-bdeb-1a927ab034c0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893569330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2893569330
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.4104689919
Short name T41
Test name
Test status
Simulation time 90903005437 ps
CPU time 462.58 seconds
Started Apr 02 02:00:01 PM PDT 24
Finished Apr 02 02:07:44 PM PDT 24
Peak memory 202128 kb
Host smart-ab3edb3a-d358-4b99-993d-d8d470c4c370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104689919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.4104689919
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2613363601
Short name T360
Test name
Test status
Simulation time 30259163082 ps
CPU time 38.25 seconds
Started Apr 02 01:59:58 PM PDT 24
Finished Apr 02 02:00:37 PM PDT 24
Peak memory 201720 kb
Host smart-6b937dfa-a58f-43bd-bf11-52663f7f1dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613363601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2613363601
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.623662488
Short name T459
Test name
Test status
Simulation time 3166602634 ps
CPU time 4.84 seconds
Started Apr 02 01:59:56 PM PDT 24
Finished Apr 02 02:00:01 PM PDT 24
Peak memory 201668 kb
Host smart-9ead629a-c386-40fd-b351-db82805aa9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623662488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.623662488
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.1483624942
Short name T190
Test name
Test status
Simulation time 5813031778 ps
CPU time 14.56 seconds
Started Apr 02 01:59:46 PM PDT 24
Finished Apr 02 02:00:01 PM PDT 24
Peak memory 201664 kb
Host smart-0a08615d-78ec-4d64-91d5-e6bd0f5e950a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483624942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1483624942
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.2468529961
Short name T663
Test name
Test status
Simulation time 175429993913 ps
CPU time 389.52 seconds
Started Apr 02 02:00:01 PM PDT 24
Finished Apr 02 02:06:31 PM PDT 24
Peak memory 201880 kb
Host smart-777e9d24-953c-49d1-97cc-29d2b8e43f9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468529961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.2468529961
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3122802307
Short name T89
Test name
Test status
Simulation time 18368091731 ps
CPU time 32.08 seconds
Started Apr 02 02:00:02 PM PDT 24
Finished Apr 02 02:00:34 PM PDT 24
Peak memory 202068 kb
Host smart-e4b7303e-7e84-4aa1-bd4b-dc36a158ab81
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122802307 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3122802307
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.562561749
Short name T369
Test name
Test status
Simulation time 395922055 ps
CPU time 1.58 seconds
Started Apr 02 02:00:17 PM PDT 24
Finished Apr 02 02:00:19 PM PDT 24
Peak memory 201572 kb
Host smart-c94e5688-f8ed-48f1-adc7-71dd3382c76f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562561749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.562561749
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.206680433
Short name T83
Test name
Test status
Simulation time 326738850555 ps
CPU time 187.67 seconds
Started Apr 02 02:00:07 PM PDT 24
Finished Apr 02 02:03:15 PM PDT 24
Peak memory 201872 kb
Host smart-158371fd-6b63-47aa-ab31-b90ca8b0867a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206680433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.206680433
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.172867004
Short name T510
Test name
Test status
Simulation time 166357286169 ps
CPU time 99.53 seconds
Started Apr 02 02:00:07 PM PDT 24
Finished Apr 02 02:01:47 PM PDT 24
Peak memory 201840 kb
Host smart-40f4e208-c211-492a-a921-53e57fedfa47
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=172867004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrup
t_fixed.172867004
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.64675797
Short name T521
Test name
Test status
Simulation time 328093358156 ps
CPU time 196.84 seconds
Started Apr 02 02:00:02 PM PDT 24
Finished Apr 02 02:03:19 PM PDT 24
Peak memory 201928 kb
Host smart-8d1413e3-5420-47dc-97a4-790033d22ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64675797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.64675797
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3662983907
Short name T509
Test name
Test status
Simulation time 156957971007 ps
CPU time 377.65 seconds
Started Apr 02 02:00:05 PM PDT 24
Finished Apr 02 02:06:22 PM PDT 24
Peak memory 201884 kb
Host smart-06a94196-ce2c-4b70-8fdc-1a1651d6561e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662983907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3662983907
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.3165440747
Short name T191
Test name
Test status
Simulation time 355093700851 ps
CPU time 770.61 seconds
Started Apr 02 02:00:10 PM PDT 24
Finished Apr 02 02:13:01 PM PDT 24
Peak memory 201888 kb
Host smart-80b91680-3062-4b6b-bedf-4b29dabb08f0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165440747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.3165440747
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.4294564073
Short name T445
Test name
Test status
Simulation time 190594382151 ps
CPU time 122.39 seconds
Started Apr 02 02:00:10 PM PDT 24
Finished Apr 02 02:02:13 PM PDT 24
Peak memory 201852 kb
Host smart-ecf2fd5e-42cb-4d35-9e78-099a3f80c204
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294564073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.4294564073
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.2040723959
Short name T650
Test name
Test status
Simulation time 118327307163 ps
CPU time 642.26 seconds
Started Apr 02 02:00:18 PM PDT 24
Finished Apr 02 02:11:00 PM PDT 24
Peak memory 202212 kb
Host smart-931c855a-a9be-438d-b92f-21d6dea8506a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040723959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2040723959
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.602874353
Short name T414
Test name
Test status
Simulation time 40495396363 ps
CPU time 43.48 seconds
Started Apr 02 02:00:18 PM PDT 24
Finished Apr 02 02:01:02 PM PDT 24
Peak memory 201672 kb
Host smart-140ad9f3-ef9a-4ad4-a302-f5aaff0c8cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602874353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.602874353
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.962218013
Short name T456
Test name
Test status
Simulation time 3579444786 ps
CPU time 8.95 seconds
Started Apr 02 02:00:13 PM PDT 24
Finished Apr 02 02:00:22 PM PDT 24
Peak memory 201744 kb
Host smart-81a74873-e55a-4898-a86f-3c59455840df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962218013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.962218013
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.3737306144
Short name T633
Test name
Test status
Simulation time 5542537140 ps
CPU time 12.93 seconds
Started Apr 02 02:00:01 PM PDT 24
Finished Apr 02 02:00:14 PM PDT 24
Peak memory 201708 kb
Host smart-d625ba1e-ce87-4119-83ad-30724af9213b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737306144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3737306144
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.1133619476
Short name T24
Test name
Test status
Simulation time 268113464194 ps
CPU time 639.84 seconds
Started Apr 02 02:00:20 PM PDT 24
Finished Apr 02 02:10:59 PM PDT 24
Peak memory 210812 kb
Host smart-98574083-45d3-44dc-b507-e1719a02e951
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133619476 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.1133619476
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.527915564
Short name T433
Test name
Test status
Simulation time 301086389 ps
CPU time 1 seconds
Started Apr 02 02:00:27 PM PDT 24
Finished Apr 02 02:00:28 PM PDT 24
Peak memory 201496 kb
Host smart-6360c248-237d-4f3c-a1f2-bff9e3284901
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527915564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.527915564
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.4271605193
Short name T255
Test name
Test status
Simulation time 163621898185 ps
CPU time 31.61 seconds
Started Apr 02 02:00:23 PM PDT 24
Finished Apr 02 02:00:55 PM PDT 24
Peak memory 201912 kb
Host smart-faf2ca56-291b-4562-8288-342a6e3f105c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271605193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.4271605193
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3575420391
Short name T151
Test name
Test status
Simulation time 360603437611 ps
CPU time 874.77 seconds
Started Apr 02 02:00:23 PM PDT 24
Finished Apr 02 02:14:58 PM PDT 24
Peak memory 201948 kb
Host smart-c0416508-c0eb-4f49-8b71-0f4e3d457e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575420391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3575420391
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.2378325301
Short name T551
Test name
Test status
Simulation time 484027956826 ps
CPU time 596.5 seconds
Started Apr 02 02:00:25 PM PDT 24
Finished Apr 02 02:10:21 PM PDT 24
Peak memory 201888 kb
Host smart-66176cec-30aa-4eaf-b49e-9c9660e64998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378325301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2378325301
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1893639510
Short name T535
Test name
Test status
Simulation time 324445192367 ps
CPU time 394.36 seconds
Started Apr 02 02:00:24 PM PDT 24
Finished Apr 02 02:06:59 PM PDT 24
Peak memory 201880 kb
Host smart-0f96e395-df62-4c8e-83fa-6bbf742b6e5e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893639510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1893639510
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1653320241
Short name T413
Test name
Test status
Simulation time 162903771211 ps
CPU time 60.02 seconds
Started Apr 02 02:00:23 PM PDT 24
Finished Apr 02 02:01:23 PM PDT 24
Peak memory 201944 kb
Host smart-1fc5660c-1d3f-4614-aa5a-81fd03233585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653320241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1653320241
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.3562921148
Short name T796
Test name
Test status
Simulation time 491619016670 ps
CPU time 1154.48 seconds
Started Apr 02 02:00:24 PM PDT 24
Finished Apr 02 02:19:39 PM PDT 24
Peak memory 201788 kb
Host smart-4de15d01-b816-430d-8ba4-de845750e890
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562921148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.3562921148
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3097331135
Short name T14
Test name
Test status
Simulation time 390994393547 ps
CPU time 472.98 seconds
Started Apr 02 02:00:26 PM PDT 24
Finished Apr 02 02:08:19 PM PDT 24
Peak memory 201876 kb
Host smart-f752d621-9054-42a4-8b59-791b0b1538f9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097331135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3097331135
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2772327231
Short name T629
Test name
Test status
Simulation time 91976114873 ps
CPU time 466.41 seconds
Started Apr 02 02:00:28 PM PDT 24
Finished Apr 02 02:08:14 PM PDT 24
Peak memory 202168 kb
Host smart-e43c450e-edf7-4553-b6c6-520dc064dc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772327231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2772327231
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.351194986
Short name T80
Test name
Test status
Simulation time 27952710548 ps
CPU time 20.94 seconds
Started Apr 02 02:00:27 PM PDT 24
Finished Apr 02 02:00:48 PM PDT 24
Peak memory 201668 kb
Host smart-4f9f2721-0319-4714-af8a-4e035cbf9c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351194986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.351194986
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.1481785028
Short name T368
Test name
Test status
Simulation time 2935865221 ps
CPU time 4.43 seconds
Started Apr 02 02:00:22 PM PDT 24
Finished Apr 02 02:00:27 PM PDT 24
Peak memory 201712 kb
Host smart-7b94112c-040b-43fb-9fac-723d7fbfd86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481785028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1481785028
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3802626764
Short name T732
Test name
Test status
Simulation time 6065543117 ps
CPU time 4.46 seconds
Started Apr 02 02:00:26 PM PDT 24
Finished Apr 02 02:00:31 PM PDT 24
Peak memory 201676 kb
Host smart-c838f423-65b7-4289-b34a-5d38a8cfce6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802626764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3802626764
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3758128226
Short name T772
Test name
Test status
Simulation time 82634720955 ps
CPU time 158.55 seconds
Started Apr 02 02:00:27 PM PDT 24
Finished Apr 02 02:03:06 PM PDT 24
Peak memory 201636 kb
Host smart-e9c277c3-b3aa-4777-a9a2-ab89ba2a484d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758128226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3758128226
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.1754209248
Short name T244
Test name
Test status
Simulation time 89363225093 ps
CPU time 208.18 seconds
Started Apr 02 02:00:27 PM PDT 24
Finished Apr 02 02:03:55 PM PDT 24
Peak memory 218008 kb
Host smart-b86abadb-20d9-4abe-aef9-0af96ad25328
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754209248 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.1754209248
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.1456814141
Short name T714
Test name
Test status
Simulation time 500502830 ps
CPU time 1.69 seconds
Started Apr 02 02:00:44 PM PDT 24
Finished Apr 02 02:00:46 PM PDT 24
Peak memory 201568 kb
Host smart-396a3a36-748c-4b98-898f-d5236796b4b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456814141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1456814141
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.1440337927
Short name T249
Test name
Test status
Simulation time 563396357070 ps
CPU time 526.05 seconds
Started Apr 02 02:00:38 PM PDT 24
Finished Apr 02 02:09:24 PM PDT 24
Peak memory 201912 kb
Host smart-fdd7ce2b-0dbb-44ac-9292-b0e79cf9cfe6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440337927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.1440337927
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1131108587
Short name T243
Test name
Test status
Simulation time 162479863150 ps
CPU time 391.6 seconds
Started Apr 02 02:00:38 PM PDT 24
Finished Apr 02 02:07:10 PM PDT 24
Peak memory 201900 kb
Host smart-6ad572cc-cb0b-4b61-afaa-aa2d291db71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131108587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1131108587
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2770250058
Short name T706
Test name
Test status
Simulation time 322812778286 ps
CPU time 197.59 seconds
Started Apr 02 02:00:35 PM PDT 24
Finished Apr 02 02:03:53 PM PDT 24
Peak memory 201948 kb
Host smart-a44c0775-2b4e-44e1-bec7-451be34b6f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770250058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2770250058
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.3902237190
Short name T205
Test name
Test status
Simulation time 336882484405 ps
CPU time 363.2 seconds
Started Apr 02 02:00:36 PM PDT 24
Finished Apr 02 02:06:39 PM PDT 24
Peak memory 201864 kb
Host smart-69bd8a9d-f4a3-4eba-ab3e-375c40685616
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902237190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.3902237190
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.884942158
Short name T496
Test name
Test status
Simulation time 160972453861 ps
CPU time 354.12 seconds
Started Apr 02 02:00:26 PM PDT 24
Finished Apr 02 02:06:21 PM PDT 24
Peak memory 201952 kb
Host smart-ef42e33c-3cf7-4519-b006-0aef65c85761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884942158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.884942158
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2575298875
Short name T515
Test name
Test status
Simulation time 482868861896 ps
CPU time 528.57 seconds
Started Apr 02 02:00:35 PM PDT 24
Finished Apr 02 02:09:23 PM PDT 24
Peak memory 201876 kb
Host smart-13cd3d6f-9519-43b5-add5-ab9c1607eab7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575298875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2575298875
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2203985772
Short name T153
Test name
Test status
Simulation time 361504751332 ps
CPU time 849.25 seconds
Started Apr 02 02:00:39 PM PDT 24
Finished Apr 02 02:14:48 PM PDT 24
Peak memory 201936 kb
Host smart-07d50c63-d742-46ca-ad14-165437d9c516
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203985772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2203985772
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2303462774
Short name T590
Test name
Test status
Simulation time 605979737164 ps
CPU time 691.46 seconds
Started Apr 02 02:00:40 PM PDT 24
Finished Apr 02 02:12:12 PM PDT 24
Peak memory 201896 kb
Host smart-01163bc6-3407-444f-96a9-465f42b21a19
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303462774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.2303462774
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.3231431103
Short name T530
Test name
Test status
Simulation time 133213841618 ps
CPU time 553.66 seconds
Started Apr 02 02:00:40 PM PDT 24
Finished Apr 02 02:09:54 PM PDT 24
Peak memory 202204 kb
Host smart-08d8b3a3-67ba-430e-95b5-47c0693c13a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231431103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.3231431103
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3568484458
Short name T411
Test name
Test status
Simulation time 26039242440 ps
CPU time 58.77 seconds
Started Apr 02 02:00:40 PM PDT 24
Finished Apr 02 02:01:39 PM PDT 24
Peak memory 201704 kb
Host smart-df814136-58dc-4d1c-a81e-969e67a29ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568484458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3568484458
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.4239265382
Short name T2
Test name
Test status
Simulation time 2923703529 ps
CPU time 7.64 seconds
Started Apr 02 02:00:36 PM PDT 24
Finished Apr 02 02:00:44 PM PDT 24
Peak memory 201680 kb
Host smart-2e188b39-8e7c-46b6-9da0-65fb44d08c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239265382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.4239265382
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3789411900
Short name T725
Test name
Test status
Simulation time 6155446900 ps
CPU time 4.77 seconds
Started Apr 02 02:00:29 PM PDT 24
Finished Apr 02 02:00:34 PM PDT 24
Peak memory 201668 kb
Host smart-3283d303-0912-47d9-ac45-ebb33b323407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789411900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3789411900
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.4223932037
Short name T156
Test name
Test status
Simulation time 275689821265 ps
CPU time 136.11 seconds
Started Apr 02 02:00:42 PM PDT 24
Finished Apr 02 02:02:58 PM PDT 24
Peak memory 210520 kb
Host smart-0061c962-2e06-44a4-9b05-a3a693e33ac3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223932037 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.4223932037
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.760663299
Short name T448
Test name
Test status
Simulation time 420758047 ps
CPU time 1.49 seconds
Started Apr 02 02:01:06 PM PDT 24
Finished Apr 02 02:01:08 PM PDT 24
Peak memory 201552 kb
Host smart-3c368a3b-5402-4cad-a7b0-6d9c8373f57f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760663299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.760663299
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.223048349
Short name T280
Test name
Test status
Simulation time 331564247793 ps
CPU time 421.58 seconds
Started Apr 02 02:00:56 PM PDT 24
Finished Apr 02 02:07:59 PM PDT 24
Peak memory 201896 kb
Host smart-e064a56a-4e40-4c81-bf64-120b01d0eb48
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223048349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gati
ng.223048349
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.3628933462
Short name T154
Test name
Test status
Simulation time 160985637769 ps
CPU time 378.48 seconds
Started Apr 02 02:01:01 PM PDT 24
Finished Apr 02 02:07:20 PM PDT 24
Peak memory 201892 kb
Host smart-f08b45d8-a3d9-4c96-9bdd-ce9d7a604cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628933462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.3628933462
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.4288080165
Short name T789
Test name
Test status
Simulation time 330373001460 ps
CPU time 211.87 seconds
Started Apr 02 02:00:55 PM PDT 24
Finished Apr 02 02:04:27 PM PDT 24
Peak memory 201848 kb
Host smart-a5097838-7b1b-459d-8b6e-3bc06b0b2ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288080165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.4288080165
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1527829343
Short name T439
Test name
Test status
Simulation time 496232232249 ps
CPU time 294.63 seconds
Started Apr 02 02:00:56 PM PDT 24
Finished Apr 02 02:05:52 PM PDT 24
Peak memory 201800 kb
Host smart-8d77f0af-c40e-4142-b7ce-c837dbe3317b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527829343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1527829343
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.651306422
Short name T254
Test name
Test status
Simulation time 162224073676 ps
CPU time 340.28 seconds
Started Apr 02 02:00:51 PM PDT 24
Finished Apr 02 02:06:31 PM PDT 24
Peak memory 201856 kb
Host smart-6e37fa19-edd6-4878-8fbc-9e9df90b17b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651306422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.651306422
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2501947496
Short name T370
Test name
Test status
Simulation time 327721594217 ps
CPU time 174.31 seconds
Started Apr 02 02:00:50 PM PDT 24
Finished Apr 02 02:03:44 PM PDT 24
Peak memory 201884 kb
Host smart-e0b5f1ae-26b4-4817-9a33-006adf1e0b34
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501947496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2501947496
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.413585156
Short name T619
Test name
Test status
Simulation time 198621283391 ps
CPU time 111.85 seconds
Started Apr 02 02:00:56 PM PDT 24
Finished Apr 02 02:02:48 PM PDT 24
Peak memory 201884 kb
Host smart-b220ccf3-f743-4a06-b065-eed4c68f93c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413585156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_
wakeup.413585156
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.3291830432
Short name T85
Test name
Test status
Simulation time 405062211413 ps
CPU time 839.19 seconds
Started Apr 02 02:00:57 PM PDT 24
Finished Apr 02 02:14:57 PM PDT 24
Peak memory 201860 kb
Host smart-3aa99f9a-7a71-48d0-89ff-fdc1e3eea4e5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291830432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.3291830432
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.3806294751
Short name T213
Test name
Test status
Simulation time 114395584222 ps
CPU time 420.69 seconds
Started Apr 02 02:01:01 PM PDT 24
Finished Apr 02 02:08:02 PM PDT 24
Peak memory 202184 kb
Host smart-c2a0d79a-80a3-406e-b575-01b51dc47497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806294751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3806294751
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.2801363194
Short name T563
Test name
Test status
Simulation time 30540703622 ps
CPU time 5.65 seconds
Started Apr 02 02:01:02 PM PDT 24
Finished Apr 02 02:01:08 PM PDT 24
Peak memory 201572 kb
Host smart-89f96ad1-575d-49f0-8923-ef1fb5fef800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801363194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.2801363194
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2007275423
Short name T579
Test name
Test status
Simulation time 3227817693 ps
CPU time 8.15 seconds
Started Apr 02 02:01:00 PM PDT 24
Finished Apr 02 02:01:08 PM PDT 24
Peak memory 201700 kb
Host smart-cc07d4c6-695b-41d4-909f-0452d382ef34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007275423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2007275423
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.3137892236
Short name T557
Test name
Test status
Simulation time 6161162417 ps
CPU time 1.54 seconds
Started Apr 02 02:00:50 PM PDT 24
Finished Apr 02 02:00:52 PM PDT 24
Peak memory 201612 kb
Host smart-06fc2c94-dfcf-4153-b307-8d4edfc3afa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137892236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.3137892236
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.872549311
Short name T20
Test name
Test status
Simulation time 439745853690 ps
CPU time 356.98 seconds
Started Apr 02 02:01:01 PM PDT 24
Finished Apr 02 02:06:59 PM PDT 24
Peak memory 210488 kb
Host smart-21743686-82e1-4633-af50-557e111af149
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872549311 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.872549311
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.1210397847
Short name T517
Test name
Test status
Simulation time 520113695 ps
CPU time 1.18 seconds
Started Apr 02 02:01:17 PM PDT 24
Finished Apr 02 02:01:19 PM PDT 24
Peak memory 201588 kb
Host smart-66d3fb3a-5ab7-4ee9-aa7b-ccf4a118d48d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210397847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1210397847
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2900363549
Short name T197
Test name
Test status
Simulation time 364080610460 ps
CPU time 83.26 seconds
Started Apr 02 02:01:10 PM PDT 24
Finished Apr 02 02:02:33 PM PDT 24
Peak memory 201844 kb
Host smart-9d6a71ae-871b-4ae3-ac84-0f6f112a6a80
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900363549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2900363549
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.4103271203
Short name T270
Test name
Test status
Simulation time 539692720495 ps
CPU time 671.65 seconds
Started Apr 02 02:01:14 PM PDT 24
Finished Apr 02 02:12:26 PM PDT 24
Peak memory 201896 kb
Host smart-119f9967-8885-4698-9071-a507f2336f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103271203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.4103271203
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.3769335798
Short name T228
Test name
Test status
Simulation time 487742944274 ps
CPU time 1169.84 seconds
Started Apr 02 02:01:10 PM PDT 24
Finished Apr 02 02:20:41 PM PDT 24
Peak memory 201976 kb
Host smart-aff21c6f-f82b-4939-8afa-985e47d748cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769335798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.3769335798
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2250691136
Short name T388
Test name
Test status
Simulation time 323117277627 ps
CPU time 193.78 seconds
Started Apr 02 02:01:09 PM PDT 24
Finished Apr 02 02:04:23 PM PDT 24
Peak memory 201824 kb
Host smart-173bd04c-d82a-4114-b28e-9ee94ac36fbc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250691136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.2250691136
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.881512042
Short name T625
Test name
Test status
Simulation time 318758880329 ps
CPU time 206.38 seconds
Started Apr 02 02:01:04 PM PDT 24
Finished Apr 02 02:04:31 PM PDT 24
Peak memory 201788 kb
Host smart-dc768185-1fcd-4ac1-9db0-c456897be440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881512042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.881512042
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.3371618788
Short name T195
Test name
Test status
Simulation time 163599794935 ps
CPU time 89.43 seconds
Started Apr 02 02:01:10 PM PDT 24
Finished Apr 02 02:02:40 PM PDT 24
Peak memory 201844 kb
Host smart-c72c1210-4c24-4cbb-ae6c-6fe66faec427
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371618788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.3371618788
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.1776599551
Short name T240
Test name
Test status
Simulation time 365960361589 ps
CPU time 163.24 seconds
Started Apr 02 02:01:09 PM PDT 24
Finished Apr 02 02:03:53 PM PDT 24
Peak memory 201900 kb
Host smart-3d2a4465-b0b7-44e0-8220-567c16b56987
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776599551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.1776599551
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3610561835
Short name T420
Test name
Test status
Simulation time 392977709961 ps
CPU time 172.03 seconds
Started Apr 02 02:01:09 PM PDT 24
Finished Apr 02 02:04:02 PM PDT 24
Peak memory 201792 kb
Host smart-ed4bface-9fcf-43c2-87ab-010358d6b615
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610561835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3610561835
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.1594325107
Short name T209
Test name
Test status
Simulation time 97401612116 ps
CPU time 463.42 seconds
Started Apr 02 02:01:39 PM PDT 24
Finished Apr 02 02:09:22 PM PDT 24
Peak memory 202136 kb
Host smart-613918e8-c3d5-4ee1-be8e-a4931840eb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594325107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.1594325107
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1586649833
Short name T695
Test name
Test status
Simulation time 31481501371 ps
CPU time 11.4 seconds
Started Apr 02 02:01:16 PM PDT 24
Finished Apr 02 02:01:28 PM PDT 24
Peak memory 201644 kb
Host smart-c7a6c071-6baf-4761-b40c-1b2236f08771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586649833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1586649833
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.3200414331
Short name T385
Test name
Test status
Simulation time 4156309465 ps
CPU time 3.01 seconds
Started Apr 02 02:01:13 PM PDT 24
Finished Apr 02 02:01:17 PM PDT 24
Peak memory 201712 kb
Host smart-379c379c-a4a9-4ae6-a0f0-80152ecb45bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200414331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.3200414331
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3153662348
Short name T552
Test name
Test status
Simulation time 5936367365 ps
CPU time 13.99 seconds
Started Apr 02 02:01:04 PM PDT 24
Finished Apr 02 02:01:18 PM PDT 24
Peak memory 201596 kb
Host smart-f513f545-fd59-47ab-9069-505ae8dd1847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153662348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3153662348
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.4114577094
Short name T149
Test name
Test status
Simulation time 507846514271 ps
CPU time 666.96 seconds
Started Apr 02 02:01:16 PM PDT 24
Finished Apr 02 02:12:23 PM PDT 24
Peak memory 202260 kb
Host smart-42b754c4-12cb-4fa0-8ee5-0bd9de725883
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114577094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.4114577094
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.4286390606
Short name T652
Test name
Test status
Simulation time 32531010310 ps
CPU time 83.77 seconds
Started Apr 02 02:01:17 PM PDT 24
Finished Apr 02 02:02:41 PM PDT 24
Peak memory 212844 kb
Host smart-7d09959b-4a4c-45a8-a1ce-686d6b7117c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286390606 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.4286390606
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.3155720197
Short name T483
Test name
Test status
Simulation time 350318964 ps
CPU time 1.45 seconds
Started Apr 02 02:01:33 PM PDT 24
Finished Apr 02 02:01:35 PM PDT 24
Peak memory 201616 kb
Host smart-46abac27-3a56-42c5-9d89-d9b3ac723ded
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155720197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.3155720197
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2297471515
Short name T250
Test name
Test status
Simulation time 506481144333 ps
CPU time 587.6 seconds
Started Apr 02 02:01:26 PM PDT 24
Finished Apr 02 02:11:14 PM PDT 24
Peak memory 201976 kb
Host smart-7a3b1144-899d-4bd3-8d0c-9a1835fb34e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297471515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2297471515
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3828825078
Short name T155
Test name
Test status
Simulation time 172362485834 ps
CPU time 409.43 seconds
Started Apr 02 02:01:27 PM PDT 24
Finished Apr 02 02:08:17 PM PDT 24
Peak memory 201952 kb
Host smart-9db42c8a-a7cc-4c0c-be33-8bd061923994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828825078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3828825078
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.943109116
Short name T236
Test name
Test status
Simulation time 169049209385 ps
CPU time 47.12 seconds
Started Apr 02 02:01:20 PM PDT 24
Finished Apr 02 02:02:08 PM PDT 24
Peak memory 201960 kb
Host smart-f4423f9a-d53d-4997-a1d0-4772e37142f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943109116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.943109116
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.956648276
Short name T589
Test name
Test status
Simulation time 326466002114 ps
CPU time 181.13 seconds
Started Apr 02 02:01:22 PM PDT 24
Finished Apr 02 02:04:23 PM PDT 24
Peak memory 201892 kb
Host smart-38b7f738-f503-4c1c-a857-3ad3dd3863de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=956648276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.956648276
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.3657955507
Short name T279
Test name
Test status
Simulation time 334568334288 ps
CPU time 680.18 seconds
Started Apr 02 02:01:17 PM PDT 24
Finished Apr 02 02:12:37 PM PDT 24
Peak memory 201944 kb
Host smart-8e6ee7e8-6a9b-49e5-b519-f8118bbe79fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657955507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.3657955507
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.389380147
Short name T463
Test name
Test status
Simulation time 487421554119 ps
CPU time 572.34 seconds
Started Apr 02 02:01:21 PM PDT 24
Finished Apr 02 02:10:54 PM PDT 24
Peak memory 201876 kb
Host smart-da897a99-0198-4f61-89f1-3d5d8e066845
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=389380147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fixe
d.389380147
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.2023177287
Short name T342
Test name
Test status
Simulation time 485184081088 ps
CPU time 112.27 seconds
Started Apr 02 02:01:21 PM PDT 24
Finished Apr 02 02:03:14 PM PDT 24
Peak memory 201988 kb
Host smart-e29da018-9022-4781-bf5d-617dbc74542d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023177287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.2023177287
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.511731644
Short name T703
Test name
Test status
Simulation time 208209724813 ps
CPU time 124.16 seconds
Started Apr 02 02:01:27 PM PDT 24
Finished Apr 02 02:03:31 PM PDT 24
Peak memory 201788 kb
Host smart-64730a5c-f7ab-4a73-8301-4df18159c708
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511731644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
adc_ctrl_filters_wakeup_fixed.511731644
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.4274195767
Short name T354
Test name
Test status
Simulation time 94311343715 ps
CPU time 505.18 seconds
Started Apr 02 02:01:30 PM PDT 24
Finished Apr 02 02:09:55 PM PDT 24
Peak memory 202100 kb
Host smart-43c37dc6-ba6b-4120-83fb-9e5fe2862fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274195767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.4274195767
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.251249564
Short name T537
Test name
Test status
Simulation time 27082984559 ps
CPU time 16.99 seconds
Started Apr 02 02:01:26 PM PDT 24
Finished Apr 02 02:01:43 PM PDT 24
Peak memory 201624 kb
Host smart-9cb61df0-3f8a-41dc-879f-1b678f1100e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251249564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.251249564
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.198827633
Short name T412
Test name
Test status
Simulation time 3207257007 ps
CPU time 7.39 seconds
Started Apr 02 02:01:26 PM PDT 24
Finished Apr 02 02:01:34 PM PDT 24
Peak memory 201596 kb
Host smart-e53fd236-ab92-4f6d-87a6-c296732a0feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198827633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.198827633
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.2763494556
Short name T90
Test name
Test status
Simulation time 6207208994 ps
CPU time 2.28 seconds
Started Apr 02 02:01:16 PM PDT 24
Finished Apr 02 02:01:19 PM PDT 24
Peak memory 201692 kb
Host smart-7db5c1ec-7019-41d7-92bb-65fb0cfec18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763494556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.2763494556
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.3332445013
Short name T31
Test name
Test status
Simulation time 163701883724 ps
CPU time 59.89 seconds
Started Apr 02 02:01:29 PM PDT 24
Finished Apr 02 02:02:29 PM PDT 24
Peak memory 201864 kb
Host smart-1b10a2db-b90f-4943-bedc-1fc98041481e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332445013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.3332445013
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.1262308785
Short name T776
Test name
Test status
Simulation time 60223381063 ps
CPU time 103.69 seconds
Started Apr 02 02:01:29 PM PDT 24
Finished Apr 02 02:03:13 PM PDT 24
Peak memory 210120 kb
Host smart-4e54749e-0ee7-4521-9ebf-8101c2b83f01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262308785 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.1262308785
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.3243406812
Short name T467
Test name
Test status
Simulation time 449454907 ps
CPU time 0.87 seconds
Started Apr 02 02:01:51 PM PDT 24
Finished Apr 02 02:01:52 PM PDT 24
Peak memory 201484 kb
Host smart-5843b3f2-160f-4e91-8346-b066659d95ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243406812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.3243406812
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.2945880519
Short name T185
Test name
Test status
Simulation time 342680180215 ps
CPU time 101.64 seconds
Started Apr 02 02:01:42 PM PDT 24
Finished Apr 02 02:03:24 PM PDT 24
Peak memory 201820 kb
Host smart-f973aae1-eea1-4d8d-ad32-d9c6258e6201
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945880519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.2945880519
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.1554354371
Short name T302
Test name
Test status
Simulation time 178537657302 ps
CPU time 126.03 seconds
Started Apr 02 02:01:46 PM PDT 24
Finished Apr 02 02:03:52 PM PDT 24
Peak memory 201888 kb
Host smart-492d372e-bdc8-467d-abec-3fc4118f5ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554354371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.1554354371
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.1738073584
Short name T315
Test name
Test status
Simulation time 325447382448 ps
CPU time 797.39 seconds
Started Apr 02 02:01:41 PM PDT 24
Finished Apr 02 02:14:59 PM PDT 24
Peak memory 201856 kb
Host smart-7ad44d5a-fbdb-42c0-8249-b3b63ad4238d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738073584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1738073584
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.528883262
Short name T455
Test name
Test status
Simulation time 493521708362 ps
CPU time 269.72 seconds
Started Apr 02 02:01:43 PM PDT 24
Finished Apr 02 02:06:13 PM PDT 24
Peak memory 201944 kb
Host smart-b5899ec4-3114-49a5-bf11-5ad46b3cbb10
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=528883262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrup
t_fixed.528883262
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.2106760000
Short name T603
Test name
Test status
Simulation time 495242515100 ps
CPU time 1180.78 seconds
Started Apr 02 02:01:37 PM PDT 24
Finished Apr 02 02:21:18 PM PDT 24
Peak memory 201952 kb
Host smart-2cacb26e-5a6c-4adf-9676-ca5d9f5f69b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106760000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.2106760000
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.3471259732
Short name T638
Test name
Test status
Simulation time 160536847525 ps
CPU time 98.02 seconds
Started Apr 02 02:01:42 PM PDT 24
Finished Apr 02 02:03:20 PM PDT 24
Peak memory 201920 kb
Host smart-4c3a3db2-2092-4d23-b22a-784cb82f50e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471259732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.3471259732
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.762231061
Short name T575
Test name
Test status
Simulation time 357579901410 ps
CPU time 215.6 seconds
Started Apr 02 02:01:43 PM PDT 24
Finished Apr 02 02:05:18 PM PDT 24
Peak memory 201860 kb
Host smart-4e259409-92ad-498f-a835-eecc304190da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762231061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_
wakeup.762231061
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.1944246144
Short name T409
Test name
Test status
Simulation time 405118708826 ps
CPU time 950.83 seconds
Started Apr 02 02:01:41 PM PDT 24
Finished Apr 02 02:17:33 PM PDT 24
Peak memory 201944 kb
Host smart-841d222e-7d9e-494c-b78b-0ced4632acdf
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944246144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.1944246144
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.137178641
Short name T104
Test name
Test status
Simulation time 76750243589 ps
CPU time 293.27 seconds
Started Apr 02 02:01:52 PM PDT 24
Finished Apr 02 02:06:46 PM PDT 24
Peak memory 202088 kb
Host smart-7da9025e-5344-4834-b45b-0e04e4421030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137178641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.137178641
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.2772433083
Short name T381
Test name
Test status
Simulation time 25846974999 ps
CPU time 14.24 seconds
Started Apr 02 02:01:52 PM PDT 24
Finished Apr 02 02:02:06 PM PDT 24
Peak memory 201656 kb
Host smart-3111b2dc-b406-4b3d-8cd3-9e3babc34768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772433083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.2772433083
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.2378411191
Short name T587
Test name
Test status
Simulation time 3797444804 ps
CPU time 2.9 seconds
Started Apr 02 02:01:47 PM PDT 24
Finished Apr 02 02:01:50 PM PDT 24
Peak memory 201704 kb
Host smart-8477adc4-681b-4f95-8e18-a3926a8b3e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378411191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.2378411191
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2482642861
Short name T641
Test name
Test status
Simulation time 5931319868 ps
CPU time 4.27 seconds
Started Apr 02 02:01:32 PM PDT 24
Finished Apr 02 02:01:37 PM PDT 24
Peak memory 201612 kb
Host smart-fecafbf9-4aba-4143-bfed-16fc07ad1ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482642861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2482642861
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1091234163
Short name T88
Test name
Test status
Simulation time 121600575832 ps
CPU time 315.22 seconds
Started Apr 02 02:01:52 PM PDT 24
Finished Apr 02 02:07:07 PM PDT 24
Peak memory 210468 kb
Host smart-0d5b32d5-87da-42bb-98cd-d6fe82789cfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091234163 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1091234163
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1147009386
Short name T384
Test name
Test status
Simulation time 310217136 ps
CPU time 0.93 seconds
Started Apr 02 02:02:14 PM PDT 24
Finished Apr 02 02:02:15 PM PDT 24
Peak memory 201588 kb
Host smart-2221562b-5cf8-4163-9bd5-56f620561839
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147009386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1147009386
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2773406343
Short name T237
Test name
Test status
Simulation time 163018358246 ps
CPU time 385 seconds
Started Apr 02 02:02:18 PM PDT 24
Finished Apr 02 02:08:43 PM PDT 24
Peak memory 201964 kb
Host smart-71fe067c-e1fc-4fbc-9e5e-82bf113df6cc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773406343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2773406343
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.1260111415
Short name T708
Test name
Test status
Simulation time 326722571747 ps
CPU time 191.83 seconds
Started Apr 02 02:02:01 PM PDT 24
Finished Apr 02 02:05:13 PM PDT 24
Peak memory 201896 kb
Host smart-aa5ee12e-d355-4ce6-83d2-8dffae2e15ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260111415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1260111415
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.412600201
Short name T418
Test name
Test status
Simulation time 168273815351 ps
CPU time 97.51 seconds
Started Apr 02 02:02:00 PM PDT 24
Finished Apr 02 02:03:38 PM PDT 24
Peak memory 201788 kb
Host smart-24a008de-9a75-4590-8b70-9ba4494f36ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=412600201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.412600201
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.124463889
Short name T325
Test name
Test status
Simulation time 493703927075 ps
CPU time 217.02 seconds
Started Apr 02 02:01:52 PM PDT 24
Finished Apr 02 02:05:30 PM PDT 24
Peak memory 201984 kb
Host smart-1e25f86f-4a08-4514-95b6-7c2b9b34c376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124463889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.124463889
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.128203933
Short name T472
Test name
Test status
Simulation time 160121055897 ps
CPU time 346.09 seconds
Started Apr 02 02:01:55 PM PDT 24
Finished Apr 02 02:07:41 PM PDT 24
Peak memory 201900 kb
Host smart-29358dca-5c20-4557-aca7-45b196abf65a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=128203933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixe
d.128203933
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.346797950
Short name T654
Test name
Test status
Simulation time 589320275968 ps
CPU time 123.82 seconds
Started Apr 02 02:02:00 PM PDT 24
Finished Apr 02 02:04:04 PM PDT 24
Peak memory 201912 kb
Host smart-5dd4e5f9-7435-4476-b4ea-3402770565b2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346797950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
adc_ctrl_filters_wakeup_fixed.346797950
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.2879339157
Short name T210
Test name
Test status
Simulation time 127471656052 ps
CPU time 622.69 seconds
Started Apr 02 02:02:03 PM PDT 24
Finished Apr 02 02:12:26 PM PDT 24
Peak memory 202212 kb
Host smart-c865693a-d48e-418a-ae26-0edf0f58fbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879339157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2879339157
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1592672683
Short name T429
Test name
Test status
Simulation time 39097033110 ps
CPU time 22.36 seconds
Started Apr 02 02:02:05 PM PDT 24
Finished Apr 02 02:02:27 PM PDT 24
Peak memory 201696 kb
Host smart-023ecc76-14eb-45f9-b467-0c4fd4c3f16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592672683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1592672683
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2669623629
Short name T518
Test name
Test status
Simulation time 3825217528 ps
CPU time 3.15 seconds
Started Apr 02 02:02:04 PM PDT 24
Finished Apr 02 02:02:07 PM PDT 24
Peak memory 201676 kb
Host smart-b12ad243-642c-43a7-87ef-8a0dd11ae378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669623629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2669623629
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.444483886
Short name T398
Test name
Test status
Simulation time 5953850990 ps
CPU time 12.34 seconds
Started Apr 02 02:01:51 PM PDT 24
Finished Apr 02 02:02:03 PM PDT 24
Peak memory 201680 kb
Host smart-40a03f36-a1e4-456a-ac39-627691247031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444483886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.444483886
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3141649899
Short name T30
Test name
Test status
Simulation time 135717599679 ps
CPU time 590.26 seconds
Started Apr 02 02:02:04 PM PDT 24
Finished Apr 02 02:11:55 PM PDT 24
Peak memory 202216 kb
Host smart-4e55a241-cd5a-4547-8fc2-c3df1b8ce788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141649899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3141649899
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2572329033
Short name T593
Test name
Test status
Simulation time 92518512702 ps
CPU time 117.56 seconds
Started Apr 02 02:02:06 PM PDT 24
Finished Apr 02 02:04:04 PM PDT 24
Peak memory 210196 kb
Host smart-7e8cd4e3-061d-4c8d-9344-86e31a6ea2fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572329033 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.2572329033
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3704917602
Short name T608
Test name
Test status
Simulation time 577731540 ps
CPU time 0.68 seconds
Started Apr 02 02:02:26 PM PDT 24
Finished Apr 02 02:02:28 PM PDT 24
Peak memory 201572 kb
Host smart-e7835feb-5e95-45ff-90be-335304b5ccb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704917602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3704917602
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3421158859
Short name T276
Test name
Test status
Simulation time 160525299059 ps
CPU time 354.4 seconds
Started Apr 02 02:02:18 PM PDT 24
Finished Apr 02 02:08:13 PM PDT 24
Peak memory 201804 kb
Host smart-9b7ad20d-2f1c-4ac4-9c73-03083e377cb4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421158859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3421158859
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.1805278489
Short name T101
Test name
Test status
Simulation time 523627739111 ps
CPU time 656.99 seconds
Started Apr 02 02:02:18 PM PDT 24
Finished Apr 02 02:13:15 PM PDT 24
Peak memory 201856 kb
Host smart-8b328cf6-9f8b-43d6-820d-67b51df65fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805278489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.1805278489
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2517198791
Short name T705
Test name
Test status
Simulation time 488756289473 ps
CPU time 192.26 seconds
Started Apr 02 02:02:11 PM PDT 24
Finished Apr 02 02:05:23 PM PDT 24
Peak memory 201896 kb
Host smart-ddcc2b0f-f8f1-4151-bf87-97cb2ab0137b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517198791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2517198791
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.918916331
Short name T585
Test name
Test status
Simulation time 159804967737 ps
CPU time 356.84 seconds
Started Apr 02 02:02:13 PM PDT 24
Finished Apr 02 02:08:11 PM PDT 24
Peak memory 201888 kb
Host smart-587bea6b-9f0e-4aa9-8790-04111bd96f41
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=918916331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrup
t_fixed.918916331
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.3430375486
Short name T7
Test name
Test status
Simulation time 327485356852 ps
CPU time 43.75 seconds
Started Apr 02 02:02:08 PM PDT 24
Finished Apr 02 02:02:52 PM PDT 24
Peak memory 201784 kb
Host smart-62ada508-7265-4580-bf01-f9d68f4012c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430375486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3430375486
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.1139525019
Short name T609
Test name
Test status
Simulation time 160491706850 ps
CPU time 244.28 seconds
Started Apr 02 02:02:11 PM PDT 24
Finished Apr 02 02:06:15 PM PDT 24
Peak memory 201956 kb
Host smart-db0ef279-3265-4fe8-bef3-7af56ee94e5f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139525019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.1139525019
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.140426126
Short name T655
Test name
Test status
Simulation time 509725415356 ps
CPU time 369.42 seconds
Started Apr 02 02:02:14 PM PDT 24
Finished Apr 02 02:08:24 PM PDT 24
Peak memory 201968 kb
Host smart-0eae73b3-c2ee-4be6-a27a-c35f0b2fd25a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140426126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_
wakeup.140426126
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.604261521
Short name T672
Test name
Test status
Simulation time 411967032491 ps
CPU time 439.74 seconds
Started Apr 02 02:02:18 PM PDT 24
Finished Apr 02 02:09:38 PM PDT 24
Peak memory 201860 kb
Host smart-5bf99167-46c9-40d8-ba86-e8801e1c0084
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604261521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.604261521
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1866755880
Short name T390
Test name
Test status
Simulation time 58941582238 ps
CPU time 345.97 seconds
Started Apr 02 02:02:21 PM PDT 24
Finished Apr 02 02:08:07 PM PDT 24
Peak memory 202196 kb
Host smart-a8ad47b9-d72c-43e5-96e6-0df73f9aaf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866755880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1866755880
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1821755188
Short name T614
Test name
Test status
Simulation time 27105769266 ps
CPU time 14.59 seconds
Started Apr 02 02:02:22 PM PDT 24
Finished Apr 02 02:02:37 PM PDT 24
Peak memory 201640 kb
Host smart-a6f8d252-038a-4eb2-9b0e-7e229d6f6e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821755188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1821755188
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2050063459
Short name T699
Test name
Test status
Simulation time 5095186909 ps
CPU time 13.11 seconds
Started Apr 02 02:02:25 PM PDT 24
Finished Apr 02 02:02:38 PM PDT 24
Peak memory 201576 kb
Host smart-f3fe92c2-855a-4ec2-a51e-531e6e700ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050063459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2050063459
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.4264948027
Short name T547
Test name
Test status
Simulation time 5961202645 ps
CPU time 3.9 seconds
Started Apr 02 02:02:10 PM PDT 24
Finished Apr 02 02:02:14 PM PDT 24
Peak memory 201676 kb
Host smart-e03194a5-250f-4121-bcbc-595ac9f20c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264948027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.4264948027
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.822731864
Short name T600
Test name
Test status
Simulation time 165855122006 ps
CPU time 403.3 seconds
Started Apr 02 02:02:25 PM PDT 24
Finished Apr 02 02:09:09 PM PDT 24
Peak memory 201836 kb
Host smart-0fb26585-4f26-4e36-9c70-6b6bd1258b2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822731864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all.
822731864
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2235944504
Short name T333
Test name
Test status
Simulation time 58666249555 ps
CPU time 123.21 seconds
Started Apr 02 02:02:22 PM PDT 24
Finished Apr 02 02:04:25 PM PDT 24
Peak memory 210544 kb
Host smart-d2bb06f7-3d8d-4021-ba11-daabf1a9b2b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235944504 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2235944504
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.520143624
Short name T457
Test name
Test status
Simulation time 479856357 ps
CPU time 1.72 seconds
Started Apr 02 01:51:38 PM PDT 24
Finished Apr 02 01:51:40 PM PDT 24
Peak memory 201592 kb
Host smart-9a90145a-ff63-47f3-b460-1ee3a4335b5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520143624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.520143624
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3023067113
Short name T84
Test name
Test status
Simulation time 378400687239 ps
CPU time 77.65 seconds
Started Apr 02 01:51:38 PM PDT 24
Finished Apr 02 01:52:55 PM PDT 24
Peak memory 201956 kb
Host smart-ef5de6ac-acc7-4fe6-a12d-6b5bae9b98ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023067113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3023067113
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3995035284
Short name T307
Test name
Test status
Simulation time 501457717110 ps
CPU time 262.67 seconds
Started Apr 02 01:51:35 PM PDT 24
Finished Apr 02 01:55:57 PM PDT 24
Peak memory 201968 kb
Host smart-59bd731e-6a52-404c-8211-9b00b89affbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995035284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3995035284
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3924921273
Short name T78
Test name
Test status
Simulation time 484949961314 ps
CPU time 280.45 seconds
Started Apr 02 01:51:33 PM PDT 24
Finished Apr 02 01:56:14 PM PDT 24
Peak memory 201932 kb
Host smart-5f90f5f8-17bd-443b-b793-b7e7dc30cf6d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924921273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.3924921273
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.3457380685
Short name T345
Test name
Test status
Simulation time 159640687129 ps
CPU time 239.19 seconds
Started Apr 02 01:51:35 PM PDT 24
Finished Apr 02 01:55:34 PM PDT 24
Peak memory 201884 kb
Host smart-fea2f065-78f2-48c7-aa0a-8c7833b50044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457380685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.3457380685
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3011660124
Short name T548
Test name
Test status
Simulation time 167256333107 ps
CPU time 108.27 seconds
Started Apr 02 01:51:37 PM PDT 24
Finished Apr 02 01:53:25 PM PDT 24
Peak memory 201832 kb
Host smart-f0ca8614-b4a7-4cae-b66e-fd53c5b6c738
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011660124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3011660124
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.4069872456
Short name T158
Test name
Test status
Simulation time 434008216210 ps
CPU time 250.99 seconds
Started Apr 02 01:51:32 PM PDT 24
Finished Apr 02 01:55:44 PM PDT 24
Peak memory 201976 kb
Host smart-a79b7d8d-5cdb-4c86-8270-92c52392cc5c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069872456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.4069872456
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.559255888
Short name T12
Test name
Test status
Simulation time 202424799335 ps
CPU time 434.13 seconds
Started Apr 02 01:51:37 PM PDT 24
Finished Apr 02 01:58:51 PM PDT 24
Peak memory 201908 kb
Host smart-36dcd066-1339-407b-82d8-52059a475846
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559255888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.a
dc_ctrl_filters_wakeup_fixed.559255888
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.4127261700
Short name T792
Test name
Test status
Simulation time 101974469023 ps
CPU time 536.66 seconds
Started Apr 02 01:51:35 PM PDT 24
Finished Apr 02 02:00:32 PM PDT 24
Peak memory 202208 kb
Host smart-55e8d0a0-3088-4c76-bea8-414c6dd9bf1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127261700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.4127261700
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2843019648
Short name T425
Test name
Test status
Simulation time 34415228756 ps
CPU time 16.91 seconds
Started Apr 02 01:51:41 PM PDT 24
Finished Apr 02 01:51:58 PM PDT 24
Peak memory 201692 kb
Host smart-40e62e7f-a29d-4222-bcc6-beacd89c49fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843019648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2843019648
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2548209752
Short name T440
Test name
Test status
Simulation time 3880716814 ps
CPU time 5.66 seconds
Started Apr 02 01:51:42 PM PDT 24
Finished Apr 02 01:51:48 PM PDT 24
Peak memory 201688 kb
Host smart-cf02efa0-6c76-46f6-9779-0621c9878110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548209752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2548209752
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.693678325
Short name T700
Test name
Test status
Simulation time 5913084553 ps
CPU time 4.93 seconds
Started Apr 02 01:51:33 PM PDT 24
Finished Apr 02 01:51:38 PM PDT 24
Peak memory 201676 kb
Host smart-43615633-d645-4672-a3d0-a5997157eee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693678325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.693678325
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2672358833
Short name T311
Test name
Test status
Simulation time 662012331506 ps
CPU time 1378.4 seconds
Started Apr 02 01:51:37 PM PDT 24
Finished Apr 02 02:14:36 PM PDT 24
Peak memory 201900 kb
Host smart-f776bf28-e200-4bc5-b690-bcc2113c4eaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672358833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2672358833
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3062229889
Short name T644
Test name
Test status
Simulation time 34863553150 ps
CPU time 58.21 seconds
Started Apr 02 01:51:38 PM PDT 24
Finished Apr 02 01:52:37 PM PDT 24
Peak memory 210196 kb
Host smart-41a90f21-7e6d-4d1b-b82b-cacdb31030c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062229889 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.3062229889
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.1783603361
Short name T355
Test name
Test status
Simulation time 409739999 ps
CPU time 1.49 seconds
Started Apr 02 01:51:41 PM PDT 24
Finished Apr 02 01:51:43 PM PDT 24
Peak memory 201600 kb
Host smart-9c3a76db-4951-4b52-b11b-a63f056ec00b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783603361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1783603361
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2363862993
Short name T143
Test name
Test status
Simulation time 496796185729 ps
CPU time 387.99 seconds
Started Apr 02 01:51:41 PM PDT 24
Finished Apr 02 01:58:09 PM PDT 24
Peak memory 201900 kb
Host smart-916ea542-f4c6-44ad-af0c-b6876f8507e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363862993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2363862993
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1102941557
Short name T234
Test name
Test status
Simulation time 326093530378 ps
CPU time 595.24 seconds
Started Apr 02 01:51:40 PM PDT 24
Finished Apr 02 02:01:36 PM PDT 24
Peak memory 201968 kb
Host smart-7cec634e-2ddf-4968-9603-481a37f63d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102941557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1102941557
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3492082811
Short name T698
Test name
Test status
Simulation time 326869737325 ps
CPU time 731.58 seconds
Started Apr 02 01:51:40 PM PDT 24
Finished Apr 02 02:03:52 PM PDT 24
Peak memory 201912 kb
Host smart-2483948b-b61a-4dba-8021-decb28c58d38
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492082811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3492082811
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.3648394804
Short name T223
Test name
Test status
Simulation time 324699878414 ps
CPU time 176.05 seconds
Started Apr 02 01:51:41 PM PDT 24
Finished Apr 02 01:54:37 PM PDT 24
Peak memory 201804 kb
Host smart-dedf4487-1b01-4bd9-8c38-2928fb01f062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648394804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.3648394804
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.853742742
Short name T428
Test name
Test status
Simulation time 328509985775 ps
CPU time 712.76 seconds
Started Apr 02 01:51:43 PM PDT 24
Finished Apr 02 02:03:36 PM PDT 24
Peak memory 201840 kb
Host smart-50cb2910-0ff5-4fda-be4c-2be4e48b95ba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=853742742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed
.853742742
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.34897379
Short name T224
Test name
Test status
Simulation time 172960983792 ps
CPU time 180.52 seconds
Started Apr 02 01:51:40 PM PDT 24
Finished Apr 02 01:54:41 PM PDT 24
Peak memory 201888 kb
Host smart-e2b31344-3548-4f0a-bd5c-b418f4b443af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34897379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_wa
keup.34897379
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.426164901
Short name T410
Test name
Test status
Simulation time 414125097011 ps
CPU time 423.29 seconds
Started Apr 02 01:51:41 PM PDT 24
Finished Apr 02 01:58:45 PM PDT 24
Peak memory 201876 kb
Host smart-3a7edc10-89a1-4698-a2ed-36b389c04d45
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426164901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.a
dc_ctrl_filters_wakeup_fixed.426164901
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.1600193924
Short name T351
Test name
Test status
Simulation time 92560900144 ps
CPU time 487.58 seconds
Started Apr 02 01:51:42 PM PDT 24
Finished Apr 02 01:59:50 PM PDT 24
Peak memory 202132 kb
Host smart-da852ffc-bc87-4d0d-8ad7-422c29e2a07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600193924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.1600193924
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1355382999
Short name T362
Test name
Test status
Simulation time 41351064539 ps
CPU time 12.68 seconds
Started Apr 02 01:51:42 PM PDT 24
Finished Apr 02 01:51:55 PM PDT 24
Peak memory 201660 kb
Host smart-e9c24430-d95d-4aea-b3dc-d1f5524f14eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355382999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1355382999
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.3552547662
Short name T635
Test name
Test status
Simulation time 3995156237 ps
CPU time 3.14 seconds
Started Apr 02 01:51:41 PM PDT 24
Finished Apr 02 01:51:44 PM PDT 24
Peak memory 201608 kb
Host smart-a0b1da0f-abce-404b-83b3-1d9f4286576c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552547662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.3552547662
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2162225103
Short name T451
Test name
Test status
Simulation time 5786845913 ps
CPU time 4.05 seconds
Started Apr 02 01:51:37 PM PDT 24
Finished Apr 02 01:51:41 PM PDT 24
Peak memory 201680 kb
Host smart-06d6a902-8c01-4b23-86e4-1ca0bfbe46b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162225103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2162225103
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.1063362288
Short name T759
Test name
Test status
Simulation time 168235247396 ps
CPU time 393.96 seconds
Started Apr 02 01:51:43 PM PDT 24
Finished Apr 02 01:58:17 PM PDT 24
Peak memory 201856 kb
Host smart-8c312282-dd50-46cb-bbce-27ba1a935aba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063362288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
1063362288
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2271632883
Short name T531
Test name
Test status
Simulation time 99900592384 ps
CPU time 268.28 seconds
Started Apr 02 01:51:41 PM PDT 24
Finished Apr 02 01:56:10 PM PDT 24
Peak memory 210584 kb
Host smart-c0b47b29-c98e-43a5-80c0-6f2325b6fb7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271632883 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.2271632883
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.3676873170
Short name T514
Test name
Test status
Simulation time 299968693 ps
CPU time 1.3 seconds
Started Apr 02 01:51:46 PM PDT 24
Finished Apr 02 01:51:47 PM PDT 24
Peak memory 201600 kb
Host smart-10e37617-6401-4569-924a-2c40dfecf3eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676873170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3676873170
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.532823666
Short name T144
Test name
Test status
Simulation time 171093294021 ps
CPU time 98.77 seconds
Started Apr 02 01:51:44 PM PDT 24
Finished Apr 02 01:53:23 PM PDT 24
Peak memory 201960 kb
Host smart-f89c37d6-a62d-42db-9416-e1b25b5371a0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532823666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin
g.532823666
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1944382224
Short name T233
Test name
Test status
Simulation time 164271226896 ps
CPU time 355.8 seconds
Started Apr 02 01:51:47 PM PDT 24
Finished Apr 02 01:57:43 PM PDT 24
Peak memory 201820 kb
Host smart-f16ae6e4-5962-4493-a074-e89592209429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944382224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1944382224
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2480734471
Short name T582
Test name
Test status
Simulation time 498352534568 ps
CPU time 562.41 seconds
Started Apr 02 01:51:45 PM PDT 24
Finished Apr 02 02:01:07 PM PDT 24
Peak memory 201856 kb
Host smart-5da5e735-dc18-4cb5-86ac-93deb84d6d83
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480734471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2480734471
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3219317687
Short name T487
Test name
Test status
Simulation time 326447261038 ps
CPU time 205.06 seconds
Started Apr 02 01:51:41 PM PDT 24
Finished Apr 02 01:55:07 PM PDT 24
Peak memory 201888 kb
Host smart-452e2c71-37db-4bae-a8bb-662a7bfb2542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219317687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3219317687
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.3129975942
Short name T406
Test name
Test status
Simulation time 329889642092 ps
CPU time 708.06 seconds
Started Apr 02 01:51:43 PM PDT 24
Finished Apr 02 02:03:32 PM PDT 24
Peak memory 201840 kb
Host smart-d53e2505-16b0-4ce3-b017-9072c16a8346
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129975942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.3129975942
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2527876758
Short name T172
Test name
Test status
Simulation time 552755741103 ps
CPU time 117.83 seconds
Started Apr 02 01:51:42 PM PDT 24
Finished Apr 02 01:53:40 PM PDT 24
Peak memory 201848 kb
Host smart-b584a5ed-2f2a-4e7f-855f-872ae52c2606
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527876758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2527876758
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.41701678
Short name T444
Test name
Test status
Simulation time 194718093008 ps
CPU time 451.45 seconds
Started Apr 02 01:51:44 PM PDT 24
Finished Apr 02 01:59:15 PM PDT 24
Peak memory 201876 kb
Host smart-2a03ea1f-cb9d-4e1d-9e61-db5e39cb56bc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41701678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.ad
c_ctrl_filters_wakeup_fixed.41701678
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.892059806
Short name T39
Test name
Test status
Simulation time 133660679700 ps
CPU time 664.18 seconds
Started Apr 02 01:51:45 PM PDT 24
Finished Apr 02 02:02:50 PM PDT 24
Peak memory 202224 kb
Host smart-fee61e3e-537c-4851-87b2-d0ef0d8a9d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892059806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.892059806
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2012820034
Short name T610
Test name
Test status
Simulation time 45383694384 ps
CPU time 12.17 seconds
Started Apr 02 01:51:44 PM PDT 24
Finished Apr 02 01:51:57 PM PDT 24
Peak memory 201712 kb
Host smart-3ad90b73-e62e-41af-8dc1-2cf33e0c036b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012820034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2012820034
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.1422999859
Short name T465
Test name
Test status
Simulation time 3855435847 ps
CPU time 9.32 seconds
Started Apr 02 01:51:46 PM PDT 24
Finished Apr 02 01:51:56 PM PDT 24
Peak memory 201672 kb
Host smart-68cbd2b3-c778-4c7b-b402-f2d7377bafb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422999859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1422999859
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.4125300697
Short name T574
Test name
Test status
Simulation time 5907683482 ps
CPU time 4.56 seconds
Started Apr 02 01:51:40 PM PDT 24
Finished Apr 02 01:51:45 PM PDT 24
Peak memory 201704 kb
Host smart-87e06de6-2af5-4437-8d02-d0883c230e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125300697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.4125300697
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1217049162
Short name T287
Test name
Test status
Simulation time 166096934084 ps
CPU time 405.46 seconds
Started Apr 02 01:51:44 PM PDT 24
Finished Apr 02 01:58:29 PM PDT 24
Peak memory 201796 kb
Host smart-edf3e257-4750-468a-83ea-809a9639574c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217049162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1217049162
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2410638949
Short name T92
Test name
Test status
Simulation time 32344699454 ps
CPU time 118.25 seconds
Started Apr 02 01:51:44 PM PDT 24
Finished Apr 02 01:53:42 PM PDT 24
Peak memory 210576 kb
Host smart-4b2ea06d-634c-49b5-85cb-1480ecdf6d3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410638949 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2410638949
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.871608431
Short name T447
Test name
Test status
Simulation time 373357887 ps
CPU time 1.04 seconds
Started Apr 02 01:51:57 PM PDT 24
Finished Apr 02 01:51:58 PM PDT 24
Peak memory 201512 kb
Host smart-64f36b56-7d52-4c87-879c-057ba814ba1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871608431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.871608431
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.3795571147
Short name T656
Test name
Test status
Simulation time 160992985720 ps
CPU time 153.78 seconds
Started Apr 02 01:51:49 PM PDT 24
Finished Apr 02 01:54:23 PM PDT 24
Peak memory 201904 kb
Host smart-3f853cf1-3487-4fd3-9fae-cdf9f4baedfb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795571147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.3795571147
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.2905385624
Short name T653
Test name
Test status
Simulation time 341968262122 ps
CPU time 792.37 seconds
Started Apr 02 01:51:58 PM PDT 24
Finished Apr 02 02:05:11 PM PDT 24
Peak memory 201952 kb
Host smart-554e04f7-bbc2-4b61-a51a-0a32567992f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905385624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2905385624
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2428908145
Short name T618
Test name
Test status
Simulation time 162633278806 ps
CPU time 205.05 seconds
Started Apr 02 01:51:47 PM PDT 24
Finished Apr 02 01:55:12 PM PDT 24
Peak memory 201848 kb
Host smart-a39ffaf2-b92f-43dd-9ef4-163dba93d31d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428908145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2428908145
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.3912656105
Short name T100
Test name
Test status
Simulation time 332351339210 ps
CPU time 391.3 seconds
Started Apr 02 01:51:45 PM PDT 24
Finished Apr 02 01:58:17 PM PDT 24
Peak memory 201976 kb
Host smart-52857fc0-3a88-46da-af7e-87ac72275dc4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912656105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.3912656105
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2765751993
Short name T760
Test name
Test status
Simulation time 560886115461 ps
CPU time 342.45 seconds
Started Apr 02 01:51:48 PM PDT 24
Finished Apr 02 01:57:30 PM PDT 24
Peak memory 201992 kb
Host smart-55f1e30a-4e48-4d97-848e-e1ec9bce80dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765751993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2765751993
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.694547398
Short name T529
Test name
Test status
Simulation time 585468795638 ps
CPU time 1315.42 seconds
Started Apr 02 01:51:49 PM PDT 24
Finished Apr 02 02:13:45 PM PDT 24
Peak memory 201860 kb
Host smart-185eea83-2edb-40f3-b8ae-b5e3d3078f2d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694547398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.a
dc_ctrl_filters_wakeup_fixed.694547398
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.522893435
Short name T449
Test name
Test status
Simulation time 121249234619 ps
CPU time 365.65 seconds
Started Apr 02 01:51:58 PM PDT 24
Finished Apr 02 01:58:03 PM PDT 24
Peak memory 202288 kb
Host smart-a8b646fd-7fca-46b3-ad55-4914a76a3a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522893435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.522893435
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.545096
Short name T356
Test name
Test status
Simulation time 22407306405 ps
CPU time 24.85 seconds
Started Apr 02 01:51:57 PM PDT 24
Finished Apr 02 01:52:22 PM PDT 24
Peak memory 201592 kb
Host smart-bee2e6c5-5450-4ce0-9b00-d99e124e52f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.545096
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.3104299326
Short name T86
Test name
Test status
Simulation time 3262110345 ps
CPU time 1.82 seconds
Started Apr 02 01:51:59 PM PDT 24
Finished Apr 02 01:52:01 PM PDT 24
Peak memory 201720 kb
Host smart-c1dfeabe-898a-45b6-a4da-e75dc42ec353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104299326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.3104299326
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.191421803
Short name T611
Test name
Test status
Simulation time 5677369231 ps
CPU time 4.08 seconds
Started Apr 02 01:51:43 PM PDT 24
Finished Apr 02 01:51:48 PM PDT 24
Peak memory 201604 kb
Host smart-958b73bf-3e9d-4103-a57d-fa55d2b6a4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191421803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.191421803
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.4276460604
Short name T748
Test name
Test status
Simulation time 390068355206 ps
CPU time 269.92 seconds
Started Apr 02 01:51:57 PM PDT 24
Finished Apr 02 01:56:27 PM PDT 24
Peak memory 201900 kb
Host smart-4283b635-4faa-4461-97f4-4eabf7c99514
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276460604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
4276460604
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.3875533306
Short name T34
Test name
Test status
Simulation time 128985241910 ps
CPU time 433.06 seconds
Started Apr 02 01:51:57 PM PDT 24
Finished Apr 02 01:59:10 PM PDT 24
Peak memory 210588 kb
Host smart-806b9537-0ef8-4d27-87de-84363a13f8a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875533306 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.3875533306
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.234135998
Short name T504
Test name
Test status
Simulation time 474130285 ps
CPU time 1.12 seconds
Started Apr 02 01:51:58 PM PDT 24
Finished Apr 02 01:51:59 PM PDT 24
Peak memory 201568 kb
Host smart-d650d115-44ee-46ee-9e11-e395b381b96e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234135998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.234135998
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2303407527
Short name T330
Test name
Test status
Simulation time 164427262195 ps
CPU time 107.06 seconds
Started Apr 02 01:51:57 PM PDT 24
Finished Apr 02 01:53:44 PM PDT 24
Peak memory 201984 kb
Host smart-787163bb-7339-42de-99d9-feafb979db02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303407527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2303407527
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.2069155313
Short name T758
Test name
Test status
Simulation time 164398483540 ps
CPU time 396 seconds
Started Apr 02 01:51:55 PM PDT 24
Finished Apr 02 01:58:32 PM PDT 24
Peak memory 201904 kb
Host smart-8caf72fa-019b-4861-829f-757e4daab0e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069155313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.2069155313
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.556753746
Short name T269
Test name
Test status
Simulation time 494657991368 ps
CPU time 1106.37 seconds
Started Apr 02 01:51:58 PM PDT 24
Finished Apr 02 02:10:25 PM PDT 24
Peak memory 201856 kb
Host smart-9e9e88a2-2506-4c1f-8f2f-3381209f8add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556753746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.556753746
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.2651621989
Short name T507
Test name
Test status
Simulation time 170102194085 ps
CPU time 188.44 seconds
Started Apr 02 01:51:55 PM PDT 24
Finished Apr 02 01:55:05 PM PDT 24
Peak memory 201864 kb
Host smart-cfccb060-f149-4079-bdb1-28454caf46c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651621989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.2651621989
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2143583829
Short name T740
Test name
Test status
Simulation time 608824147898 ps
CPU time 735.84 seconds
Started Apr 02 01:51:57 PM PDT 24
Finished Apr 02 02:04:13 PM PDT 24
Peak memory 201944 kb
Host smart-a902fcfa-9931-4c91-be8d-9d7c469347a9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143583829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2143583829
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.40539174
Short name T214
Test name
Test status
Simulation time 103250749818 ps
CPU time 286.67 seconds
Started Apr 02 01:51:57 PM PDT 24
Finished Apr 02 01:56:44 PM PDT 24
Peak memory 202216 kb
Host smart-478c07ff-7144-4957-84de-d7c863ee9e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40539174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.40539174
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.2311276124
Short name T389
Test name
Test status
Simulation time 42991891333 ps
CPU time 36.27 seconds
Started Apr 02 01:51:55 PM PDT 24
Finished Apr 02 01:52:32 PM PDT 24
Peak memory 201716 kb
Host smart-c77d641e-9391-4ccb-ab3c-718be42d3280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311276124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.2311276124
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.4273136244
Short name T658
Test name
Test status
Simulation time 4221735379 ps
CPU time 5.72 seconds
Started Apr 02 01:51:57 PM PDT 24
Finished Apr 02 01:52:03 PM PDT 24
Peak memory 201620 kb
Host smart-16ad7c06-c35d-4cdb-aa50-28ae2ecb5725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273136244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.4273136244
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.1983397125
Short name T400
Test name
Test status
Simulation time 5620394121 ps
CPU time 14.37 seconds
Started Apr 02 01:51:57 PM PDT 24
Finished Apr 02 01:52:12 PM PDT 24
Peak memory 201708 kb
Host smart-798a081d-7457-4048-9246-3feea4eef9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983397125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1983397125
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1583894352
Short name T707
Test name
Test status
Simulation time 179545304896 ps
CPU time 404.62 seconds
Started Apr 02 01:51:57 PM PDT 24
Finished Apr 02 01:58:42 PM PDT 24
Peak memory 201800 kb
Host smart-63625b50-cdb4-453f-adf4-8b648c49a8b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583894352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1583894352
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3172956945
Short name T612
Test name
Test status
Simulation time 33610443228 ps
CPU time 108.27 seconds
Started Apr 02 01:51:59 PM PDT 24
Finished Apr 02 01:53:47 PM PDT 24
Peak memory 210500 kb
Host smart-0156a827-e89d-4e3e-b562-f5466d359320
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172956945 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3172956945
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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