Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

---

Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6974	1			T2	20		T4	5		T7	46
testmodes[AdcCtrlTestmodeNormal]	5626	1			T1	2		T3	3		T4	9
testmodes[AdcCtrlTestmodeLowpower]	5908	1			T4	20		T6	1		T7	42
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3761	1			T2	19		T4	1		T7	15
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1710	1			T4	3		T7	14		T9	1
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1389	1			T4	1		T7	16		T37	19
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1725	1			T4	4		T7	16		T9	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2105	1			T1	1		T3	2		T4	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1446	1			T7	12		T37	15		T12	6
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1369	1			T7	15		T37	20		T12	13
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1469	1			T4	1		T7	14		T37	15
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2837	1			T4	19		T7	13		T37	22