Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26606

1

T1

2

T2

20

T3

27

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22897

1

T1

2

T2

20

T3

27

auto[ADC_CTRL_FILTER_COND_OUT]

3709

1

T4

3

T8

2

T11

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20694

1

T1

2

T2

20

T4

38

auto[1]

5912

1

T3

27

T5

21

T6

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

2

T2

20

T3

3

auto[1]

3833

1

T3

24

T4

4

T5

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	19	1			T193	11		T192	8		-	-
values[0]	10	1			T194	1		T195	9		-	-
values[1]	783	1			T28	2		T128	6		T122	12
values[2]	795	1			T11	6		T44	22		T122	1
values[3]	584	1			T4	3		T43	14		T36	3
values[4]	646	1			T1	1		T8	1		T45	13
values[5]	575	1			T13	9		T138	15		T139	4
values[6]	663	1			T120	21		T132	14		T81	16
values[7]	731	1			T29	35		T45	14		T121	7
values[8]	3065	1			T3	27		T5	21		T6	4
values[9]	1185	1			T1	1		T8	2		T11	1
minimum	17550	1			T2	20		T4	35		T7	124

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	914	1			T28	2		T128	6		T122	12
values[1]	841	1			T4	3		T11	6		T43	14
values[2]	505	1			T1	1		T8	1		T36	3
values[3]	757	1			T13	9		T45	13		T120	23
values[4]	498	1			T139	4		T125	3		T134	1
values[5]	695	1			T129	7		T132	14		T81	8
values[6]	3094	1			T3	27		T5	21		T6	4
values[7]	757	1			T11	1		T12	5		T28	21
values[8]	824	1			T1	1		T8	2		T30	1
values[9]	168	1			T39	12		T151	5		T87	9
minimum	17553	1			T2	20		T4	35		T7	124

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

4265

1

T6

3

T12

1

T13

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T123	11		T15	6		T196	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T28	1		T128	1		T122	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T43	9		T44	10		T78	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T4	1		T11	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T1	1		T8	1		T122	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T36	2		T139	1		T130	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T138	7		T140	13		T78	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T13	7		T45	11		T120	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T125	3		T142	3		T197	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T139	1		T134	1		T16	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T129	5		T81	1		T198	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T132	1		T18	2		T199	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1673	1			T3	3		T5	2		T6	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T29	19		T45	5		T120	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T12	4		T28	11		T29	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T11	1		T200	9		T142	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T1	1		T129	13		T50	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T8	2		T30	1		T44	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T39	11		T87	7		T20	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T151	2		T201	1		T185	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17444	1			T2	20		T4	33		T7	124
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T123	2		T15	3		T196	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T28	1		T128	5		T50	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T43	5		T44	12		T202	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T4	2		T11	5		T141	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T130	5		T19	4		T203	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T36	1		T139	9		T130	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T138	8		T140	12		T42	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	2		T45	2		T120	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T145	13		T204	4		T205	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T139	3		T16	2		T206	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T129	2		T81	7		T198	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T132	13		T18	5		T199	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	993	1			T3	24		T5	19		T10	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T29	16		T45	9		T120	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	1		T28	10		T29	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T200	7		T207	11		T137	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T129	12		T50	13		T191	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T44	3		T208	9		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T39	1		T87	2		T20	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T151	3		T201	13		T209	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T4	2		T33	1		T16	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T193	1		T192	4		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T194	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T195	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T15	6		T81	1		T210	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T28	1		T128	1		T122	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T44	10		T122	1		T123	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	1		T139	1		T211	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T43	9		T122	12		T130	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T4	1		T36	2		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	1		T8	1		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T45	11		T120	12		T138	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T138	7		T125	3		T140	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	7		T139	1		T125	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T81	1		T198	10		T212	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T120	11		T132	1		T81	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T121	7		T129	5		T140	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T29	19		T45	5		T50	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1695	1			T3	3		T5	2		T6	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T138	12		T200	9		T142	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T1	1		T29	3		T129	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	423	1			T8	2		T11	1		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17442	1			T2	20		T4	33		T7	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T193	10		T192	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T195	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T15	3		T81	1		T202	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T28	1		T128	5		T50	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T44	12		T123	2		T213	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T11	5		T139	13		T211	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T43	5		T130	5		T19	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T4	2		T36	1		T139	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T42	2		T135	6		T202	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T45	2		T120	11		T138	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T138	8		T140	12		T18	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T13	2		T139	3		T16	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T81	7		T198	8		T212	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T120	10		T132	13		T81	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T129	2		T140	11		T214	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T29	16		T45	9		T18	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1051	1			T3	24		T5	19		T10	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T138	13		T200	7		T196	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T29	14		T129	12		T50	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T44	3		T208	9		T40	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	2		T33	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T123	3		T15	7		T196	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T28	2		T128	6		T122	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T43	6		T44	13		T78	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T4	3		T11	6		T141	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T1	1		T8	1		T122	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T36	3		T139	10		T130	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T138	9		T140	13		T78	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T13	7		T45	3		T120	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T125	1		T142	1		T197	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T139	4		T134	1		T16	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T129	3		T81	8		T198	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T132	14		T18	7		T199	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T3	27		T5	21		T6	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T29	17		T45	10		T120	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T12	4		T28	11		T29	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T11	1		T200	8		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	1		T129	13		T50	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T8	2		T30	1		T44	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T39	6		T87	9		T20	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T151	4		T201	14		T185	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17553	1			T2	20		T4	35		T7	124
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T123	10		T15	2		T196	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T122	11		T50	15		T215	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T43	8		T44	9		T202	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T211	12		T135	16		T136	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T122	11		T130	2		T216	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T130	3		T208	14		T17	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T138	6		T140	12		T42	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	2		T45	10		T120	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T125	2		T142	2		T145	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T16	1		T206	7		T142	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T129	4		T198	9		T217	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T199	10		T213	7		T218	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T6	3		T27	28		T46	42
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T29	18		T45	4		T120	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	1		T28	10		T29	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T200	8		T142	8		T207	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T129	12		T191	22		T219	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T44	2		T208	14		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T39	6		T20	5		T220	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T151	1		T185	2		T209	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T193	11		T192	6		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T194	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T195	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T15	7		T81	2		T210	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T28	2		T128	6		T122	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T44	13		T122	1		T123	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T11	6		T139	14		T211	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T43	6		T122	1		T130	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T4	3		T36	3		T139	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T1	1		T8	1		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T45	3		T120	12		T138	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T138	9		T125	1		T140	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	7		T139	4		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T81	8		T198	9		T212	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T120	11		T132	14		T81	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T121	1		T129	3		T140	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T29	17		T45	10		T50	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1396	1			T3	27		T5	21		T6	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T138	14		T200	8		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T1	1		T29	15		T129	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	367	1			T8	2		T11	1		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17550	1			T2	20		T4	35		T7	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T192	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T195	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T15	2		T202	12		T196	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T122	11		T50	15		T215	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T44	9		T123	10		T213	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T211	12		T135	16		T213	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T43	8		T122	11		T130	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T130	3		T208	14		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T42	1		T135	5		T202	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T45	10		T120	11		T138	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T138	6		T125	2		T140	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T13	2		T125	1		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T198	9		T217	13		T221	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T120	10		T218	1		T144	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T121	6		T129	4		T140	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T29	18		T45	4		T50	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T6	3		T12	1		T27	28
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T138	11		T200	8		T142	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T29	2		T129	12		T191	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T44	2		T208	14		T40	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

auto[0]

4265

1

T6

3

T12

1

T13

2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26606

1

T1

2

T2

20

T3

27

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23262

1

T2

20

T3

27

T4

38

auto[ADC_CTRL_FILTER_COND_OUT]

3344

1

T1

2

T8

1

T12

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20207

1

T1

1

T2

20

T4

35

auto[1]

6399

1

T1

1

T3

27

T4

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

2

T2

20

T3

3

auto[1]

3833

1

T3

24

T4

4

T5

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	111	1			T29	17		T139	4		T144	22
values[1]	584	1			T28	21		T50	26		T138	22
values[2]	672	1			T8	1		T122	12		T123	13
values[3]	841	1			T8	1		T29	35		T43	14
values[4]	2755	1			T3	27		T5	21		T6	4
values[5]	822	1			T8	1		T36	3		T50	31
values[6]	835	1			T11	6		T12	5		T122	1
values[7]	550	1			T1	1		T128	6		T121	7
values[8]	688	1			T13	9		T28	2		T122	12
values[9]	1198	1			T1	1		T4	3		T11	1
minimum	17550	1			T2	20		T4	35		T7	124

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	824	1			T28	21		T29	17		T123	13
values[1]	649	1			T8	1		T45	13		T122	12
values[2]	826	1			T8	1		T29	35		T30	1
values[3]	2891	1			T3	27		T5	21		T6	4
values[4]	786	1			T8	1		T36	3		T122	1
values[5]	689	1			T1	1		T11	6		T12	5
values[6]	757	1			T13	9		T121	7		T133	1
values[7]	670	1			T28	2		T122	12		T129	7
values[8]	777	1			T1	1		T4	3		T11	1
values[9]	173	1			T44	6		T140	27		T162	23
minimum	17564	1			T2	20		T4	35		T7	124

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

4265

1

T6

3

T12

1

T13

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T123	11		T129	13		T50	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T28	11		T29	3		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T45	11		T138	12		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T8	1		T122	12		T50	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T8	1		T30	1		T45	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T29	19		T43	9		T120	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1599	1			T3	3		T5	2		T6	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T38	5		T141	1		T81	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T8	1		T36	2		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T141	1		T39	11		T136	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	1		T125	2		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T1	1		T12	4		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T13	7		T121	7		T215	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T133	1		T41	7		T137	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T134	1		T34	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T28	1		T122	12		T129	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T4	1		T11	1		T44	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T1	1		T15	6		T207	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T44	3		T18	7		T221	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T140	16		T162	13		T222	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17443	1			T2	20		T4	33		T7	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T165	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T123	2		T129	12		T50	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T28	10		T29	14		T162	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T45	2		T138	13		T132	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T139	9		T191	10		T81	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T45	9		T120	11		T130	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T29	16		T43	5		T120	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	952	1			T3	24		T5	19		T10	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T81	7		T219	7		T221	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T36	1		T50	15		T139	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T141	15		T39	1		T136	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T11	5		T132	10		T223	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T12	1		T128	5		T138	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T13	2		T215	1		T202	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T41	3		T137	7		T224	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T141	4		T208	9		T35	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T28	1		T129	2		T132	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T4	2		T44	12		T16	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T15	3		T207	11		T137	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T44	3		T18	5		T221	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T140	11		T162	10		T225	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T4	2		T33	1		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T165	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T139	1		T144	12		T226	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T29	3		T154	5		T227	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T50	1		T138	11		T142	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T28	11		T50	12		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T123	11		T129	13		T138	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T8	1		T122	12		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T8	1		T45	16		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T29	19		T43	9		T120	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1560	1			T3	3		T5	2		T6	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T81	1		T228	1		T229	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T8	1		T36	2		T50	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T38	5		T141	1		T39	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T11	1		T122	1		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T12	4		T138	7		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T121	7		T210	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T1	1		T128	1		T130	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	7		T134	1		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T28	1		T122	12		T129	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T4	1		T11	1		T44	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	393	1			T1	1		T132	1		T15	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17442	1			T2	20		T4	33		T7	124
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T139	3		T144	10		T230	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T29	14		T154	3		T227	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T50	13		T138	11		T231	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T28	10		T202	8		T19	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T123	2		T129	12		T138	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T139	9		T191	10		T81	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T45	11		T132	8		T130	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T29	16		T43	5		T120	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	964	1			T3	24		T5	19		T10	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T81	7		T219	7		T221	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T36	1		T50	15		T40	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T39	1		T136	11		T94	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	5		T139	13		T132	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	1		T138	8		T33	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T232	12		T201	13		T233	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T128	5		T130	5		T135	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	2		T208	9		T35	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T28	1		T129	2		T140	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T4	2		T44	15		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T132	13		T15	3		T140	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	2		T33	1		T16	1