Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26606

1

T1

2

T2

20

T3

27

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23044

1

T1

1

T2

20

T3

27

auto[ADC_CTRL_FILTER_COND_OUT]

3562

1

T1

1

T4

3

T8

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21284

1

T1

1

T2

20

T4

35

auto[1]

5322

1

T1

1

T3

27

T4

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

2

T2

20

T3

3

auto[1]

3833

1

T3

24

T4

4

T5

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	240	1			T130	8		T38	5		T81	8
values[0]	38	1			T261	11		T266	15		T288	12
values[1]	751	1			T11	1		T29	35		T122	12
values[2]	2762	1			T3	27		T5	21		T6	4
values[3]	655	1			T1	2		T11	6		T36	3
values[4]	580	1			T12	5		T13	9		T44	6
values[5]	854	1			T4	3		T28	2		T29	17
values[6]	704	1			T28	21		T45	14		T123	13
values[7]	651	1			T8	1		T30	1		T50	14
values[8]	665	1			T8	2		T43	14		T134	1
values[9]	1156	1			T45	13		T128	6		T139	24
minimum	17550	1			T2	20		T4	35		T7	124

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	615	1			T29	35		T50	12		T132	9
values[1]	2806	1			T3	27		T5	21		T6	4
values[2]	678	1			T1	2		T11	6		T12	5
values[3]	621	1			T4	3		T13	9		T28	2
values[4]	852	1			T44	22		T123	13		T139	4
values[5]	672	1			T28	21		T29	17		T45	14
values[6]	545	1			T8	2		T30	1		T138	22
values[7]	854	1			T8	1		T43	14		T45	13
values[8]	1001	1			T128	6		T139	24		T130	8
values[9]	126	1			T33	7		T38	5		T142	3
minimum	17836	1			T2	20		T4	35		T7	124

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

4265

1

T6

3

T12

1

T13

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T29	19		T132	1		T126	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T50	12		T130	4		T136	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1580	1			T3	3		T5	2		T6	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T122	1		T120	12		T191	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	1		T11	1		T44	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T1	1		T12	4		T120	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T28	1		T129	5		T228	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T4	1		T13	7		T129	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T44	10		T139	1		T200	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T123	11		T125	3		T191	23
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T29	3		T138	7		T140	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T28	11		T45	5		T50	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	1		T138	11		T132	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T8	1		T30	1		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T43	9		T45	11		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T8	1		T35	1		T18	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T128	1		T139	2		T130	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T134	1		T17	5		T135	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T33	1		T142	3		T305	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T38	5		T144	3		T233	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17578	1			T2	20		T4	33		T7	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T11	1		T81	1		T285	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T29	16		T132	8		T252	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T130	7		T136	11		T250	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	928	1			T3	24		T5	19		T10	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T120	11		T191	1		T207	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T11	5		T44	3		T36	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T12	1		T120	10		T223	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T28	1		T129	2		T212	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T4	2		T13	2		T129	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T44	12		T139	3		T200	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T123	2		T191	10		T15	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T29	14		T138	8		T140	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T28	10		T45	9		T50	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T138	11		T132	10		T141	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T163	9		T152	6		T253	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T43	5		T45	2		T208	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T35	1		T18	5		T221	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T128	5		T139	22		T130	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T17	1		T135	6		T35	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T33	6		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T144	2		T233	4		T306	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T4	2		T50	15		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T81	1		T204	10		T307	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T130	3		T81	1		T142	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T38	5		T232	21		T203	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T261	11		T266	8		T288	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T29	19		T122	12		T50	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	1		T130	4		T81	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1594	1			T3	3		T5	2		T6	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T122	1		T120	12		T50	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T1	1		T11	1		T36	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	1		T120	11		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T44	3		T129	5		T229	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	4		T13	7		T129	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T28	1		T29	3		T44	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T4	1		T191	23		T15	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T139	1		T142	9		T198	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T28	11		T45	5		T123	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T138	18		T132	1		T140	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T8	1		T30	1		T50	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T8	1		T43	9		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T8	1		T134	1		T18	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T45	11		T128	1		T139	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	384	1			T134	1		T17	5		T135	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17442	1			T2	20		T4	33		T7	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T130	5		T81	7		T162	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T232	15		T203	13		T308	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T266	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T29	16		T50	15		T132	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T130	7		T81	1		T136	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	952	1			T3	24		T5	19		T10	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T120	11		T191	1		T21	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T11	5		T36	1		T77	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T120	10		T207	11		T199	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T44	3		T129	2		T18	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	1		T13	2		T129	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T28	1		T29	14		T44	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T4	2		T191	10		T15	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T139	3		T198	8		T213	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T28	10		T45	9		T123	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T138	19		T132	10		T140	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T50	13		T163	9		T152	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T43	5		T141	15		T208	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T18	5		T221	17		T267	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T45	2		T128	5		T139	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T17	1		T135	6		T35	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	2		T33	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T29	17		T132	9		T126	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T50	1		T130	8		T136	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1256	1			T3	27		T5	21		T6	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T122	1		T120	12		T191	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	1		T11	6		T44	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	1		T12	4		T120	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T28	2		T129	3		T228	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T4	3		T13	7		T129	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T44	13		T139	4		T200	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T123	3		T125	1		T191	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T29	15		T138	9		T140	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T28	11		T45	10		T50	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T8	1		T138	12		T132	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T8	1		T30	1		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T43	6		T45	3		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T8	1		T35	2		T18	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T128	6		T139	24		T130	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T134	1		T17	5		T135	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T33	7		T142	1		T305	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T38	5		T144	3		T233	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17666	1			T2	20		T4	35		T7	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T11	1		T81	2		T285	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T29	18		T213	7		T19	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T50	11		T130	3		T136	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1252	1			T6	3		T27	28		T46	42
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T120	11		T207	12		T245	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T44	2		T40	1		T202	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	1		T120	10		T223	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T129	4		T19	7		T250	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	2		T129	12		T140	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T44	9		T200	8		T219	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T123	10		T125	2		T191	22
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T29	2		T138	6		T140	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T28	10		T45	4		T42	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T138	10		T39	6		T250	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T163	5		T152	6		T209	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T43	8		T45	10		T208	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T18	5		T221	20		T196	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T130	2		T208	14		T162	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T17	1		T135	5		T35	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T142	2		T305	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T144	2		T233	9		T248	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T122	11		T50	15		T135	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T261	10		T309	2		T288	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T130	6		T81	8		T142	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T38	5		T232	16		T203	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T261	1		T266	8		T288	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T29	17		T122	1		T50	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	1		T130	8		T81	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T3	27		T5	21		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T122	1		T120	12		T50	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T1	1		T11	6		T36	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	1		T120	11		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T44	4		T129	3		T229	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	4		T13	7		T129	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T28	2		T29	15		T44	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T4	3		T191	11		T15	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T139	4		T142	1		T198	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T28	11		T45	10		T123	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T138	21		T132	11		T140	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T8	1		T30	1		T50	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	1		T43	6		T141	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T8	1		T134	1		T18	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T45	3		T128	6		T139	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T134	1		T17	5		T135	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17550	1			T2	20		T4	35		T7	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T130	2		T142	2		T202	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T232	20		T203	14		T308	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T261	10		T266	7		T288	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T29	18		T122	11		T50	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T130	3		T136	11		T250	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T6	3		T27	28		T46	42
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T120	11		T50	11		T245	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T121	6		T125	1		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T120	10		T217	13		T207	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T44	2		T129	4		T19	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	1		T13	2		T129	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T29	2		T44	9		T200	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T191	22		T15	2		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T142	8		T198	9		T213	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T28	10		T45	4		T123	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T138	16		T140	15		T250	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T163	5		T152	6		T20	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T43	8		T208	14		T39	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T18	5		T221	20		T270	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T45	10		T208	14		T162	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T17	1		T135	5		T35	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

auto[0]

4265

1

T6

3

T12

1

T13

2