Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26606

1

T1

2

T2

20

T3

27

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23220

1

T2

20

T3

27

T4

38

auto[ADC_CTRL_FILTER_COND_OUT]

3386

1

T1

2

T8

1

T12

5

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20160

1

T1

1

T2

20

T4

35

auto[1]

6446

1

T1

1

T3

27

T4

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

2

T2

20

T3

3

auto[1]

3833

1

T3

24

T4

4

T5

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	259	1			T44	22		T15	9		T18	12
values[0]	45	1			T226	9		T313	1		T230	25
values[1]	650	1			T28	21		T29	17		T50	26
values[2]	633	1			T8	1		T122	12		T123	13
values[3]	882	1			T8	1		T29	35		T30	1
values[4]	2757	1			T3	27		T5	21		T6	4
values[5]	805	1			T8	1		T36	3		T122	1
values[6]	759	1			T1	1		T11	6		T12	5
values[7]	653	1			T128	6		T121	7		T132	11
values[8]	705	1			T13	9		T28	2		T122	12
values[9]	908	1			T1	1		T4	3		T11	1
minimum	17550	1			T2	20		T4	35		T7	124

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	650	1			T28	21		T29	17		T123	13
values[1]	676	1			T8	1		T45	13		T122	12
values[2]	802	1			T8	1		T29	35		T30	1
values[3]	2898	1			T3	27		T5	21		T6	4
values[4]	769	1			T8	1		T36	3		T122	1
values[5]	720	1			T1	1		T11	6		T12	5
values[6]	702	1			T13	9		T121	7		T133	1
values[7]	689	1			T4	3		T28	2		T122	12
values[8]	858	1			T1	1		T11	1		T44	28
values[9]	107	1			T140	27		T18	12		T221	26
minimum	17735	1			T2	20		T4	35		T7	124

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

4265

1

T6

3

T12

1

T13

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T123	11		T50	1		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T28	11		T29	3		T50	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T45	11		T129	13		T138	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T8	1		T122	12		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T8	1		T30	1		T45	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T29	19		T43	9		T120	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1600	1			T3	3		T5	2		T6	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T38	5		T141	1		T81	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T8	1		T36	2		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T141	1		T39	11		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T11	1		T125	2		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T1	1		T12	4		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T13	7		T121	7		T215	19
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T133	1		T80	1		T41	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T4	1		T134	1		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T28	1		T122	12		T129	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T11	1		T44	13		T16	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T1	1		T15	6		T162	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T18	7		T221	13		T152	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T140	16		T269	5		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17519	1			T2	20		T4	33		T7	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T153	13		T154	5		T248	18
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T123	2		T50	13		T139	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T28	10		T29	14		T162	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T45	2		T129	12		T138	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T139	9		T191	10		T81	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T45	9		T120	11		T130	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T29	16		T43	5		T120	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	941	1			T3	24		T5	19		T10	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T81	7		T219	7		T221	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T36	1		T50	15		T139	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T141	15		T39	1		T136	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T11	5		T132	10		T223	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T12	1		T128	5		T138	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	2		T215	1		T202	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T41	3		T135	6		T137	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T4	2		T141	4		T208	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T28	1		T129	2		T132	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T44	15		T16	2		T214	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T15	3		T162	10		T18	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T18	5		T221	13		T152	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T140	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T4	2		T138	11		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T154	3		T227	8		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T44	10		T18	7		T155	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T15	6		T207	13		T137	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T226	9		T313	1		T230	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T227	1		T175	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T50	1		T138	11		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T28	11		T29	3		T50	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T123	11		T129	13		T206	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T8	1		T122	12		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T8	1		T30	1		T45	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T29	19		T43	9		T120	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1581	1			T3	3		T5	2		T6	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T141	1		T81	1		T228	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T8	1		T36	2		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T38	5		T39	11		T196	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T11	1		T139	1		T125	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T1	1		T12	4		T138	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T121	7		T132	1		T210	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T128	1		T130	3		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T13	7		T134	1		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T28	1		T122	12		T129	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T4	1		T11	1		T44	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T1	1		T125	3		T132	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17442	1			T2	20		T4	33		T7	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T44	12		T18	5		T227	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T15	3		T207	11		T137	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T230	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T227	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T50	13		T138	11		T139	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T28	10		T29	14		T202	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T123	2		T129	12		T206	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T139	9		T191	10		T81	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T45	11		T138	13		T132	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T29	16		T43	5		T120	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	957	1			T3	24		T5	19		T10	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T81	7		T219	7		T221	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T36	1		T50	15		T42	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T39	1		T196	7		T94	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T11	5		T139	13		T223	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	1		T138	8		T33	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T132	10		T232	12		T201	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T128	5		T130	5		T135	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	2		T208	9		T35	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T28	1		T129	2		T140	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T4	2		T44	3		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T132	13		T140	11		T208	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	2		T33	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T123	3		T50	14		T139	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T28	11		T29	15		T50	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T45	3		T129	13		T138	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T8	1		T122	1		T139	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T8	1		T30	1		T45	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T29	17		T43	6		T120	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T3	27		T5	21		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T38	5		T141	1		T81	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T8	1		T36	3		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T141	16		T39	6		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T11	6		T125	1		T132	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T1	1		T12	4		T128	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T13	7		T121	1		T215	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T133	1		T80	1		T41	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T4	3		T134	1		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T28	2		T122	1		T129	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	1		T44	17		T16	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T1	1		T15	7		T162	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T18	7		T221	14		T152	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T140	12		T269	1		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17622	1			T2	20		T4	35		T7	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T153	1		T154	4		T248	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T123	10		T213	8		T96	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T28	10		T29	2		T50	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T45	10		T129	12		T138	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T122	11		T191	22		T17	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T45	4		T120	11		T130	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T29	18		T43	8		T120	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1274	1			T6	3		T27	28		T46	42
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T219	6		T221	20		T136	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T50	15		T40	1		T42	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T39	6		T136	11		T88	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T125	1		T223	2		T198	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T12	1		T138	6		T130	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	2		T121	6		T215	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T41	3		T135	5		T137	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T208	14		T35	11		T18	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T122	11		T129	4		T125	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T44	11		T16	1		T142	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T15	2		T162	12		T207	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T18	5		T221	12		T152	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T140	15		T269	4		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T138	10		T142	4		T242	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T153	12		T154	4		T248	17

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T44	13		T18	7		T155	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T15	7		T207	12		T137	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T226	1		T313	1		T230	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T227	9		T175	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T50	14		T138	12		T139	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T28	11		T29	15		T50	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T123	3		T129	13		T206	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T8	1		T122	1		T139	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T8	1		T30	1		T45	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T29	17		T43	6		T120	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1287	1			T3	27		T5	21		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T141	1		T81	8		T228	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T8	1		T36	3		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T38	5		T39	6		T196	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T11	6		T139	14		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T1	1		T12	4		T138	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T121	1		T132	11		T210	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T128	6		T130	6		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	7		T134	1		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T28	2		T122	1		T129	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T4	3		T11	1		T44	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T1	1		T125	1		T132	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17550	1			T2	20		T4	35		T7	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T44	9		T18	5		T227	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T15	2		T207	12		T137	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T226	8		T230	15		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T138	10		T142	4		T213	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T28	10		T29	2		T50	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T123	10		T129	12		T206	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T122	11		T191	22		T17	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T45	14		T138	11		T130	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T29	18		T43	8		T120	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1251	1			T6	3		T27	28		T46	42
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T219	6		T221	20		T136	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T50	15		T42	1		T135	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T39	6		T196	8		T94	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T125	1		T223	2		T40	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	1		T138	6		T211	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T121	6		T232	11		T240	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T130	2		T135	5		T137	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	2		T208	14		T35	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T122	11		T129	4		T140	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T44	2		T16	1		T142	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T125	2		T140	15		T208	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

auto[0]

4265

1

T6

3

T12

1

T13

2