Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26606

1

T1

2

T2

20

T3

27

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23034

1

T2

20

T3

27

T4

35

auto[ADC_CTRL_FILTER_COND_OUT]

3572

1

T1

2

T4

3

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20449

1

T1

1

T2

20

T4

35

auto[1]

6157

1

T1

1

T3

27

T4

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

2

T2

20

T3

3

auto[1]

3833

1

T3

24

T4

4

T5

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	47	1			T121	7		T136	15		T314	12
values[0]	48	1			T122	12		T251	19		T315	6
values[1]	694	1			T1	1		T12	5		T122	12
values[2]	783	1			T43	14		T120	21		T138	47
values[3]	659	1			T45	14		T120	23		T133	1
values[4]	791	1			T8	1		T13	9		T29	17
values[5]	689	1			T36	3		T33	7		T206	15
values[6]	587	1			T4	3		T8	1		T123	13
values[7]	662	1			T11	1		T28	2		T44	22
values[8]	643	1			T8	1		T30	1		T122	1
values[9]	3453	1			T1	1		T3	27		T5	21
minimum	17550	1			T2	20		T4	35		T7	124

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	953	1			T1	1		T43	14		T122	24
values[1]	629	1			T12	5		T120	21		T138	22
values[2]	751	1			T44	6		T45	14		T120	23
values[3]	822	1			T8	1		T13	9		T29	17
values[4]	525	1			T8	1		T36	3		T129	25
values[5]	786	1			T4	3		T123	13		T50	31
values[6]	2814	1			T3	27		T5	21		T6	4
values[7]	804	1			T30	1		T44	22		T122	1
values[8]	804	1			T1	1		T8	1		T28	21
values[9]	141	1			T11	6		T50	12		T191	2
minimum	17577	1			T2	20		T4	35		T7	124

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

4265

1

T6

3

T12

1

T13

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T43	9		T122	12		T129	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	1		T122	12		T132	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T140	13		T80	1		T202	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T12	4		T120	11		T138	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T44	3		T120	12		T138	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T45	5		T133	1		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T8	1		T13	7		T33	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T29	3		T50	1		T206	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	1		T141	1		T81	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T36	2		T129	13		T162	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T50	16		T139	1		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T4	1		T123	11		T125	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1598	1			T3	3		T5	2		T6	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T11	1		T28	1		T45	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T122	1		T140	16		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T30	1		T44	10		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T28	11		T29	19		T121	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	1		T8	1		T128	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T191	1		T145	19		T227	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T11	1		T50	12		T80	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17444	1			T2	20		T4	33		T7	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T316	1		T317	7		T318	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T43	5		T129	2		T138	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T132	10		T41	3		T35	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T140	12		T202	8		T308	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	1		T120	10		T138	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T44	3		T120	11		T138	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T45	9		T18	5		T252	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T13	2		T33	6		T223	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T29	14		T50	13		T206	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T141	4		T81	7		T202	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T36	1		T129	12		T162	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T50	15		T139	3		T208	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T4	2		T123	2		T135	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	941	1			T3	24		T5	19		T10	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T28	1		T45	2		T221	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T140	11		T141	15		T208	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T44	12		T135	6		T35	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T28	10		T29	16		T139	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T128	5		T139	13		T162	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T191	1		T145	12		T227	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T11	5		T136	7		T144	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T4	2		T33	1		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T316	4		T317	2		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T121	7		T272	3		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T136	8		T314	12		T319	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T122	12		T299	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T251	9		T315	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T129	5		T124	1		T138	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	1		T12	4		T122	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T43	9		T138	12		T140	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T120	11		T138	11		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T120	12		T16	5		T200	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T45	5		T133	1		T38	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T8	1		T13	7		T44	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T29	3		T50	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T33	1		T141	1		T81	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T36	2		T206	8		T162	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T8	1		T50	16		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	1		T123	11		T129	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T130	4		T41	1		T213	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	1		T28	1		T44	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T122	1		T141	1		T208	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T8	1		T30	1		T35	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1817	1			T3	3		T5	2		T6	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T1	1		T11	1		T128	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17442	1			T2	20		T4	33		T7	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T272	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T136	7		T320	2		T307	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T299	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T251	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T129	2		T138	8		T191	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T12	1		T132	10		T35	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T43	5		T138	13		T140	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T120	10		T138	11		T132	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T120	11		T16	2		T200	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T45	9		T18	5		T294	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	2		T44	3		T132	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T29	14		T50	13		T252	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T33	6		T141	4		T81	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T36	1		T206	7		T162	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T50	15		T139	3		T208	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T4	2		T123	2		T129	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T130	7		T213	2		T98	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T28	1		T44	12		T45	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T141	15		T208	9		T42	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T35	10		T199	9		T267	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1057	1			T3	24		T5	19		T10	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T11	5		T128	5		T139	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	2		T33	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T43	6		T122	1		T129	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T1	1		T122	1		T132	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T140	13		T80	1		T202	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T12	4		T120	11		T138	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T44	4		T120	12		T138	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T45	10		T133	1		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T8	1		T13	7		T33	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T29	15		T50	14		T206	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T8	1		T141	5		T81	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T36	3		T129	13		T162	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T50	16		T139	4		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T4	3		T123	3		T125	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T3	27		T5	21		T6	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T11	1		T28	2		T45	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T122	1		T140	12		T141	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T30	1		T44	13		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T28	11		T29	17		T121	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T1	1		T8	1		T128	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T191	2		T145	13		T227	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T11	6		T50	1		T80	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17562	1			T2	20		T4	35		T7	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T316	5		T317	3		T318	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T43	8		T122	11		T129	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T122	11		T142	4		T41	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T140	12		T202	9		T96	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T12	1		T120	10		T138	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T44	2		T120	11		T138	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T45	4		T270	12		T277	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T13	2		T223	2		T219	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T29	2		T206	7		T213	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T202	12		T217	13		T251	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T129	12		T162	12		T242	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T50	15		T208	14		T151	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T123	10		T125	2		T135	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1267	1			T6	3		T27	28		T46	42
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T45	10		T221	12		T321	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T140	15		T208	14		T42	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T44	9		T135	5		T35	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T28	10		T29	18		T121	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T125	1		T198	9		T196	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T145	18		T227	7		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T50	11		T136	7		T144	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T317	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T121	1		T272	4		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T136	8		T314	1		T319	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T122	1		T299	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T251	11		T315	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T129	3		T124	1		T138	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T1	1		T12	4		T122	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T43	6		T138	14		T140	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T120	11		T138	12		T132	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T120	12		T16	6		T200	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T45	10		T133	1		T38	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T8	1		T13	7		T44	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T29	15		T50	14		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T33	7		T141	5		T81	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T36	3		T206	8		T162	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	1		T50	16		T139	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T4	3		T123	3		T129	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T130	8		T41	1		T213	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	1		T28	2		T44	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T122	1		T141	16		T208	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T8	1		T30	1		T35	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1430	1			T3	27		T5	21		T6	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T1	1		T11	6		T128	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17550	1			T2	20		T4	35		T7	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T121	6		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T136	7		T314	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T122	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T251	8		T315	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T129	4		T138	6		T191	22
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T12	1		T122	11		T19	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T43	8		T138	11		T140	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T120	10		T138	10		T40	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T120	11		T16	1		T200	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T45	4		T216	18		T270	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	2		T44	2		T130	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T29	2		T244	11		T203	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T217	13		T214	15		T232	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T206	7		T162	12		T213	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T50	15		T208	14		T151	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T123	10		T129	12		T135	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T130	3		T213	8		T98	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T44	9		T45	10		T125	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T208	14		T42	1		T98	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T35	11		T199	10		T19	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1444	1			T6	3		T27	28		T28	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T50	11		T125	1		T198	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

auto[0]

4265

1

T6

3

T12

1

T13

2