Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26606

1

T1

2

T2

20

T3

27

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23150

1

T2

20

T3

27

T4

35

auto[ADC_CTRL_FILTER_COND_OUT]

3456

1

T1

2

T4

3

T8

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20391

1

T1

1

T2

20

T4

35

auto[1]

6215

1

T1

1

T3

27

T4

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

2

T2

20

T3

3

auto[1]

3833

1

T3

24

T4

4

T5

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	722	1			T7	4		T37	1		T12	7
values[0]	36	1			T44	6		T138	15		T322	1
values[1]	639	1			T8	1		T30	1		T122	12
values[2]	2844	1			T3	27		T5	21		T6	4
values[3]	747	1			T12	5		T121	7		T122	13
values[4]	708	1			T11	7		T13	9		T43	14
values[5]	782	1			T4	3		T8	1		T44	22
values[6]	498	1			T1	2		T140	27		T81	2
values[7]	700	1			T29	17		T139	14		T130	8
values[8]	834	1			T29	35		T128	6		T50	12
values[9]	1035	1			T50	45		T125	2		T132	14
minimum	17061	1			T2	20		T4	35		T7	120

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	525	1			T30	1		T45	14		T36	3
values[1]	3016	1			T3	27		T5	21		T6	4
values[2]	673	1			T11	1		T12	5		T121	7
values[3]	694	1			T8	1		T11	6		T13	9
values[4]	718	1			T4	3		T44	22		T45	13
values[5]	587	1			T1	2		T134	1		T81	2
values[6]	761	1			T29	17		T50	12		T139	14
values[7]	742	1			T29	35		T128	6		T132	14
values[8]	895	1			T50	31		T124	1		T138	22
values[9]	234	1			T28	2		T50	14		T133	1
minimum	17761	1			T2	20		T4	35		T7	124

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

4265

1

T6

3

T12

1

T13

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T36	2		T191	23		T142	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T30	1		T45	5		T122	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1678	1			T3	3		T5	2		T6	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T123	11		T129	18		T38	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T121	7		T125	3		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	1		T12	4		T120	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T43	9		T132	1		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T8	1		T11	1		T13	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T45	11		T140	16		T178	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T4	1		T44	10		T78	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T81	1		T136	1		T189	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T1	2		T134	1		T252	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T29	3		T130	3		T208	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T50	12		T139	1		T223	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T29	19		T128	1		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T132	1		T215	19		T202	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T124	1		T125	2		T191	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T50	16		T138	11		T15	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T50	1		T141	1		T81	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T28	1		T133	1		T202	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17488	1			T2	20		T4	33		T7	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T8	1		T138	7		T18	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T36	1		T191	10		T219	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T45	9		T139	12		T151	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1024	1			T3	24		T5	19		T10	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T123	2		T129	14		T16	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T250	12		T251	4		T98	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T12	1		T120	11		T138	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T43	5		T132	8		T224	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T11	5		T13	2		T120	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T45	2		T140	11		T196	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T4	2		T44	12		T81	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T81	1		T136	10		T251	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T252	7		T243	10		T253	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T29	14		T130	5		T208	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T139	13		T223	2		T141	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T29	16		T128	5		T33	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T132	13		T215	1		T202	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T191	1		T140	12		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T50	15		T138	11		T15	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T50	13		T141	15		T81	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T28	1		T202	10		T94	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T4	2		T44	3		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T138	8		T18	3		T321	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	558	1			T7	4		T37	1		T12	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T28	1		T134	1		T162	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T44	3		T322	1		T323	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T138	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T191	23		T135	17		T219	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T8	1		T30	1		T122	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1634	1			T3	3		T5	2		T6	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T45	5		T123	11		T38	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T121	7		T122	13		T125	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T12	4		T120	12		T129	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T43	9		T34	1		T78	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T11	2		T13	7		T130	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T45	11		T132	1		T178	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T4	1		T8	1		T44	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T140	16		T81	1		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T1	2		T252	1		T243	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T29	3		T130	3		T208	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T139	1		T134	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T29	19		T128	1		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T50	12		T138	11		T223	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T50	1		T125	2		T191	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T50	16		T132	1		T15	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16953	1			T2	20		T4	33		T7	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T141	15		T213	7		T250	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T28	1		T162	1		T135	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T44	3		T323	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T138	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T191	10		T135	19		T219	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T139	12		T151	8		T18	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	985	1			T3	24		T5	19		T10	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T45	9		T123	2		T16	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T214	16		T250	12		T224	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T12	1		T120	11		T129	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T43	5		T251	4		T98	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T11	5		T13	2		T130	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T45	2		T132	8		T196	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T4	2		T44	12		T120	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T140	11		T81	1		T136	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T252	7		T243	10		T21	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T29	14		T130	5		T208	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T139	13		T141	4		T19	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T29	16		T128	5		T33	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T138	11		T223	2		T215	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T50	13		T191	1		T140	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T50	15		T132	13		T15	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	2		T33	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T36	3		T191	11		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T30	1		T45	10		T122	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1362	1			T3	27		T5	21		T6	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T123	3		T129	16		T38	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T121	1		T125	1		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	1		T12	4		T120	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T43	6		T132	9		T34	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T8	1		T11	6		T13	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T45	3		T140	12		T178	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T4	3		T44	13		T78	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T81	2		T136	11		T189	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T1	2		T134	1		T252	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T29	15		T130	6		T208	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T50	1		T139	14		T223	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T29	17		T128	6		T33	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T132	14		T215	2		T202	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T124	1		T125	1		T191	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T50	16		T138	12		T15	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T50	14		T141	16		T81	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T28	2		T133	1		T202	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17618	1			T2	20		T4	35		T7	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T8	1		T138	9		T18	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T191	22		T142	2		T219	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T45	4		T122	11		T232	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1340	1			T6	3		T27	28		T28	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T123	10		T129	16		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T121	6		T125	2		T250	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T12	1		T120	11		T138	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T43	8		T270	11		T324	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	2		T120	10		T130	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T45	10		T140	15		T217	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T44	9		T211	12		T198	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T189	12		T251	8		T270	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T21	1		T230	15		T325	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T29	2		T130	2		T208	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T50	11		T223	2		T218	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T29	18		T207	12		T136	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T215	18		T202	9		T136	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T125	1		T140	12		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T50	15		T138	10		T15	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T250	3		T257	11		T289	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T202	10		T94	18		T259	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T44	2		T135	16		T144	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T138	6		T18	4		T305	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	589	1			T7	4		T37	1		T12	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T28	2		T134	1		T162	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T44	4		T322	1		T323	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T138	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T191	11		T135	20		T219	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T8	1		T30	1		T122	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1326	1			T3	27		T5	21		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T45	10		T123	3		T38	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T121	1		T122	2		T125	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T12	4		T120	12		T129	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T43	6		T34	1		T78	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T11	7		T13	7		T130	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T45	3		T132	9		T178	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T4	3		T8	1		T44	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T140	12		T81	2		T136	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T1	2		T252	8		T243	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T29	15		T130	6		T208	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T139	14		T134	1		T141	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T29	17		T128	6		T33	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T50	1		T138	12		T223	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T50	14		T125	1		T191	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T50	16		T132	14		T15	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17061	1			T2	20		T4	35		T7	120
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T213	8		T250	3		T185	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T135	5		T144	14		T154	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T44	2		T323	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T138	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T191	22		T135	16		T219	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T122	11		T18	4		T203	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1293	1			T6	3		T27	28		T28	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T45	4		T123	10		T16	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T121	6		T122	11		T125	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	1		T120	11		T129	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T43	8		T251	2		T98	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T13	2		T130	3		T39	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T45	10		T217	13		T196	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T44	9		T120	10		T211	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T140	15		T189	12		T251	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T21	1		T325	6		T326	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T29	2		T130	2		T208	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T218	1		T19	6		T156	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T29	18		T217	8		T136	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T50	11		T138	10		T223	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T125	1		T140	12		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T50	15		T15	2		T202	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

auto[0]

4265

1

T6

3

T12

1

T13

2