Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26606

1

T1

2

T2

20

T3

27

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23479

1

T1

2

T2

20

T3

27

auto[ADC_CTRL_FILTER_COND_OUT]

3127

1

T4

3

T8

2

T11

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20544

1

T1

1

T2

20

T4

38

auto[1]

6062

1

T1

1

T3

27

T5

21

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

2

T2

20

T3

3

auto[1]

3833

1

T3

24

T4

4

T5

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	345	1			T126	1		T16	7		T142	9
values[0]	91	1			T136	23		T98	14		T224	7
values[1]	605	1			T28	21		T50	12		T15	9
values[2]	429	1			T13	9		T28	2		T30	1
values[3]	654	1			T1	1		T121	7		T122	12
values[4]	747	1			T8	1		T11	6		T125	3
values[5]	3118	1			T3	27		T4	3		T5	21
values[6]	678	1			T44	22		T122	1		T120	21
values[7]	755	1			T11	1		T29	17		T128	6
values[8]	593	1			T1	1		T43	14		T45	13
values[9]	1041	1			T12	5		T29	35		T36	3
minimum	17550	1			T2	20		T4	35		T7	124

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	462	1			T28	23		T15	9		T142	8
values[1]	531	1			T13	9		T30	1		T44	6
values[2]	641	1			T1	1		T121	7		T122	12
values[3]	3108	1			T3	27		T5	21		T6	4
values[4]	814	1			T4	3		T8	1		T129	25
values[5]	671	1			T122	1		T120	21		T138	25
values[6]	742	1			T11	1		T29	17		T44	22
values[7]	593	1			T1	1		T43	14		T122	12
values[8]	1038	1			T12	5		T29	35		T36	3
values[9]	174	1			T215	20		T202	21		T217	9
minimum	17832	1			T2	20		T4	35		T7	124

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

4265

1

T6

3

T12

1

T13

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T142	5		T35	1		T212	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T28	12		T15	6		T142	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	7		T44	3		T42	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T30	1		T120	12		T129	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T1	1		T122	12		T123	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T121	7		T130	4		T81	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1715	1			T3	3		T5	2		T6	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T8	1		T45	5		T39	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T129	13		T200	9		T189	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T4	1		T8	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T122	1		T138	12		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T120	11		T130	3		T140	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T44	10		T45	11		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T11	1		T29	3		T217	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T1	1		T43	9		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T122	12		T50	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	365	1			T29	19		T138	7		T125	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T12	4		T36	2		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T202	11		T217	9		T166	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T215	19		T234	14		T277	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17534	1			T2	20		T4	33		T7	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T94	13		T98	8		T204	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T35	1		T212	4		T87	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T28	11		T15	3		T162	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	2		T44	3		T42	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T120	11		T129	2		T136	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T123	2		T50	15		T33	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T130	7		T81	7		T219	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1030	1			T3	24		T5	19		T10	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T45	9		T39	1		T18	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T129	12		T200	7		T137	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	2		T139	9		T191	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T138	13		T139	3		T141	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T120	10		T130	5		T140	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T44	12		T45	2		T128	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T29	14		T136	10		T213	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T43	5		T139	13		T132	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T50	13		T132	8		T141	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T29	16		T138	8		T208	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	1		T36	1		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T202	10		T166	4		T327	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T215	1		T277	12		T328	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T4	2		T33	1		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T94	11		T98	6		T204	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T126	1		T142	9		T202	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T16	5		T234	14		T277	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T136	12		T224	1		T278	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T98	8		T145	19		T187	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T50	12		T210	1		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T28	11		T15	6		T142	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	7		T44	3		T142	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T28	1		T30	1		T120	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	1		T122	12		T123	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T121	7		T129	5		T130	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T11	1		T125	3		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T8	1		T39	11		T228	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1627	1			T3	3		T5	2		T6	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T4	1		T8	1		T45	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T44	10		T122	1		T138	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T120	11		T139	1		T191	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T128	1		T80	1		T135	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T11	1		T29	3		T130	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T1	1		T43	9		T45	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T122	12		T50	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	372	1			T29	19		T138	7		T125	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T12	4		T36	2		T124	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17442	1			T2	20		T4	33		T7	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T202	10		T196	2		T201	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T16	2		T277	12		T245	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T136	11		T224	6		T278	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T98	6		T145	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T221	13		T19	4		T87	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T28	10		T15	3		T162	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T13	2		T44	3		T42	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T28	1		T120	11		T136	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T123	2		T50	15		T35	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T129	2		T130	7		T81	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T11	5		T33	6		T208	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T39	1		T18	5		T252	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1016	1			T3	24		T5	19		T10	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T4	2		T45	9		T140	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T44	12		T138	13		T139	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T120	10		T139	9		T191	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T128	5		T135	19		T297	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T29	14		T130	5		T282	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T43	5		T45	2		T138	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T50	13		T132	8		T141	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T29	16		T138	8		T191	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	1		T36	1		T77	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	2		T33	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T142	1		T35	2		T212	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T28	13		T15	7		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	7		T44	4		T42	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T30	1		T120	12		T129	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T1	1		T122	1		T123	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T121	1		T130	8		T81	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1373	1			T3	27		T5	21		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T8	1		T45	10		T39	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T129	13		T200	8		T189	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T4	3		T8	1		T139	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T122	1		T138	14		T139	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T120	11		T130	6		T140	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T44	13		T45	3		T128	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	1		T29	15		T217	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	1		T43	6		T139	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T122	1		T50	14		T132	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T29	17		T138	9		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T12	4		T36	3		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T202	11		T217	1		T166	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T215	2		T234	1		T277	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17629	1			T2	20		T4	35		T7	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T94	12		T98	7		T204	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T142	4		T234	11		T329	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T28	10		T15	2		T142	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	2		T44	2		T42	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T120	11		T129	4		T136	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T122	11		T123	10		T50	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T121	6		T130	3		T219	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1372	1			T6	3		T27	28		T46	42
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T45	4		T39	6		T18	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T129	12		T200	8		T189	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T191	22		T140	15		T223	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T138	11		T40	1		T202	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T120	10		T130	2		T140	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T44	9		T45	10		T138	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T29	2		T217	13		T213	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T43	8		T199	10		T283	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T122	11		T207	12		T196	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T29	18		T138	6		T125	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	1		T16	1		T17	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T202	10		T217	8		T327	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T215	18		T234	13		T277	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T50	11		T221	12		T136	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T94	12		T98	7		T230	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T126	1		T142	1		T202	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T16	6		T234	1		T277	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T136	12		T224	7		T278	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T98	7		T145	13		T187	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T50	1		T210	1		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T28	11		T15	7		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T13	7		T44	4		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T28	2		T30	1		T120	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T1	1		T122	1		T123	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T121	1		T129	3		T130	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T11	6		T125	1		T33	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T8	1		T39	6		T228	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1347	1			T3	27		T5	21		T6	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T4	3		T8	1		T45	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T44	13		T122	1		T138	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T120	11		T139	10		T191	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T128	6		T80	1		T135	20
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	1		T29	15		T130	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	1		T43	6		T45	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T122	1		T50	14		T132	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T29	17		T138	9		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	4		T36	3		T124	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17550	1			T2	20		T4	35		T7	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T142	8		T202	10		T196	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T16	1		T234	13		T277	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T136	11		T280	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T98	7		T145	18		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T50	11		T221	12		T19	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T28	10		T15	2		T142	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T13	2		T44	2		T142	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T120	11		T136	7		T213	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T122	11		T123	10		T50	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T121	6		T129	4		T130	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T125	2		T208	14		T211	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T39	6		T18	5		T216	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1296	1			T6	3		T27	28		T46	42
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T45	4		T140	15		T223	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T44	9		T138	11		T200	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T120	10		T191	22		T140	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T135	16		T284	4		T190	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T29	2		T130	2		T217	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T43	8		T45	10		T138	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T122	11		T207	12		T196	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T29	18		T138	6		T125	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	1		T17	1		T41	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

auto[0]

4265

1

T6

3

T12

1

T13

2