Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26606

1

T1

2

T2

20

T3

27

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20791

1

T1

1

T2

20

T4

35

auto[ADC_CTRL_FILTER_COND_OUT]

5815

1

T1

1

T3

27

T4

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20610

1

T1

1

T2

20

T4

38

auto[1]

5996

1

T1

1

T3

27

T5

21

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

2

T2

20

T3

3

auto[1]

3833

1

T3

24

T4

4

T5

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	373	1			T44	6		T139	24		T15	9
values[0]	67	1			T210	1		T202	26		T290	6
values[1]	663	1			T45	13		T122	12		T123	13
values[2]	643	1			T1	1		T28	21		T36	3
values[3]	474	1			T12	5		T122	12		T132	14
values[4]	623	1			T11	6		T128	6		T120	21
values[5]	630	1			T11	1		T28	2		T30	1
values[6]	745	1			T1	1		T8	1		T29	17
values[7]	678	1			T8	1		T29	35		T121	7
values[8]	789	1			T4	3		T139	4		T132	11
values[9]	3371	1			T3	27		T5	21		T6	4
minimum	17550	1			T2	20		T4	35		T7	124

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	646	1			T28	21		T45	13		T123	13
values[1]	2805	1			T1	1		T3	27		T5	21
values[2]	562	1			T11	6		T122	12		T120	21
values[3]	565	1			T28	2		T43	14		T128	6
values[4]	701	1			T11	1		T29	17		T30	1
values[5]	730	1			T1	1		T8	1		T44	22
values[6]	644	1			T8	1		T29	35		T121	7
values[7]	871	1			T4	3		T139	4		T125	2
values[8]	1067	1			T8	1		T13	9		T44	6
values[9]	157	1			T81	8		T17	6		T219	1
minimum	17858	1			T2	20		T4	35		T7	124

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

4265

1

T6

3

T12

1

T13

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T123	11		T125	3		T191	23
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T28	11		T45	11		T50	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	4		T129	13		T126	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1562	1			T1	1		T3	3		T5	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T11	1		T132	1		T142	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T122	12		T120	11		T38	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T28	1		T128	1		T138	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T43	9		T130	3		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T29	3		T50	16		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T11	1		T30	1		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	1		T120	12		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T8	1		T44	10		T129	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T29	19		T121	7		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T8	1		T133	1		T208	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T34	1		T223	3		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T4	1		T139	1		T125	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T44	3		T45	5		T138	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T8	1		T13	7		T50	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T219	1		T136	1		T285	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T81	1		T17	5		T251	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T2	20		T4	33		T7	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T122	12		T41	8		T210	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T123	2		T191	10		T81	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T28	10		T45	2		T50	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T12	1		T129	12		T141	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	932	1			T3	24		T5	19		T10	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T11	5		T132	13		T35	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T120	10		T141	15		T35	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T28	1		T128	5		T138	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T43	5		T130	5		T77	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T29	14		T50	15		T33	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T206	7		T211	9		T42	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T120	11		T132	8		T191	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T44	12		T129	2		T138	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T29	16		T16	2		T81	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T208	9		T250	18		T94	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T223	2		T221	13		T196	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T4	2		T139	3		T132	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T44	3		T45	9		T138	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T13	2		T15	3		T162	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T251	4		T278	4		T246	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T81	7		T17	1		T251	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T4	2		T33	1		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T41	3		T202	13		T213	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T44	3		T139	2		T40	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T15	6		T163	8		T251	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T289	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T210	1		T202	13		T290	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T123	11		T125	3		T81	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T45	11		T122	12		T50	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T129	13		T191	23		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T1	1		T28	11		T36	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	4		T132	1		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T122	12		T38	5		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	1		T128	1		T138	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T120	11		T130	3		T77	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T28	1		T50	16		T140	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T11	1		T30	1		T43	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T1	1		T29	3		T120	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T8	1		T44	10		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T29	19		T121	7		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T8	1		T125	2		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T134	1		T16	5		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T4	1		T139	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T45	5		T138	7		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1787	1			T3	3		T5	2		T6	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17442	1			T2	20		T4	33		T7	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T44	3		T139	22		T40	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T15	3		T163	6		T251	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T289	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T202	13		T290	5		T192	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T123	2		T81	7		T196	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T45	2		T50	13		T208	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T129	12		T191	10		T39	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T28	10		T36	1		T130	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T12	1		T132	13		T141	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T141	15		T35	10		T18	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	5		T128	5		T138	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T120	10		T130	5		T77	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T28	1		T50	15		T140	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T43	5		T42	2		T20	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T29	14		T120	11		T191	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T44	12		T129	2		T138	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T29	16		T132	8		T200	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T208	9		T250	18		T293	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T16	2		T223	2		T81	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T4	2		T139	3		T132	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T45	9		T138	8		T221	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1128	1			T3	24		T5	19		T10	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	2		T33	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T123	3		T125	1		T191	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T28	11		T45	3		T50	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	4		T129	13		T126	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1272	1			T1	1		T3	27		T5	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T11	6		T132	14		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T122	1		T120	11		T38	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T28	2		T128	6		T138	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T43	6		T130	6		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T29	15		T50	16		T33	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T11	1		T30	1		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T1	1		T120	12		T132	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T8	1		T44	13		T129	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T29	17		T121	1		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T8	1		T133	1		T208	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T34	1		T223	3		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T4	3		T139	4		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T44	4		T45	10		T138	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	330	1			T8	1		T13	7		T50	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T219	1		T136	1		T285	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T81	8		T17	5		T251	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17596	1			T2	20		T4	35		T7	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T122	1		T41	8		T210	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T123	10		T125	2		T191	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T28	10		T45	10		T208	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T12	1		T129	12		T39	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1222	1			T6	3		T27	28		T46	42
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T142	2		T216	8		T96	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T122	11		T120	10		T35	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T138	10		T140	15		T250	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T43	8		T130	2		T217	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T29	2		T50	15		T142	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T206	7		T211	12		T42	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T120	11		T200	8		T198	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T44	9		T129	4		T138	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T29	18		T121	6		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T208	14		T250	16		T94	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T223	2		T221	12		T196	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T125	1		T162	12		T219	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T44	2		T45	4		T138	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T13	2		T50	11		T15	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T251	2		T234	13		T246	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T17	1		T251	8		T144	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T196	1		T216	18		T152	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T122	11		T41	3		T202	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T44	4		T139	24		T40	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T15	7		T163	7		T251	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T289	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T210	1		T202	14		T290	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T123	3		T125	1		T81	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T45	3		T122	1		T50	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T129	13		T191	11		T126	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	1		T28	11		T36	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T12	4		T132	14		T141	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T122	1		T38	5		T141	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	6		T128	6		T138	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T120	11		T130	6		T77	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T28	2		T50	16		T140	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T11	1		T30	1		T43	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T1	1		T29	15		T120	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T8	1		T44	13		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T29	17		T121	1		T132	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T8	1		T125	1		T133	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T134	1		T16	6		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T4	3		T139	4		T132	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T45	10		T138	9		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1497	1			T3	27		T5	21		T6	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17550	1			T2	20		T4	35		T7	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T44	2		T40	1		T135	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T15	2		T163	7		T251	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T289	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T202	12		T192	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T123	10		T125	2		T196	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T45	10		T122	11		T208	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T129	12		T191	22		T39	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T28	10		T130	3		T140	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T12	1		T142	2		T96	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T122	11		T35	11		T18	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T138	10		T216	8		T250	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T120	10		T130	2		T217	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T50	15		T140	15		T213	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T43	8		T42	1		T270	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T29	2		T120	11		T142	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T44	9		T129	4		T138	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T29	18		T121	6		T200	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T125	1		T208	14		T250	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T16	1		T223	2		T151	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T94	12		T245	2		T297	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T45	4		T138	6		T221	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1418	1			T6	3		T13	2		T27	28

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

auto[0]

4265

1

T6

3

T12

1

T13

2