Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T123	3		T129	13		T50	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T28	11		T29	15		T134	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T45	3		T138	14		T132	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T8	1		T122	1		T50	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T8	1		T30	1		T45	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T29	17		T43	6		T120	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T3	27		T5	21		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T38	5		T141	1		T81	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T8	1		T36	3		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T141	16		T39	6		T136	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	6		T125	1		T132	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	1		T12	4		T128	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T13	7		T121	1		T215	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T133	1		T41	7		T137	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T134	1		T34	1		T141	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T28	2		T122	1		T129	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T4	3		T11	1		T44	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T1	1		T15	7		T207	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T44	4		T18	7		T221	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T140	12		T162	11		T222	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17552	1			T2	20		T4	35		T7	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T165	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T123	10		T129	12		T138	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T28	10		T29	2		T202	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T45	10		T138	11		T206	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T122	11		T50	11		T191	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T45	4		T120	11		T130	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T29	18		T43	8		T120	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1272	1			T6	3		T27	28		T46	42
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T219	6		T221	20		T196	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T50	15		T40	1		T42	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T39	6		T136	11		T234	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T125	1		T223	2		T198	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	1		T138	6		T130	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T13	2		T121	6		T215	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T41	3		T137	9		T235	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T208	14		T35	11		T189	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T122	11		T129	4		T125	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T44	9		T16	1		T142	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T15	2		T207	12		T137	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T44	2		T18	5		T221	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T140	15		T162	12		T236	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T165	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T139	4		T144	11		T226	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T29	15		T154	4		T227	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T50	14		T138	12		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T28	11		T50	1		T134	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T123	3		T129	13		T138	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T8	1		T122	1		T139	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T8	1		T45	13		T132	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T29	17		T43	6		T120	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T3	27		T5	21		T6	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T81	8		T228	1		T229	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T8	1		T36	3		T50	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T38	5		T141	1		T39	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T11	6		T122	1		T139	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T12	4		T138	9		T33	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T121	1		T210	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	1		T128	6		T130	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	7		T134	1		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T28	2		T122	1		T129	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T4	3		T11	1		T44	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T1	1		T132	14		T15	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17550	1			T2	20		T4	35		T7	124
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T144	11		T226	8		T230	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T29	2		T154	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T138	10		T142	4		T213	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T28	10		T50	11		T202	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T123	10		T129	12		T138	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T122	11		T191	22		T17	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T45	14		T130	3		T200	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T29	18		T43	8		T120	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1229	1			T6	3		T27	28		T46	42
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T219	6		T221	20		T196	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T50	15		T40	1		T42	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T39	6		T136	11		T94	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T125	1		T223	2		T198	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	1		T138	6		T211	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T121	6		T232	11		T233	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T130	2		T135	5		T137	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	2		T208	14		T35	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T122	11		T129	4		T125	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T44	11		T16	1		T142	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T15	2		T140	15		T208	14

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

auto[0]

4265

1

T6

3

T12

1

T13

2