Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26606

1

T1

2

T2

20

T3

27

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22997

1

T1

2

T2

20

T3

27

auto[ADC_CTRL_FILTER_COND_OUT]

3609

1

T4

3

T8

2

T11

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20698

1

T1

2

T2

20

T4

38

auto[1]

5908

1

T3

27

T5

21

T6

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

2

T2

20

T3

3

auto[1]

3833

1

T3

24

T4

4

T5

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	241	1			T44	6		T191	35		T40	7
values[1]	778	1			T28	2		T128	6		T122	12
values[2]	816	1			T11	6		T44	22		T123	13
values[3]	594	1			T1	1		T4	3		T43	14
values[4]	668	1			T8	1		T13	9		T45	13
values[5]	526	1			T139	4		T125	5		T140	25
values[6]	684	1			T129	7		T132	14		T81	16
values[7]	723	1			T29	35		T45	14		T121	7
values[8]	3030	1			T3	27		T5	21		T6	4
values[9]	996	1			T1	1		T8	2		T28	21
minimum	17550	1			T2	20		T4	35		T7	124

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	757	1			T128	6		T122	12		T123	13
values[1]	881	1			T4	3		T11	6		T43	14
values[2]	519	1			T1	1		T36	3		T122	13
values[3]	676	1			T8	1		T13	9		T45	13
values[4]	518	1			T139	4		T125	3		T134	1
values[5]	737	1			T129	7		T132	14		T81	8
values[6]	3085	1			T3	27		T5	21		T6	4
values[7]	763	1			T8	1		T11	1		T12	5
values[8]	874	1			T1	1		T30	1		T44	6
values[9]	107	1			T8	1		T151	5		T185	3
minimum	17689	1			T2	20		T4	35		T7	124

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

4265

1

T6

3

T12

1

T13

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T123	11		T15	6		T81	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T128	1		T122	12		T50	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T43	9		T44	10		T78	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T4	1		T11	1		T139	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T1	1		T122	13		T130	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T36	2		T130	4		T208	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T8	1		T138	7		T140	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T13	7		T45	11		T120	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T125	3		T16	5		T142	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T139	1		T134	1		T206	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T129	5		T81	1		T198	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T132	1		T212	1		T18	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1690	1			T3	3		T5	2		T6	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T45	5		T120	11		T50	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	4		T28	11		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T8	1		T11	1		T29	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T1	1		T129	13		T50	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T30	1		T44	3		T208	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T20	6		T193	1		T237	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T8	1		T151	2		T185	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17474	1			T2	20		T4	33		T7	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T28	1		T126	1		T238	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T123	2		T15	3		T81	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T128	5		T50	15		T139	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T43	5		T44	12		T202	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T4	2		T11	5		T139	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T130	5		T19	4		T239	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T36	1		T130	7		T208	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T138	8		T140	12		T42	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T13	2		T45	2		T120	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T16	2		T94	13		T145	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T139	3		T206	7		T81	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T129	2		T81	7		T198	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T132	13		T212	4		T18	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1010	1			T3	24		T5	19		T10	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T45	9		T120	10		T138	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T12	1		T28	10		T33	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T29	14		T200	7		T207	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T129	12		T50	13		T191	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T44	3		T208	9		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T20	4		T193	10		T237	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T151	3		T240	4		T209	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T4	2		T33	1		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T28	1		T230	11		T236	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T191	24		T20	6		T241	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T44	3		T40	6		T145	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T15	6		T81	1		T210	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T28	1		T128	1		T122	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T44	10		T123	11		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	1		T139	1		T211	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T1	1		T43	9		T122	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	1		T139	1		T130	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T8	1		T138	7		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T13	7		T45	11		T36	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T125	3		T140	13		T16	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T139	1		T125	2		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T129	5		T81	1		T198	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T132	1		T81	1		T212	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T29	19		T121	7		T140	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T45	5		T120	11		T50	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1676	1			T3	3		T5	2		T6	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	1		T200	9		T142	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T1	1		T28	11		T129	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T8	2		T29	3		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17442	1			T2	20		T4	33		T7	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T191	11		T20	4		T241	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T44	3		T40	1		T145	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T15	3		T81	1		T196	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T28	1		T128	5		T50	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T44	12		T123	2		T202	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T11	5		T139	13		T211	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T43	5		T130	5		T19	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T4	2		T139	9		T130	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T138	8		T42	2		T135	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T13	2		T45	2		T36	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T140	12		T16	2		T242	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T139	3		T206	7		T243	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T129	2		T81	7		T198	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T132	13		T81	7		T212	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T29	16		T140	11		T199	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T45	9		T120	10		T138	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1032	1			T3	24		T5	19		T10	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T200	7		T137	10		T244	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T28	10		T129	12		T50	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T29	14		T208	9		T151	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	2		T33	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T123	3		T15	7		T81	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T128	6		T122	1		T50	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T43	6		T44	13		T78	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T4	3		T11	6		T139	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T1	1		T122	2		T130	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T36	3		T130	8		T208	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T8	1		T138	9		T140	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T13	7		T45	3		T120	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T125	1		T16	6		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T139	4		T134	1		T206	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T129	3		T81	8		T198	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T132	14		T212	5		T18	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1356	1			T3	27		T5	21		T6	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T45	10		T120	11		T50	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T12	4		T28	11		T124	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T8	1		T11	1		T29	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	1		T129	13		T50	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T30	1		T44	4		T208	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T20	5		T193	11		T237	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T8	1		T151	4		T185	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17588	1			T2	20		T4	35		T7	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T28	2		T126	1		T238	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T123	10		T15	2		T196	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T122	11		T50	15		T215	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T43	8		T44	9		T202	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T211	12		T135	16		T136	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T122	11		T130	2		T216	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T130	3		T208	14		T17	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T138	6		T140	12		T42	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	2		T45	10		T120	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T125	2		T16	1		T142	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T206	7		T142	4		T18	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T129	4		T198	9		T217	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T213	7		T218	1		T144	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1344	1			T6	3		T27	28		T29	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T45	4		T120	10		T50	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	1		T28	10		T223	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T29	2		T200	8		T142	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T129	12		T191	22		T39	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T44	2		T208	14		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T20	5		T220	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T151	1		T185	2		T240	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T245	2		T226	8		T246	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T230	10		T236	6		T247	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	*	--	--	2
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T191	13		T20	5		T241	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T44	4		T40	6		T145	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	7		T81	2		T210	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T28	2		T128	6		T122	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T44	13		T123	3		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T11	6		T139	14		T211	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	1		T43	6		T122	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T4	3		T139	10		T130	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T8	1		T138	9		T133	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	7		T45	3		T36	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T125	1		T140	13		T16	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T139	4		T125	1		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T129	3		T81	8		T198	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T132	14		T81	8		T212	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T29	17		T121	1		T140	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T45	10		T120	11		T50	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1376	1			T3	27		T5	21		T6	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T11	1		T200	8		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T1	1		T28	11		T129	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T8	2		T29	15		T30	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17550	1			T2	20		T4	35		T7	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T191	22		T20	5		T248	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T44	2		T40	1		T145	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T15	2		T196	7		T234	24
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T122	11		T50	15		T215	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T44	9		T123	10		T202	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T211	12		T135	16		T136	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T43	8		T122	11		T130	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T130	3		T208	14		T17	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T138	6		T42	1		T135	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	2		T45	10		T120	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T125	2		T140	12		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T125	1		T206	7		T142	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T129	4		T198	9		T217	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T213	7		T218	1		T144	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T29	18		T121	6		T140	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T45	4		T120	10		T50	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T6	3		T12	1		T27	28
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T200	8		T142	8		T216	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T28	10		T129	12		T39	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T29	2		T208	14		T151	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

auto[0]

4265

1

T6

3

T12

1

T13

2