Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26606

1

T1

2

T2

20

T3

27

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23351

1

T2

20

T3

27

T4

38

auto[ADC_CTRL_FILTER_COND_OUT]

3255

1

T1

2

T8

1

T11

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20410

1

T1

2

T2

20

T4

38

auto[1]

6196

1

T3

27

T5

21

T6

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

2

T2

20

T3

3

auto[1]

3833

1

T3

24

T4

4

T5

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	489	1			T7	4		T37	1		T12	7
values[0]	62	1			T122	12		T138	15		T219	14
values[1]	622	1			T8	1		T30	1		T44	6
values[2]	2776	1			T3	27		T5	21		T6	4
values[3]	817	1			T12	5		T121	7		T122	13
values[4]	683	1			T11	7		T13	9		T43	14
values[5]	800	1			T4	3		T8	1		T44	22
values[6]	528	1			T1	2		T140	27		T78	1
values[7]	714	1			T29	17		T139	14		T130	8
values[8]	827	1			T29	35		T128	6		T50	12
values[9]	1227	1			T28	2		T50	45		T124	1
minimum	17061	1			T2	20		T4	35		T7	120

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	749	1			T8	2		T30	1		T44	6
values[1]	3078	1			T3	27		T5	21		T6	4
values[2]	587	1			T11	1		T12	5		T120	23
values[3]	721	1			T8	1		T11	6		T13	9
values[4]	727	1			T4	3		T43	14		T44	22
values[5]	575	1			T1	2		T134	1		T81	2
values[6]	772	1			T29	17		T50	12		T139	14
values[7]	750	1			T29	35		T128	6		T132	14
values[8]	847	1			T50	31		T124	1		T138	22
values[9]	249	1			T28	2		T50	14		T133	1
minimum	17551	1			T2	20		T4	35		T7	124

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

4265

1

T6

3

T12

1

T13

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T8	1		T36	2		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T8	1		T30	1		T44	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1714	1			T3	3		T5	2		T6	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T123	11		T129	18		T38	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T125	3		T77	1		T210	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	1		T12	4		T120	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T8	1		T121	7		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T11	1		T13	7		T120	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T4	1		T43	9		T45	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T44	10		T78	1		T211	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T143	1		T136	1		T189	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	2		T134	1		T81	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T29	3		T130	3		T208	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T50	12		T139	1		T223	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T29	19		T132	1		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T128	1		T215	19		T207	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T125	2		T191	1		T140	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T50	16		T124	1		T138	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T50	1		T133	1		T40	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T28	1		T81	1		T212	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17442	1			T2	20		T4	33		T7	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T249	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T36	1		T139	3		T135	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T44	3		T138	8		T139	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1013	1			T3	24		T5	19		T10	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T123	2		T129	14		T16	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T77	10		T250	12		T251	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	1		T120	11		T138	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T132	8		T130	7		T39	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T11	5		T13	2		T120	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T4	2		T43	5		T45	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T44	12		T211	9		T221	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T136	10		T251	10		T145	25
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T81	1		T252	7		T253	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T29	14		T130	5		T208	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T139	13		T223	2		T141	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T29	16		T132	13		T33	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T128	5		T215	1		T207	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T191	1		T140	12		T141	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T50	15		T138	11		T15	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T50	13		T40	1		T254	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T28	1		T81	7		T212	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	2		T33	1		T16	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	489	1			T7	4		T37	1		T12	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T219	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T122	12		T138	7		T187	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T139	1		T208	15		T135	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T8	1		T30	1		T44	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1595	1			T3	3		T5	2		T6	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T123	11		T38	5		T16	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T121	7		T122	13		T125	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T12	4		T120	12		T129	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T43	9		T130	4		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	2		T13	7		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T4	1		T8	1		T45	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T44	10		T120	11		T211	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T140	16		T217	14		T136	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T1	2		T78	1		T81	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T29	3		T130	3		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T139	1		T134	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T29	19		T80	1		T35	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T128	1		T50	12		T223	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T50	1		T125	2		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	375	1			T28	1		T50	16		T124	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16953	1			T2	20		T4	33		T7	120
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T219	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T138	8		T255	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T139	3		T208	9		T135	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T44	3		T139	9		T191	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	958	1			T3	24		T5	19		T10	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T123	2		T16	2		T200	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T77	10		T162	10		T202	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T12	1		T120	11		T129	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T43	5		T130	7		T39	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T11	5		T13	2		T42	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T4	2		T45	2		T132	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T44	12		T120	10		T211	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T140	11		T136	10		T251	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T81	1		T21	7		T205	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T29	14		T130	5		T33	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T139	13		T141	4		T252	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T29	16		T35	1		T202	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T128	5		T223	2		T215	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T50	13		T132	13		T191	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T28	1		T50	15		T138	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	2		T33	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T8	1		T36	3		T139	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T8	1		T30	1		T44	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1353	1			T3	27		T5	21		T6	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T123	3		T129	16		T38	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T125	1		T77	11		T210	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	1		T12	4		T120	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T8	1		T121	1		T132	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	6		T13	7		T120	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T4	3		T43	6		T45	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T44	13		T78	1		T211	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T143	1		T136	11		T189	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T1	2		T134	1		T81	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T29	15		T130	6		T208	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T50	1		T139	14		T223	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T29	17		T132	14		T33	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T128	6		T215	2		T207	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T125	1		T191	2		T140	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T50	16		T124	1		T138	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T50	14		T133	1		T40	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T28	2		T81	8		T212	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17550	1			T2	20		T4	35		T7	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T249	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T142	2		T135	16		T219	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T44	2		T122	11		T138	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1374	1			T6	3		T27	28		T28	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T123	10		T129	16		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T125	2		T250	13		T251	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	1		T120	11		T138	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T121	6		T130	3		T39	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	2		T120	10		T42	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T43	8		T45	10		T140	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T44	9		T211	12		T221	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T189	12		T218	1		T251	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T21	1		T205	9		T256	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T29	2		T130	2		T208	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T50	11		T223	2		T142	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T29	18		T202	9		T136	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T215	18		T207	12		T136	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T125	1		T140	12		T41	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T50	15		T138	10		T15	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T40	1		T257	11		T258	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T202	10		T94	18		T259	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	489	1			T7	4		T37	1		T12	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T219	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T122	1		T138	9		T187	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T139	4		T208	10		T135	20
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T8	1		T30	1		T44	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1293	1			T3	27		T5	21		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T123	3		T38	5		T16	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T121	1		T122	2		T125	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T12	4		T120	12		T129	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T43	6		T130	8		T126	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	7		T13	7		T133	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T4	3		T8	1		T45	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T44	13		T120	11		T211	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T140	12		T217	1		T136	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T1	2		T78	1		T81	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T29	15		T130	6		T33	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T139	14		T134	1		T141	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T29	17		T80	1		T35	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T128	6		T50	1		T223	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T50	14		T125	1		T132	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T28	2		T50	16		T124	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17061	1			T2	20		T4	35		T7	120
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T219	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T122	11		T138	6		T260	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T208	14		T135	16		T242	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T44	2		T191	22		T18	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1260	1			T6	3		T27	28		T28	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T123	10		T16	1		T200	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T121	6		T122	11		T125	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	1		T120	11		T129	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T43	8		T130	3		T39	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T13	2		T42	1		T221	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T45	10		T250	16		T234	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T44	9		T120	10		T211	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T140	15		T217	13		T189	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T21	1		T205	9		T256	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T29	2		T130	2		T208	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T142	4		T19	6		T261	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T29	18		T202	9		T136	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T50	11		T223	2		T215	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T125	1		T140	12		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T50	15		T138	10		T15	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

auto[0]

4265

1

T6

3

T12

1

T13

2