Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26606

1

T1

2

T2

20

T3

27

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23074

1

T1

1

T2

20

T3

27

auto[ADC_CTRL_FILTER_COND_OUT]

3532

1

T1

1

T4

3

T8

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21279

1

T1

1

T2

20

T4

35

auto[1]

5327

1

T1

1

T3

27

T4

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

2

T2

20

T3

3

auto[1]

3833

1

T3

24

T4

4

T5

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	53	1			T202	18		T22	2		T262	12
values[0]	62	1			T122	12		T132	9		T126	1
values[1]	747	1			T11	1		T29	35		T122	12
values[2]	2773	1			T3	27		T5	21		T6	4
values[3]	594	1			T1	1		T11	6		T44	6
values[4]	627	1			T1	1		T12	5		T13	9
values[5]	828	1			T4	3		T28	2		T29	17
values[6]	749	1			T28	21		T45	14		T123	13
values[7]	567	1			T8	1		T30	1		T50	14
values[8]	730	1			T8	2		T43	14		T134	1
values[9]	1326	1			T45	13		T128	6		T139	24
minimum	17550	1			T2	20		T4	35		T7	124

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	885	1			T11	1		T29	35		T122	12
values[1]	2828	1			T3	27		T5	21		T6	4
values[2]	606	1			T1	2		T11	6		T12	5
values[3]	682	1			T4	3		T13	9		T28	2
values[4]	827	1			T44	22		T123	13		T129	7
values[5]	644	1			T8	1		T28	21		T29	17
values[6]	590	1			T8	1		T30	1		T45	14
values[7]	837	1			T8	1		T43	14		T45	13
values[8]	968	1			T128	6		T139	10		T130	8
values[9]	175	1			T139	14		T33	7		T38	5
minimum	17564	1			T2	20		T4	35		T7	124

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

4265

1

T6

3

T12

1

T13

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T29	19		T122	12		T50	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T11	1		T120	12		T50	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1601	1			T3	3		T5	2		T6	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T122	1		T191	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	1		T11	1		T44	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	1		T12	4		T120	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T28	1		T41	7		T229	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T4	1		T13	7		T129	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T44	10		T129	5		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T123	11		T125	3		T15	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T29	3		T138	18		T140	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T8	1		T28	11		T50	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T8	1		T132	1		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T30	1		T45	5		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T43	9		T45	11		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T8	1		T35	1		T18	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T128	1		T139	1		T130	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T134	1		T17	5		T135	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T139	1		T33	1		T210	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T38	5		T19	1		T263	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17443	1			T2	20		T4	33		T7	124
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T29	16		T50	15		T132	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T120	11		T130	7		T81	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	953	1			T3	24		T5	19		T10	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T191	1		T207	11		T224	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T11	5		T44	3		T36	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T12	1		T120	10		T251	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T28	1		T41	3		T212	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T4	2		T13	2		T129	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T44	12		T129	2		T139	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T123	2		T15	3		T16	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T29	14		T138	19		T140	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T28	10		T50	13		T42	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T132	10		T141	15		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T45	9		T163	9		T152	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T43	5		T45	2		T208	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T35	1		T18	5		T221	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T128	5		T139	9		T130	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T17	1		T135	6		T35	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T139	13		T33	6		T194	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T264	8		T265	18		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T4	2		T33	1		T16	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T202	10		T22	1		T262	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T122	12		T132	1		T126	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T266	8		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T29	19		T122	12		T50	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	1		T130	4		T81	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1570	1			T3	3		T5	2		T6	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T122	1		T120	12		T50	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T1	1		T11	1		T44	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T120	11		T141	1		T217	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T129	5		T223	3		T228	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T1	1		T12	4		T13	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T28	1		T29	3		T44	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T4	1		T191	23		T15	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T139	1		T142	9		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T28	11		T45	5		T123	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T138	18		T132	1		T140	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T8	1		T30	1		T50	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T8	1		T43	9		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T8	1		T134	1		T18	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	352	1			T45	11		T128	1		T139	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	462	1			T38	5		T134	1		T17	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17442	1			T2	20		T4	33		T7	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T202	8		T22	1		T262	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T132	8		T196	7		T176	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T266	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T29	16		T50	15		T135	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T130	7		T81	1		T136	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	955	1			T3	24		T5	19		T10	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T120	11		T191	1		T250	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T11	5		T44	3		T36	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T120	10		T207	11		T199	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T129	2		T223	2		T18	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	1		T13	2		T129	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T28	1		T29	14		T44	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T4	2		T191	10		T15	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T139	3		T213	7		T242	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T28	10		T45	9		T123	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T138	19		T132	10		T140	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T50	13		T163	9		T20	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T43	5		T141	15		T208	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T18	5		T221	17		T267	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T45	2		T128	5		T139	22
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T17	1		T135	6		T35	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	2		T33	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T29	17		T122	1		T50	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T11	1		T120	12		T50	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T3	27		T5	21		T6	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T122	1		T191	2		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T1	1		T11	6		T44	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T1	1		T12	4		T120	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T28	2		T41	7		T229	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T4	3		T13	7		T129	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T44	13		T129	3		T139	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T123	3		T125	1		T15	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T29	15		T138	21		T140	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T8	1		T28	11		T50	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T8	1		T132	11		T141	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T30	1		T45	10		T134	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T43	6		T45	3		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T8	1		T35	2		T18	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T128	6		T139	10		T130	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T134	1		T17	5		T135	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T139	14		T33	7		T210	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T38	5		T19	1		T263	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17564	1			T2	20		T4	35		T7	124
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T29	18		T122	11		T50	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T120	11		T50	11		T130	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1270	1			T6	3		T27	28		T46	42
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T207	12		T245	2		T256	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T44	2		T223	2		T40	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T12	1		T120	10		T142	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T41	3		T19	7		T250	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	2		T129	12		T191	22
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T44	9		T129	4		T200	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T123	10		T125	2		T15	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T29	2		T138	16		T140	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T28	10		T42	1		T151	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T39	6		T250	3		T242	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T45	4		T163	5		T152	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T43	8		T45	10		T208	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T18	5		T221	20		T196	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T130	2		T208	14		T142	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T17	1		T135	5		T35	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T268	10		T248	17		T230	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T265	17		T269	2		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T202	9		T22	2		T262	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T122	1		T132	9		T126	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T266	8		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T29	17		T122	1		T50	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T11	1		T130	8		T81	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T3	27		T5	21		T6	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T122	1		T120	12		T50	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T1	1		T11	6		T44	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T120	11		T141	1		T217	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T129	3		T223	3		T228	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T1	1		T12	4		T13	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T28	2		T29	15		T44	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T4	3		T191	11		T15	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T139	4		T142	1		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T28	11		T45	10		T123	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T138	21		T132	11		T140	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T8	1		T30	1		T50	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T8	1		T43	6		T141	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T8	1		T134	1		T18	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T45	3		T128	6		T139	24
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	373	1			T38	5		T134	1		T17	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17550	1			T2	20		T4	35		T7	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T202	9		T262	3		T172	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T122	11		T196	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T266	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T29	18		T122	11		T50	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T130	3		T136	11		T203	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1239	1			T6	3		T27	28		T46	42
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T120	11		T50	11		T250	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T44	2		T121	6		T125	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T120	10		T217	13		T207	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T129	4		T223	2		T19	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	1		T13	2		T129	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T29	2		T44	9		T200	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T191	22		T15	2		T206	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T142	8		T213	8		T216	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T28	10		T45	4		T123	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T138	16		T140	15		T198	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T163	5		T20	5		T209	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T43	8		T208	14		T39	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T18	5		T221	20		T270	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T45	10		T130	2		T208	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	381	1			T17	1		T135	5		T35	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

auto[0]

4265

1

T6

3

T12

1

T13

2