Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26606

1

T1

2

T2

20

T3

27

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23150

1

T1

1

T2

20

T3

27

auto[ADC_CTRL_FILTER_COND_OUT]

3456

1

T1

1

T11

1

T29

35

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21093

1

T1

1

T2

20

T4

38

auto[1]

5513

1

T1

1

T3

27

T5

21

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

2

T2

20

T3

3

auto[1]

3833

1

T3

24

T4

4

T5

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	15	1			T271	11		T272	4		-	-
values[0]	107	1			T44	22		T232	36		T87	9
values[1]	635	1			T1	1		T132	11		T133	1
values[2]	802	1			T1	1		T29	35		T44	6
values[3]	600	1			T120	23		T50	43		T125	5
values[4]	637	1			T8	1		T13	9		T122	12
values[5]	2963	1			T3	27		T4	3		T5	21
values[6]	628	1			T50	14		T139	14		T34	1
values[7]	767	1			T8	1		T11	6		T12	5
values[8]	779	1			T28	2		T30	1		T121	7
values[9]	1123	1			T8	1		T43	14		T45	14
minimum	17550	1			T2	20		T4	35		T7	124

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	895	1			T1	1		T44	22		T132	11
values[1]	771	1			T1	1		T29	35		T44	6
values[2]	651	1			T122	12		T139	4		T125	3
values[3]	2886	1			T3	27		T5	21		T6	4
values[4]	778	1			T4	3		T11	1		T28	21
values[5]	567	1			T12	5		T123	13		T139	14
values[6]	881	1			T11	6		T28	2		T29	17
values[7]	729	1			T8	1		T128	6		T121	7
values[8]	738	1			T8	1		T45	14		T122	1
values[9]	158	1			T43	14		T78	1		T273	18
minimum	17552	1			T2	20		T4	35		T7	124

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

4265

1

T6

3

T12

1

T13

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T44	10		T132	1		T223	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T1	1		T133	1		T141	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	1		T44	3		T129	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T29	19		T120	12		T50	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T122	12		T139	1		T125	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T191	1		T140	16		T77	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1636	1			T3	3		T5	2		T6	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T45	11		T125	2		T228	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T4	1		T28	11		T50	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T11	1		T36	2		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T12	4		T123	11		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T139	1		T15	6		T78	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	1		T28	1		T29	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T30	1		T138	11		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T8	1		T128	1		T130	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T121	7		T122	12		T120	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T8	1		T45	5		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T122	1		T129	13		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T43	9		T78	1		T203	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T273	8		T145	19		T186	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17443	1			T2	20		T4	33		T7	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T253	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T44	12		T132	10		T223	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T141	4		T39	1		T211	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T44	3		T129	2		T50	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T29	16		T120	11		T140	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T139	3		T132	8		T130	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T191	1		T140	11		T77	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	973	1			T3	24		T5	19		T10	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T45	2		T198	8		T215	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T4	2		T28	10		T50	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T36	1		T206	7		T200	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T12	1		T123	2		T33	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T139	13		T15	3		T162	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T11	5		T28	1		T29	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T138	11		T135	19		T18	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T128	5		T130	5		T151	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T120	10		T139	9		T136	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T45	9		T35	11		T212	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T129	12		T132	13		T191	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T43	5		T203	13		T166	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T273	10		T145	12		T186	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	2		T33	1		T16	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T272	3		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T271	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T44	10		T232	21		T274	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T87	7		T176	1		T177	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T132	1		T208	15		T40	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T1	1		T133	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T1	1		T44	3		T129	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T29	19		T140	13		T38	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T50	16		T125	3		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T120	12		T50	12		T125	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T8	1		T13	7		T122	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T140	16		T126	1		T228	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1613	1			T3	3		T4	1		T5	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	1		T45	11		T36	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T50	1		T178	1		T42	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T139	1		T34	1		T78	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T8	1		T11	1		T12	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T138	11		T15	6		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T28	1		T142	5		T151	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T30	1		T121	7		T135	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T8	1		T43	9		T45	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T122	13		T120	11		T129	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17442	1			T2	20		T4	33		T7	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T272	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T271	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T44	12		T232	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T87	2		T176	8		T177	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T132	10		T208	9		T40	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T141	4		T39	1		T211	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T44	3		T129	2		T223	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T29	16		T140	12		T162	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T50	15		T132	8		T141	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T120	11		T191	1		T77	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T13	2		T139	3		T130	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T140	11		T198	8		T215	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1017	1			T3	24		T4	2		T5	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T45	2		T36	1		T206	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T50	13		T42	2		T252	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T139	13		T231	6		T244	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T11	5		T12	1		T29	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T138	11		T15	3		T162	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T28	1		T151	8		T202	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T135	19		T136	18		T213	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T43	5		T45	9		T35	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T120	10		T129	12		T139	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	2		T33	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T44	13		T132	11		T223	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T1	1		T133	1		T141	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T1	1		T44	4		T129	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T29	17		T120	12		T50	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T122	1		T139	4		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T191	2		T140	12		T77	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T3	27		T5	21		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T45	3		T125	1		T228	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T4	3		T28	11		T50	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T11	1		T36	3		T126	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	4		T123	3		T33	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T139	14		T15	7		T78	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T11	6		T28	2		T29	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T30	1		T138	12		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T8	1		T128	6		T130	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T121	1		T122	1		T120	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T8	1		T45	10		T124	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T122	1		T129	13		T132	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T43	6		T78	1		T203	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T273	11		T145	13		T186	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17551	1			T2	20		T4	35		T7	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T253	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T44	9		T223	2		T208	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T39	6		T142	2		T211	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T44	2		T129	4		T50	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T29	18		T120	11		T50	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T122	11		T125	2		T130	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T140	15		T189	10		T137	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T6	3		T13	2		T27	28
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T45	10		T125	1		T198	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T28	10		T16	1		T208	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T206	7		T200	8		T244	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T12	1		T123	10		T42	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T15	2		T162	12		T217	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T29	2		T17	1		T135	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T138	10		T142	8		T135	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T130	2		T142	4		T207	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T121	6		T122	11		T120	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T45	4		T35	11		T151	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T129	12		T191	22		T196	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T43	8		T203	14		T153	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T273	7		T145	18		T275	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T272	4		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T271	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T44	13		T232	16		T274	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T87	9		T176	9		T177	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T132	11		T208	10		T40	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T1	1		T133	1		T141	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T1	1		T44	4		T129	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T29	17		T140	13		T38	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T50	16		T125	1		T132	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T120	12		T50	1		T125	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	1		T13	7		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T140	12		T126	1		T228	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1354	1			T3	27		T4	3		T5	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T11	1		T45	3		T36	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T50	14		T178	1		T42	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T139	14		T34	1		T78	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T8	1		T11	6		T12	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T138	12		T15	7		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T28	2		T142	1		T151	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T30	1		T121	1		T135	20
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T8	1		T43	6		T45	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T122	2		T120	11		T129	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17550	1			T2	20		T4	35		T7	124
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T44	9		T232	20		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T177	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T208	14		T40	1		T41	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T39	6		T142	2		T211	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T44	2		T129	4		T223	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T29	18		T140	12		T250	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T50	15		T125	2		T221	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T120	11		T50	11		T125	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T13	2		T122	11		T130	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T140	15		T198	9		T215	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1276	1			T6	3		T27	28		T28	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T45	10		T206	7		T200	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T42	1		T217	8		T213	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T217	13		T244	11		T185	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	1		T29	2		T123	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T138	10		T15	2		T142	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T142	4		T202	19		T199	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T121	6		T135	16		T136	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T43	8		T45	4		T35	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T122	11		T120	10		T129	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

auto[0]

4265

1

T6

3

T12

1

T13

2