Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26606

1

T1

2

T2

20

T3

27

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23478

1

T1

2

T2

20

T3

27

auto[ADC_CTRL_FILTER_COND_OUT]

3128

1

T4

3

T8

2

T11

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20510

1

T1

1

T2

20

T4

38

auto[1]

6096

1

T1

1

T3

27

T5

21

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

2

T2

20

T3

3

auto[1]

3833

1

T3

24

T4

4

T5

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	27	1			T34	1		T194	3		T276	22
values[0]	85	1			T98	14		T224	7		T145	31
values[1]	568	1			T28	21		T50	12		T15	9
values[2]	453	1			T13	9		T28	2		T30	1
values[3]	730	1			T1	1		T121	7		T122	12
values[4]	619	1			T8	1		T11	6		T123	13
values[5]	3100	1			T3	27		T4	3		T5	21
values[6]	788	1			T44	22		T122	1		T120	21
values[7]	735	1			T11	1		T29	17		T128	6
values[8]	576	1			T1	1		T43	14		T45	13
values[9]	1375	1			T12	5		T29	35		T36	3
minimum	17550	1			T2	20		T4	35		T7	124

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	728	1			T28	23		T50	12		T15	9
values[1]	558	1			T13	9		T30	1		T44	6
values[2]	588	1			T1	1		T121	7		T122	12
values[3]	3119	1			T3	27		T5	21		T6	4
values[4]	801	1			T4	3		T8	1		T122	1
values[5]	708	1			T120	21		T138	25		T139	4
values[6]	723	1			T11	1		T29	17		T44	22
values[7]	609	1			T1	1		T43	14		T122	12
values[8]	952	1			T12	5		T29	35		T36	3
values[9]	255	1			T16	7		T81	2		T215	20
minimum	17565	1			T2	20		T4	35		T7	124

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

4265

1

T6

3

T12

1

T13

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T50	12		T142	5		T35	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T28	12		T15	6		T142	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T13	7		T44	3		T42	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T30	1		T120	12		T129	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T1	1		T122	12		T123	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T121	7		T130	4		T81	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1721	1			T3	3		T5	2		T6	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T8	1		T45	5		T39	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T129	13		T200	9		T189	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T4	1		T8	1		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T138	12		T139	1		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T120	11		T130	3		T140	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T44	10		T45	11		T128	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T11	1		T29	3		T217	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	1		T43	9		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T122	12		T50	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T29	19		T138	7		T125	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T12	4		T36	2		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T81	1		T202	11		T232	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T16	5		T215	19		T234	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17442	1			T2	20		T4	33		T7	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T99	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T35	1		T221	13		T136	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T28	11		T15	3		T151	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	2		T44	3		T42	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T120	11		T129	2		T162	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T123	2		T50	15		T33	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T130	7		T81	7		T219	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1029	1			T3	24		T5	19		T10	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T45	9		T39	1		T18	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T129	12		T200	7		T137	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T4	2		T139	9		T191	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T138	13		T139	3		T141	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T120	10		T130	5		T140	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T44	12		T45	2		T128	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T29	14		T136	10		T213	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T43	5		T139	13		T132	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T50	13		T132	8		T141	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T29	16		T138	8		T208	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	1		T36	1		T17	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T81	1		T202	10		T232	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T16	2		T215	1		T277	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	2		T33	1		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T99	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T34	1		T194	1		T276	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T224	1		T278	1		T279	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T98	8		T145	19		T187	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T50	12		T210	1		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T28	11		T15	6		T142	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	7		T44	3		T50	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T28	1		T30	1		T120	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T1	1		T122	12		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T121	7		T129	5		T130	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T11	1		T123	11		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T8	1		T39	11		T81	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1649	1			T3	3		T5	2		T6	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T4	1		T8	1		T45	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T44	10		T138	12		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T122	1		T120	11		T191	23
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T128	1		T80	1		T40	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	1		T29	3		T130	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T1	1		T43	9		T45	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T122	12		T50	1		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	469	1			T29	19		T138	7		T125	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	363	1			T12	4		T36	2		T124	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17442	1			T2	20		T4	33		T7	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T194	2		T276	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T224	6		T278	8		T280	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T98	6		T145	12		T281	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T221	13		T136	11		T19	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T28	10		T15	3		T162	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T13	2		T44	3		T50	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T28	1		T120	11		T136	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T162	10		T135	6		T35	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T129	2		T130	7		T219	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T11	5		T123	2		T33	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T39	1		T81	7		T18	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T3	24		T5	19		T10	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T4	2		T45	9		T139	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T44	12		T138	13		T139	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T120	10		T191	10		T140	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T128	5		T40	1		T135	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T29	14		T130	5		T282	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T43	5		T45	2		T138	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T50	13		T132	8		T141	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T29	16		T138	8		T132	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T12	1		T36	1		T16	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	2		T33	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T50	1		T142	1		T35	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T28	13		T15	7		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	7		T44	4		T42	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T30	1		T120	12		T129	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T1	1		T122	1		T123	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T121	1		T130	8		T81	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1370	1			T3	27		T5	21		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T8	1		T45	10		T39	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T129	13		T200	8		T189	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T4	3		T8	1		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T138	14		T139	4		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T120	11		T130	6		T140	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T44	13		T45	3		T128	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T11	1		T29	15		T217	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	1		T43	6		T139	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T122	1		T50	14		T132	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T29	17		T138	9		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T12	4		T36	3		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T81	2		T202	11		T232	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T16	6		T215	2		T234	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17550	1			T2	20		T4	35		T7	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T99	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T50	11		T142	4		T221	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T28	10		T15	2		T142	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	2		T44	2		T42	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T120	11		T129	4		T136	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T122	11		T123	10		T50	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T121	6		T130	3		T219	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T6	3		T27	28		T46	42
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T45	4		T39	6		T18	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T129	12		T200	8		T189	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T191	22		T140	15		T223	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T138	11		T202	9		T221	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T120	10		T130	2		T140	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T44	9		T45	10		T138	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T29	2		T217	13		T213	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T43	8		T199	10		T283	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T122	11		T207	12		T196	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T29	18		T138	6		T125	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T12	1		T17	1		T41	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T202	10		T232	11		T259	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T16	1		T215	18		T234	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T99	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T34	1		T194	3		T276	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T224	7		T278	9		T279	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T98	7		T145	13		T187	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T50	1		T210	1		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T28	11		T15	7		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T13	7		T44	4		T50	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T28	2		T30	1		T120	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T1	1		T122	1		T133	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T121	1		T129	3		T130	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	6		T123	3		T33	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T8	1		T39	6		T81	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1337	1			T3	27		T5	21		T6	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T4	3		T8	1		T45	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T44	13		T138	14		T139	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T122	1		T120	11		T191	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T128	6		T80	1		T40	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T11	1		T29	15		T130	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T1	1		T43	6		T45	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T122	1		T50	14		T132	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	403	1			T29	17		T138	9		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T12	4		T36	3		T124	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17550	1			T2	20		T4	35		T7	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T276	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T280	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T98	7		T145	18		T281	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T50	11		T221	12		T136	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T28	10		T15	2		T142	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T13	2		T44	2		T50	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T120	11		T136	7		T213	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T122	11		T162	12		T135	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T121	6		T129	4		T130	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T123	10		T208	14		T211	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T39	6		T18	5		T216	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1316	1			T6	3		T27	28		T46	42
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T45	4		T140	15		T223	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T44	9		T138	11		T200	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T120	10		T191	22		T140	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T40	1		T135	16		T284	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T29	2		T130	2		T217	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T43	8		T45	10		T138	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T122	11		T207	12		T196	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	393	1			T29	18		T138	6		T125	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T12	1		T16	1		T17	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

auto[0]

4265

1

T6

3

T12

1

T13

2