Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26606

1

T1

2

T2

20

T3

27

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20721

1

T1

1

T2

20

T4

35

auto[ADC_CTRL_FILTER_COND_OUT]

5885

1

T1

1

T3

27

T4

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20541

1

T1

1

T2

20

T4

38

auto[1]

6065

1

T1

1

T3

27

T5

21

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

2

T2

20

T3

3

auto[1]

3833

1

T3

24

T4

4

T5

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	63	1			T285	1		T261	10		T271	26
values[0]	78	1			T202	26		T196	6		T286	1
values[1]	691	1			T45	13		T122	12		T123	13
values[2]	596	1			T1	1		T28	21		T36	3
values[3]	514	1			T12	5		T122	12		T129	25
values[4]	610	1			T11	6		T128	6		T120	21
values[5]	589	1			T11	1		T28	2		T30	1
values[6]	789	1			T1	1		T8	1		T29	17
values[7]	706	1			T8	1		T29	35		T121	7
values[8]	726	1			T4	3		T132	11		T133	1
values[9]	3694	1			T3	27		T5	21		T6	4
minimum	17550	1			T2	20		T4	35		T7	124

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	935	1			T28	21		T45	13		T122	12
values[1]	2799	1			T1	1		T3	27		T5	21
values[2]	581	1			T11	6		T122	12		T120	21
values[3]	547	1			T28	2		T43	14		T128	6
values[4]	704	1			T11	1		T29	17		T30	1
values[5]	731	1			T1	1		T8	1		T44	22
values[6]	723	1			T4	3		T29	35		T121	7
values[7]	807	1			T8	1		T139	4		T132	11
values[8]	1033	1			T8	1		T13	9		T44	6
values[9]	185	1			T81	8		T17	6		T219	1
minimum	17561	1			T2	20		T4	35		T7	124

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

4265

1

T6

3

T12

1

T13

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T123	11		T125	3		T191	23
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T28	11		T45	11		T122	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T12	4		T129	13		T126	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1565	1			T1	1		T3	3		T5	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	1		T35	1		T18	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T122	12		T120	11		T38	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T28	1		T128	1		T138	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T43	9		T140	16		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T29	3		T50	16		T33	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T11	1		T30	1		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	1		T120	12		T132	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T8	1		T44	10		T129	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T29	19		T121	7		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	1		T125	2		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T34	1		T223	3		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T8	1		T139	1		T132	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T44	3		T45	5		T138	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T8	1		T13	7		T50	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T219	1		T285	1		T251	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T81	1		T17	5		T251	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17448	1			T2	20		T4	33		T7	124
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T123	2		T191	10		T81	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T28	10		T45	2		T50	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T12	1		T129	12		T141	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	940	1			T3	24		T5	19		T10	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T11	5		T35	1		T18	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T120	10		T141	15		T35	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T28	1		T128	5		T138	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T43	5		T140	11		T77	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T29	14		T50	15		T33	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T130	5		T206	7		T211	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T120	11		T132	8		T191	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T44	12		T129	2		T138	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T29	16		T16	2		T81	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T4	2		T208	9		T250	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T223	2		T221	13		T196	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T139	3		T132	10		T162	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T44	3		T45	9		T138	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T13	2		T15	3		T162	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T251	4		T278	4		T287	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T81	7		T17	1		T251	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T4	2		T33	1		T16	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T285	1		T288	12		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T261	10		T271	13		T266	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T196	2		T286	1		T289	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T202	13		T290	1		T291	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T123	11		T125	3		T81	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T45	11		T122	12		T208	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T191	23		T126	1		T39	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	1		T28	11		T36	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T12	4		T129	13		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T122	12		T38	5		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	1		T128	1		T138	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T120	11		T130	3		T77	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T28	1		T50	16		T213	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T11	1		T30	1		T43	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T1	1		T29	3		T120	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T8	1		T44	10		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T29	19		T121	7		T132	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T8	1		T139	1		T125	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T134	1		T16	5		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T4	1		T132	1		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T44	3		T45	5		T138	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1908	1			T3	3		T5	2		T6	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17442	1			T2	20		T4	33		T7	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T271	13		T266	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T196	4		T289	11		T292	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T202	13		T290	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T123	2		T81	7		T250	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T45	2		T208	9		T41	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T191	10		T39	1		T19	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T28	10		T36	1		T50	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T12	1		T129	12		T132	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T141	15		T35	10		T18	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	5		T128	5		T138	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T120	10		T130	5		T77	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T28	1		T50	15		T213	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T43	5		T140	11		T203	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T29	14		T120	11		T191	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T44	12		T129	2		T138	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T29	16		T132	8		T200	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T139	3		T250	18		T293	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T16	2		T81	1		T151	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T4	2		T132	10		T294	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T44	3		T45	9		T138	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1221	1			T3	24		T5	19		T10	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	2		T33	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T123	3		T125	1		T191	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T28	11		T45	3		T122	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T12	4		T129	13		T126	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1283	1			T1	1		T3	27		T5	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T11	6		T35	2		T18	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T122	1		T120	11		T38	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T28	2		T128	6		T138	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T43	6		T140	12		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T29	15		T50	16		T33	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T11	1		T30	1		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	1		T120	12		T132	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T8	1		T44	13		T129	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T29	17		T121	1		T134	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	3		T125	1		T133	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T34	1		T223	3		T178	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T8	1		T139	4		T132	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T44	4		T45	10		T138	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T8	1		T13	7		T50	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T219	1		T285	1		T251	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T81	8		T17	5		T251	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17557	1			T2	20		T4	35		T7	124
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T123	10		T125	2		T191	22
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T28	10		T45	10		T122	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T12	1		T129	12		T39	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1222	1			T6	3		T27	28		T46	42
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T216	8		T96	8		T270	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T122	11		T120	10		T35	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T138	10		T250	3		T145	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T43	8		T140	15		T217	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T29	2		T50	15		T142	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T130	2		T206	7		T211	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T120	11		T200	8		T145	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T44	9		T129	4		T138	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T29	18		T121	6		T16	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T125	1		T208	14		T250	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T223	2		T221	12		T196	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T162	12		T219	6		T163	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T44	2		T45	4		T138	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T13	2		T50	11		T15	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T251	2		T234	13		T261	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T17	1		T251	8		T98	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T295	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T285	1		T288	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T261	1		T271	14		T266	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T196	5		T286	1		T289	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T202	14		T290	6		T291	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T123	3		T125	1		T81	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T45	3		T122	1		T208	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T191	11		T126	1		T39	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T1	1		T28	11		T36	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T12	4		T129	13		T132	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T122	1		T38	5		T141	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	6		T128	6		T138	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T120	11		T130	6		T77	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T28	2		T50	16		T213	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T11	1		T30	1		T43	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	1		T29	15		T120	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T8	1		T44	13		T122	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T29	17		T121	1		T132	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T8	1		T139	4		T125	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T134	1		T16	6		T34	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T4	3		T132	11		T133	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	344	1			T44	4		T45	10		T138	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1600	1			T3	27		T5	21		T6	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17550	1			T2	20		T4	35		T7	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T288	11		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T261	9		T271	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T196	1		T289	14		T292	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T202	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T123	10		T125	2		T216	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T45	10		T122	11		T208	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T191	22		T39	6		T19	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T28	10		T130	3		T140	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T12	1		T129	12		T142	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T122	11		T35	11		T18	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T138	10		T216	8		T250	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T120	10		T130	2		T42	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T50	15		T213	8		T283	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T43	8		T140	15		T270	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T29	2		T120	11		T142	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T44	9		T129	4		T138	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T29	18		T121	6		T200	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T125	1		T250	16		T296	25
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T16	1		T151	1		T196	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T94	12		T245	2		T297	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T44	2		T45	4		T138	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1529	1			T6	3		T13	2		T27	28

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

auto[0]

4265

1

T6

3

T12

1

T13

2