Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26606

1

T1

2

T2

20

T3

27

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23161

1

T1

1

T2

20

T3

27

auto[ADC_CTRL_FILTER_COND_OUT]

3445

1

T1

1

T29

35

T36

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20954

1

T1

2

T2

20

T4

38

auto[1]

5652

1

T3

27

T5

21

T6

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22773

1

T1

2

T2

20

T3

3

auto[1]

3833

1

T3

24

T4

4

T5

19

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	172	1			T129	25		T124	1		T196	10
values[0]	23	1			T44	22		T274	1		-	-
values[1]	725	1			T1	1		T132	11		T133	1
values[2]	743	1			T1	1		T29	35		T44	6
values[3]	643	1			T120	23		T50	43		T125	3
values[4]	657	1			T8	1		T13	9		T122	12
values[5]	2987	1			T3	27		T4	3		T5	21
values[6]	639	1			T50	14		T139	14		T34	1
values[7]	733	1			T11	6		T12	5		T28	2
values[8]	783	1			T8	1		T30	1		T121	7
values[9]	951	1			T8	1		T43	14		T45	14
minimum	17550	1			T2	20		T4	35		T7	124

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	672	1			T1	1		T132	11		T141	5
values[1]	892	1			T1	1		T29	35		T44	6
values[2]	551	1			T122	12		T139	4		T125	3
values[3]	2909	1			T3	27		T5	21		T6	4
values[4]	781	1			T4	3		T11	1		T28	21
values[5]	600	1			T12	5		T123	13		T138	22
values[6]	825	1			T11	6		T28	2		T29	17
values[7]	741	1			T8	1		T128	6		T121	7
values[8]	795	1			T8	1		T45	14		T122	1
values[9]	101	1			T43	14		T124	1		T273	18
minimum	17739	1			T2	20		T4	35		T7	124

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

4265

1

T6

3

T12

1

T13

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T132	1		T141	1		T40	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T1	1		T208	15		T39	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T1	1		T44	3		T129	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T29	19		T120	12		T140	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T122	12		T139	1		T125	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T132	1		T191	1		T140	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1653	1			T3	3		T5	2		T6	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T138	12		T126	1		T228	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T4	1		T11	1		T28	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T36	2		T50	1		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T12	4		T123	11		T178	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T138	11		T139	1		T15	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T11	1		T28	1		T29	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T141	1		T135	17		T283	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T8	1		T128	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T121	7		T122	12		T120	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T8	1		T45	5		T78	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T122	1		T129	13		T132	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T43	9		T124	1		T273	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T186	1		T271	1		T298	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17528	1			T2	20		T4	33		T7	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T133	1		T96	9		T144	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T132	10		T141	4		T40	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T208	9		T39	1		T211	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T44	3		T129	2		T50	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T29	16		T120	11		T140	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T139	3		T130	7		T250	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T132	8		T191	1		T140	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	973	1			T3	24		T5	19		T10	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T138	13		T198	8		T267	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T4	2		T28	10		T208	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T36	1		T50	13		T206	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T12	1		T123	2		T42	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T138	11		T139	13		T15	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T11	5		T28	1		T29	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T135	19		T283	12		T232	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T128	5		T139	9		T130	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T120	10		T136	7		T213	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T45	9		T35	11		T212	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T129	12		T132	13		T191	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T43	5		T273	10		T299	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T186	1		T271	10		T298	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T4	2		T44	12		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T144	2		T246	1		T177	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T124	1		T153	12		T300	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T129	13		T196	8		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T44	10		T274	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T132	1		T141	1		T40	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T1	1		T133	1		T208	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	1		T44	3		T129	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T29	19		T140	13		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T50	28		T125	3		T163	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T120	12		T132	1		T191	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T8	1		T13	7		T122	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T140	16		T228	1		T198	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1638	1			T3	3		T4	1		T5	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T36	2		T138	12		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T178	1		T42	6		T217	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T50	1		T139	1		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T11	1		T12	4		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T138	11		T15	6		T33	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T8	1		T30	1		T130	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T121	7		T122	12		T120	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T8	1		T43	9		T45	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T122	1		T132	1		T191	23
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17442	1			T2	20		T4	33		T7	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T300	2		T278	4		T301	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T129	12		T196	2		T271	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T44	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T132	10		T141	4		T40	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T208	9		T39	1		T211	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T44	3		T129	2		T223	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T29	16		T140	12		T162	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T50	15		T163	9		T250	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T120	11		T132	8		T191	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T13	2		T139	3		T130	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T140	11		T198	8		T267	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1013	1			T3	24		T4	2		T5	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T36	1		T138	13		T206	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T42	2		T214	16		T213	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T50	13		T139	13		T231	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T11	5		T12	1		T28	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T138	11		T15	3		T33	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T130	5		T151	8		T202	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T120	10		T135	19		T136	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T43	5		T45	9		T139	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T132	13		T191	10		T151	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T4	2		T33	1		T16	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T132	11		T141	5		T40	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T1	1		T208	10		T39	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T1	1		T44	4		T129	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T29	17		T120	12		T140	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T122	1		T139	4		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T132	9		T191	2		T140	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T3	27		T5	21		T6	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T138	14		T126	1		T228	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T4	3		T11	1		T28	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T36	3		T50	14		T134	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T12	4		T123	3		T178	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T138	12		T139	14		T15	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T11	6		T28	2		T29	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T141	1		T135	20		T283	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T8	1		T128	6		T139	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T121	1		T122	1		T120	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T8	1		T45	10		T78	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T122	1		T129	13		T132	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T43	6		T124	1		T273	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T186	2		T271	11		T298	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17589	1			T2	20		T4	35		T7	124
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T133	1		T96	1		T144	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T40	1		T142	2		T41	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T208	14		T39	6		T211	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T44	2		T129	4		T50	26
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T29	18		T120	11		T140	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T122	11		T125	2		T130	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T140	15		T189	10		T137	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T6	3		T13	2		T27	28
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T138	11		T198	9		T213	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T28	10		T208	14		T217	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T206	7		T200	8		T244	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T12	1		T123	10		T42	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T138	10		T15	2		T162	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T29	2		T17	1		T135	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T135	16		T283	10		T232	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T130	2		T142	4		T207	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T121	6		T122	11		T120	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T45	4		T35	11		T221	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T129	12		T191	22		T151	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T43	8		T273	7		T153	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T298	7		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T44	9		T153	12		T190	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T96	8		T144	2		T177	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T124	1		T153	1		T300	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T129	13		T196	3		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T44	13		T274	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T132	11		T141	5		T40	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T1	1		T133	1		T208	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	1		T44	4		T129	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T29	17		T140	13		T162	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T50	17		T125	1		T163	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T120	12		T132	9		T191	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T8	1		T13	7		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T140	12		T228	1		T198	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T3	27		T4	3		T5	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T36	3		T138	14		T126	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T178	1		T42	7		T217	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T50	14		T139	14		T34	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T11	6		T12	4		T28	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T138	12		T15	7		T33	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T8	1		T30	1		T130	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T121	1		T122	1		T120	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T8	1		T43	6		T45	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T122	1		T132	14		T191	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17550	1			T2	20		T4	35		T7	124
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T153	11		T302	8		T303	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T129	12		T196	7		T304	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T44	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T40	1		T142	2		T41	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T208	14		T39	6		T211	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T44	2		T129	4		T223	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T29	18		T140	12		T250	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T50	26		T125	2		T163	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T120	11		T221	20		T137	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	2		T122	11		T125	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T140	15		T198	9		T189	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T6	3		T27	28		T28	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T138	11		T206	7		T200	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T42	1		T217	8		T214	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T217	13		T244	11		T98	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	1		T29	2		T123	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T138	10		T15	2		T142	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T130	2		T142	4		T202	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T121	6		T122	11		T120	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T43	8		T45	4		T35	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T191	22		T151	1		T250	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22341

1

T1

2

T2

20

T3

27

auto[1]

auto[0]

4265

1

T6

3

T12

1

T13

2