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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 99.07 96.67 100.00 100.00 98.83 98.33 91.19


Total test records in report: 918
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T793 /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.628068404 Apr 04 01:16:32 PM PDT 24 Apr 04 01:25:05 PM PDT 24 481017221850 ps
T794 /workspace/coverage/default/22.adc_ctrl_fsm_reset.3686133638 Apr 04 01:15:42 PM PDT 24 Apr 04 01:24:42 PM PDT 24 107353897901 ps
T99 /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3436964578 Apr 04 01:19:58 PM PDT 24 Apr 04 01:20:56 PM PDT 24 174644251864 ps
T74 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3931573713 Apr 04 02:56:50 PM PDT 24 Apr 04 02:56:53 PM PDT 24 448121100 ps
T795 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2688157825 Apr 04 02:56:57 PM PDT 24 Apr 04 02:56:58 PM PDT 24 413899191 ps
T796 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2240996738 Apr 04 02:57:03 PM PDT 24 Apr 04 02:57:05 PM PDT 24 514540861 ps
T797 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3611395976 Apr 04 02:57:04 PM PDT 24 Apr 04 02:57:06 PM PDT 24 481121855 ps
T75 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2761551133 Apr 04 02:56:45 PM PDT 24 Apr 04 02:56:46 PM PDT 24 582161110 ps
T53 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2069657884 Apr 04 02:56:52 PM PDT 24 Apr 04 02:56:56 PM PDT 24 2283383370 ps
T798 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.103924535 Apr 04 02:57:11 PM PDT 24 Apr 04 02:57:12 PM PDT 24 468562286 ps
T56 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1628566446 Apr 04 02:57:17 PM PDT 24 Apr 04 02:57:29 PM PDT 24 4170106532 ps
T100 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3963459049 Apr 04 02:57:03 PM PDT 24 Apr 04 02:57:04 PM PDT 24 433261070 ps
T119 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.296360853 Apr 04 02:56:34 PM PDT 24 Apr 04 02:56:36 PM PDT 24 568368340 ps
T59 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1012444929 Apr 04 02:57:21 PM PDT 24 Apr 04 02:57:25 PM PDT 24 1007243320 ps
T60 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.93342807 Apr 04 02:56:59 PM PDT 24 Apr 04 02:57:02 PM PDT 24 425818550 ps
T65 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1834024586 Apr 04 02:56:51 PM PDT 24 Apr 04 02:56:53 PM PDT 24 603428813 ps
T799 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3984468820 Apr 04 02:56:50 PM PDT 24 Apr 04 02:56:52 PM PDT 24 492075282 ps
T69 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.512732513 Apr 04 02:56:50 PM PDT 24 Apr 04 02:56:52 PM PDT 24 509612456 ps
T800 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1171309332 Apr 04 02:57:04 PM PDT 24 Apr 04 02:57:05 PM PDT 24 436157838 ps
T801 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3464669449 Apr 04 02:57:02 PM PDT 24 Apr 04 02:57:04 PM PDT 24 429829903 ps
T54 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1441125957 Apr 04 02:56:37 PM PDT 24 Apr 04 02:56:39 PM PDT 24 2488264103 ps
T57 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.207141563 Apr 04 02:57:17 PM PDT 24 Apr 04 02:57:29 PM PDT 24 4346384390 ps
T101 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2917407677 Apr 04 02:57:04 PM PDT 24 Apr 04 02:57:05 PM PDT 24 579525194 ps
T76 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1500411570 Apr 04 02:57:07 PM PDT 24 Apr 04 02:57:09 PM PDT 24 575307086 ps
T55 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1752634041 Apr 04 02:56:59 PM PDT 24 Apr 04 02:57:07 PM PDT 24 5017760593 ps
T102 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3030962317 Apr 04 02:56:51 PM PDT 24 Apr 04 02:57:32 PM PDT 24 8996496273 ps
T114 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3252947991 Apr 04 02:57:03 PM PDT 24 Apr 04 02:57:05 PM PDT 24 331489987 ps
T58 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3800902660 Apr 04 02:56:53 PM PDT 24 Apr 04 02:57:01 PM PDT 24 4371809139 ps
T61 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.186001189 Apr 04 02:57:02 PM PDT 24 Apr 04 02:57:24 PM PDT 24 8477867056 ps
T802 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3591335137 Apr 04 02:57:05 PM PDT 24 Apr 04 02:57:07 PM PDT 24 488453971 ps
T803 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.944837529 Apr 04 02:57:03 PM PDT 24 Apr 04 02:57:04 PM PDT 24 581215908 ps
T804 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3463755450 Apr 04 02:57:08 PM PDT 24 Apr 04 02:57:09 PM PDT 24 396075139 ps
T115 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3309811024 Apr 04 02:56:45 PM PDT 24 Apr 04 02:56:46 PM PDT 24 512404152 ps
T116 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.4064064808 Apr 04 02:56:48 PM PDT 24 Apr 04 02:56:49 PM PDT 24 446150791 ps
T117 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.226725551 Apr 04 02:56:52 PM PDT 24 Apr 04 02:56:55 PM PDT 24 4110096084 ps
T86 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1092360238 Apr 04 02:56:58 PM PDT 24 Apr 04 02:57:06 PM PDT 24 8889111367 ps
T89 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3249232391 Apr 04 02:56:53 PM PDT 24 Apr 04 02:56:54 PM PDT 24 373995178 ps
T118 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.778613858 Apr 04 02:56:54 PM PDT 24 Apr 04 02:56:57 PM PDT 24 4177873920 ps
T66 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2840316527 Apr 04 02:57:02 PM PDT 24 Apr 04 02:57:05 PM PDT 24 436364114 ps
T805 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2541699273 Apr 04 02:56:58 PM PDT 24 Apr 04 02:57:00 PM PDT 24 801533450 ps
T68 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.983341920 Apr 04 02:57:03 PM PDT 24 Apr 04 02:57:06 PM PDT 24 628558319 ps
T103 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.33245946 Apr 04 02:56:48 PM PDT 24 Apr 04 02:56:50 PM PDT 24 442953952 ps
T806 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1500785207 Apr 04 02:57:04 PM PDT 24 Apr 04 02:57:05 PM PDT 24 328056260 ps
T807 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1188457754 Apr 04 02:56:55 PM PDT 24 Apr 04 02:57:06 PM PDT 24 4646232209 ps
T808 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1689884020 Apr 04 02:57:06 PM PDT 24 Apr 04 02:57:07 PM PDT 24 467591384 ps
T809 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.958064085 Apr 04 02:56:36 PM PDT 24 Apr 04 02:58:05 PM PDT 24 26019453949 ps
T104 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1989116798 Apr 04 02:56:53 PM PDT 24 Apr 04 02:56:59 PM PDT 24 1020216140 ps
T810 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.4047271589 Apr 04 02:57:01 PM PDT 24 Apr 04 02:57:02 PM PDT 24 550802206 ps
T811 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.893909083 Apr 04 02:57:03 PM PDT 24 Apr 04 02:57:05 PM PDT 24 424773747 ps
T812 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.117201565 Apr 04 02:56:58 PM PDT 24 Apr 04 02:57:00 PM PDT 24 419146704 ps
T813 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.4006248503 Apr 04 02:57:02 PM PDT 24 Apr 04 02:57:20 PM PDT 24 4556342386 ps
T814 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1553176968 Apr 04 02:57:28 PM PDT 24 Apr 04 02:57:30 PM PDT 24 457250505 ps
T815 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2576807294 Apr 04 02:57:00 PM PDT 24 Apr 04 02:57:01 PM PDT 24 481066340 ps
T816 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2867415050 Apr 04 02:56:48 PM PDT 24 Apr 04 02:57:01 PM PDT 24 4914345909 ps
T817 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3283736064 Apr 04 02:56:42 PM PDT 24 Apr 04 02:57:50 PM PDT 24 26338410523 ps
T105 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.763358777 Apr 04 02:57:01 PM PDT 24 Apr 04 02:57:02 PM PDT 24 363178817 ps
T818 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.4085248068 Apr 04 02:56:59 PM PDT 24 Apr 04 02:57:01 PM PDT 24 517981899 ps
T819 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3675872885 Apr 04 02:57:11 PM PDT 24 Apr 04 02:57:12 PM PDT 24 474254134 ps
T62 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2725624992 Apr 04 02:57:02 PM PDT 24 Apr 04 02:57:25 PM PDT 24 8421481040 ps
T820 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.813243234 Apr 04 02:56:57 PM PDT 24 Apr 04 02:56:59 PM PDT 24 612163870 ps
T821 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3099885174 Apr 04 02:56:54 PM PDT 24 Apr 04 02:57:03 PM PDT 24 2592740857 ps
T822 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.4284119849 Apr 04 02:57:01 PM PDT 24 Apr 04 02:57:03 PM PDT 24 535238805 ps
T823 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.920046541 Apr 04 02:56:57 PM PDT 24 Apr 04 02:56:58 PM PDT 24 444923903 ps
T824 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3357010125 Apr 04 02:57:16 PM PDT 24 Apr 04 02:57:18 PM PDT 24 450923056 ps
T825 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2813166689 Apr 04 02:57:04 PM PDT 24 Apr 04 02:57:05 PM PDT 24 500718571 ps
T826 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2292375476 Apr 04 02:56:59 PM PDT 24 Apr 04 02:57:08 PM PDT 24 2437243669 ps
T827 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3202208357 Apr 04 02:57:01 PM PDT 24 Apr 04 02:57:02 PM PDT 24 560141434 ps
T828 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.105313077 Apr 04 02:57:12 PM PDT 24 Apr 04 02:57:13 PM PDT 24 536977938 ps
T829 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.432645921 Apr 04 02:56:39 PM PDT 24 Apr 04 02:56:40 PM PDT 24 406100304 ps
T830 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2583678318 Apr 04 02:56:59 PM PDT 24 Apr 04 02:57:01 PM PDT 24 490400414 ps
T831 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1767316971 Apr 04 02:56:56 PM PDT 24 Apr 04 02:56:58 PM PDT 24 566450880 ps
T832 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.542280477 Apr 04 02:57:12 PM PDT 24 Apr 04 02:57:23 PM PDT 24 4427225892 ps
T833 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1812531732 Apr 04 02:56:36 PM PDT 24 Apr 04 02:56:37 PM PDT 24 320463183 ps
T834 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2460508915 Apr 04 02:57:03 PM PDT 24 Apr 04 02:57:09 PM PDT 24 2504816350 ps
T835 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.4082413122 Apr 04 02:56:58 PM PDT 24 Apr 04 02:57:01 PM PDT 24 2214557032 ps
T836 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2672865571 Apr 04 02:57:02 PM PDT 24 Apr 04 02:57:03 PM PDT 24 319989446 ps
T837 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3731778926 Apr 04 02:57:00 PM PDT 24 Apr 04 02:57:04 PM PDT 24 4543738256 ps
T70 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2369634700 Apr 04 02:57:03 PM PDT 24 Apr 04 02:57:15 PM PDT 24 8073099184 ps
T838 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2369522791 Apr 04 02:56:59 PM PDT 24 Apr 04 02:57:01 PM PDT 24 434352137 ps
T839 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.191239649 Apr 04 02:56:35 PM PDT 24 Apr 04 02:56:38 PM PDT 24 424763299 ps
T106 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3443768434 Apr 04 02:56:49 PM PDT 24 Apr 04 02:56:51 PM PDT 24 1293736832 ps
T840 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.697790056 Apr 04 02:56:50 PM PDT 24 Apr 04 02:56:52 PM PDT 24 446148983 ps
T841 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.280582776 Apr 04 02:56:57 PM PDT 24 Apr 04 02:56:59 PM PDT 24 788342148 ps
T842 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.4187600791 Apr 04 02:56:53 PM PDT 24 Apr 04 02:56:56 PM PDT 24 925240633 ps
T843 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.862162445 Apr 04 02:56:53 PM PDT 24 Apr 04 02:57:01 PM PDT 24 8516109064 ps
T844 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.4014413610 Apr 04 02:56:53 PM PDT 24 Apr 04 02:57:20 PM PDT 24 8394397481 ps
T845 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2389202717 Apr 04 02:56:53 PM PDT 24 Apr 04 02:56:54 PM PDT 24 491404378 ps
T846 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.783506601 Apr 04 02:57:04 PM PDT 24 Apr 04 02:57:05 PM PDT 24 484163867 ps
T847 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2897078103 Apr 04 02:56:58 PM PDT 24 Apr 04 02:56:59 PM PDT 24 464570738 ps
T848 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1070620803 Apr 04 02:57:04 PM PDT 24 Apr 04 02:57:05 PM PDT 24 493194725 ps
T849 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2632538304 Apr 04 02:56:54 PM PDT 24 Apr 04 02:56:58 PM PDT 24 469314069 ps
T850 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.4043746609 Apr 04 02:57:09 PM PDT 24 Apr 04 02:57:10 PM PDT 24 341515224 ps
T851 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.446859981 Apr 04 02:57:04 PM PDT 24 Apr 04 02:57:05 PM PDT 24 470255626 ps
T852 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1944117678 Apr 04 02:57:02 PM PDT 24 Apr 04 02:57:05 PM PDT 24 537352370 ps
T853 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1435544669 Apr 04 02:57:03 PM PDT 24 Apr 04 02:57:09 PM PDT 24 501797393 ps
T854 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.363298839 Apr 04 02:56:52 PM PDT 24 Apr 04 02:56:56 PM PDT 24 593935442 ps
T855 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1314558481 Apr 04 02:56:57 PM PDT 24 Apr 04 02:57:10 PM PDT 24 4506269229 ps
T856 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1221496375 Apr 04 02:57:08 PM PDT 24 Apr 04 02:57:10 PM PDT 24 505101590 ps
T857 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.392467505 Apr 04 02:57:25 PM PDT 24 Apr 04 02:57:26 PM PDT 24 442573122 ps
T107 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.8916644 Apr 04 02:56:46 PM PDT 24 Apr 04 02:56:48 PM PDT 24 363855359 ps
T858 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.127393108 Apr 04 02:57:12 PM PDT 24 Apr 04 02:57:16 PM PDT 24 4445481062 ps
T859 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2957391103 Apr 04 02:56:49 PM PDT 24 Apr 04 02:56:51 PM PDT 24 522586006 ps
T108 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3920022097 Apr 04 02:56:47 PM PDT 24 Apr 04 02:56:49 PM PDT 24 641958028 ps
T860 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.418919445 Apr 04 02:56:56 PM PDT 24 Apr 04 02:56:58 PM PDT 24 613138120 ps
T861 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3638148658 Apr 04 02:57:02 PM PDT 24 Apr 04 02:57:04 PM PDT 24 393895210 ps
T862 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3073538768 Apr 04 02:56:55 PM PDT 24 Apr 04 02:57:01 PM PDT 24 2688709372 ps
T863 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.464104739 Apr 04 02:57:14 PM PDT 24 Apr 04 02:57:15 PM PDT 24 475322435 ps
T864 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2027486385 Apr 04 02:56:55 PM PDT 24 Apr 04 02:56:57 PM PDT 24 508057148 ps
T865 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.619407063 Apr 04 02:57:06 PM PDT 24 Apr 04 02:57:08 PM PDT 24 352554429 ps
T866 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.4112642821 Apr 04 02:57:02 PM PDT 24 Apr 04 02:57:03 PM PDT 24 727064713 ps
T867 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1739088564 Apr 04 02:57:04 PM PDT 24 Apr 04 02:57:05 PM PDT 24 541481029 ps
T868 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1328598801 Apr 04 02:56:55 PM PDT 24 Apr 04 02:57:05 PM PDT 24 4163604901 ps
T109 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1791442111 Apr 04 02:57:25 PM PDT 24 Apr 04 02:57:26 PM PDT 24 461588530 ps
T869 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1430482911 Apr 04 02:57:06 PM PDT 24 Apr 04 02:57:08 PM PDT 24 392444824 ps
T870 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3048231628 Apr 04 02:56:57 PM PDT 24 Apr 04 02:57:00 PM PDT 24 319342971 ps
T871 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1993817196 Apr 04 02:56:46 PM PDT 24 Apr 04 02:56:50 PM PDT 24 4255549028 ps
T872 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2429594204 Apr 04 02:57:18 PM PDT 24 Apr 04 02:57:20 PM PDT 24 401944633 ps
T873 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1752288647 Apr 04 02:56:42 PM PDT 24 Apr 04 02:56:49 PM PDT 24 677505999 ps
T874 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1049040963 Apr 04 02:56:59 PM PDT 24 Apr 04 02:57:00 PM PDT 24 339996123 ps
T875 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2275988411 Apr 04 02:57:02 PM PDT 24 Apr 04 02:57:03 PM PDT 24 540583663 ps
T876 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1162299875 Apr 04 02:56:57 PM PDT 24 Apr 04 02:56:58 PM PDT 24 390381629 ps
T877 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3099883635 Apr 04 02:56:51 PM PDT 24 Apr 04 02:57:12 PM PDT 24 8355688339 ps
T878 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1551630499 Apr 04 02:57:00 PM PDT 24 Apr 04 02:57:08 PM PDT 24 8757577883 ps
T879 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.324747593 Apr 04 02:57:01 PM PDT 24 Apr 04 02:57:04 PM PDT 24 2065773061 ps
T880 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2638869924 Apr 04 02:57:00 PM PDT 24 Apr 04 02:57:01 PM PDT 24 496475443 ps
T881 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2280446296 Apr 04 02:57:00 PM PDT 24 Apr 04 02:57:02 PM PDT 24 372215198 ps
T882 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3958693336 Apr 04 02:57:03 PM PDT 24 Apr 04 02:57:05 PM PDT 24 607412836 ps
T883 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.190025829 Apr 04 02:57:00 PM PDT 24 Apr 04 02:57:02 PM PDT 24 512877905 ps
T884 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2321540417 Apr 04 02:56:39 PM PDT 24 Apr 04 02:56:41 PM PDT 24 2609554189 ps
T112 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2481568303 Apr 04 02:56:36 PM PDT 24 Apr 04 02:56:38 PM PDT 24 724106775 ps
T885 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4006027417 Apr 04 02:57:00 PM PDT 24 Apr 04 02:57:01 PM PDT 24 380378142 ps
T110 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3351824946 Apr 04 02:56:49 PM PDT 24 Apr 04 02:56:52 PM PDT 24 1130981275 ps
T886 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3405192743 Apr 04 02:57:04 PM PDT 24 Apr 04 02:57:05 PM PDT 24 468423097 ps
T887 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1682583633 Apr 04 02:56:46 PM PDT 24 Apr 04 02:56:58 PM PDT 24 4268365338 ps
T888 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3802922313 Apr 04 02:56:51 PM PDT 24 Apr 04 02:56:55 PM PDT 24 2276376182 ps
T889 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2017590846 Apr 04 02:56:52 PM PDT 24 Apr 04 02:56:56 PM PDT 24 4551634139 ps
T890 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2187292097 Apr 04 02:56:50 PM PDT 24 Apr 04 02:56:52 PM PDT 24 677986928 ps
T113 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2449282273 Apr 04 02:56:56 PM PDT 24 Apr 04 02:56:59 PM PDT 24 543762946 ps
T891 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1265803213 Apr 04 02:56:51 PM PDT 24 Apr 04 02:56:52 PM PDT 24 336749078 ps
T892 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2610089002 Apr 04 02:57:00 PM PDT 24 Apr 04 02:57:02 PM PDT 24 402995248 ps
T893 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3770338275 Apr 04 02:57:07 PM PDT 24 Apr 04 02:57:10 PM PDT 24 537635880 ps
T894 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2226379455 Apr 04 02:57:00 PM PDT 24 Apr 04 02:57:57 PM PDT 24 25879162223 ps
T895 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2968378212 Apr 04 02:56:40 PM PDT 24 Apr 04 02:56:47 PM PDT 24 4349433866 ps
T111 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1596131848 Apr 04 02:56:50 PM PDT 24 Apr 04 02:56:51 PM PDT 24 372904700 ps
T896 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3337983977 Apr 04 02:56:53 PM PDT 24 Apr 04 02:56:54 PM PDT 24 540351126 ps
T897 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2200559017 Apr 04 02:56:44 PM PDT 24 Apr 04 02:56:48 PM PDT 24 4586957277 ps
T898 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.515745274 Apr 04 02:57:00 PM PDT 24 Apr 04 02:57:07 PM PDT 24 4069092452 ps
T899 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2231664498 Apr 04 02:57:02 PM PDT 24 Apr 04 02:57:03 PM PDT 24 310860467 ps
T900 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.4115248165 Apr 04 02:56:46 PM PDT 24 Apr 04 02:56:49 PM PDT 24 677268996 ps
T330 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.4149752781 Apr 04 02:57:04 PM PDT 24 Apr 04 02:57:10 PM PDT 24 8857623402 ps
T901 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1638221311 Apr 04 02:56:59 PM PDT 24 Apr 04 02:57:01 PM PDT 24 508770720 ps
T902 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2976435792 Apr 04 02:57:03 PM PDT 24 Apr 04 02:57:04 PM PDT 24 496888333 ps
T903 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.4286310774 Apr 04 02:56:55 PM PDT 24 Apr 04 02:56:57 PM PDT 24 699395841 ps
T904 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.12180565 Apr 04 02:56:57 PM PDT 24 Apr 04 02:56:59 PM PDT 24 783953105 ps
T905 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.824394135 Apr 04 02:57:06 PM PDT 24 Apr 04 02:57:07 PM PDT 24 304955207 ps
T906 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2770842420 Apr 04 02:56:57 PM PDT 24 Apr 04 02:57:00 PM PDT 24 819015391 ps
T907 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1165803041 Apr 04 02:57:17 PM PDT 24 Apr 04 02:57:20 PM PDT 24 636823824 ps
T908 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3734350574 Apr 04 02:56:45 PM PDT 24 Apr 04 02:56:48 PM PDT 24 578016824 ps
T909 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.253576013 Apr 04 02:57:10 PM PDT 24 Apr 04 02:57:11 PM PDT 24 320610476 ps
T910 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3777746071 Apr 04 02:57:00 PM PDT 24 Apr 04 02:57:02 PM PDT 24 427980279 ps
T911 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3332012989 Apr 04 02:57:04 PM PDT 24 Apr 04 02:57:06 PM PDT 24 382862382 ps
T912 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2424287640 Apr 04 02:56:46 PM PDT 24 Apr 04 02:56:48 PM PDT 24 517104324 ps
T913 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2756736339 Apr 04 02:56:57 PM PDT 24 Apr 04 02:56:59 PM PDT 24 373128457 ps
T914 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2825803118 Apr 04 02:56:53 PM PDT 24 Apr 04 02:56:56 PM PDT 24 395503301 ps
T915 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1197034440 Apr 04 02:57:13 PM PDT 24 Apr 04 02:57:14 PM PDT 24 377095297 ps
T916 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2653239615 Apr 04 02:57:27 PM PDT 24 Apr 04 02:57:29 PM PDT 24 2657348854 ps
T917 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2453596102 Apr 04 02:56:57 PM PDT 24 Apr 04 02:56:59 PM PDT 24 446066827 ps
T918 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4272253830 Apr 04 02:57:01 PM PDT 24 Apr 04 02:57:02 PM PDT 24 868203045 ps

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.5613060
Short name T4
Test name
Test status
Simulation time 217377915983 ps
CPU time 246.81 seconds
Started Apr 04 01:17:26 PM PDT 24
Finished Apr 04 01:21:33 PM PDT 24
Peak memory 202284 kb
Host smart-695a2b23-df01-4e5c-8ae4-7365084f9e3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5613060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all.5613060
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.2317567610
Short name T12
Test name
Test status
Simulation time 277489403889 ps
CPU time 262.89 seconds
Started Apr 04 01:10:43 PM PDT 24
Finished Apr 04 01:15:06 PM PDT 24
Peak memory 210904 kb
Host smart-cb79fb6e-6170-414f-93db-fd3e2e83dfd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317567610 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.2317567610
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3472343527
Short name T18
Test name
Test status
Simulation time 173159313200 ps
CPU time 448.12 seconds
Started Apr 04 01:16:52 PM PDT 24
Finished Apr 04 01:24:20 PM PDT 24
Peak memory 211152 kb
Host smart-2fa2a2a5-f8c7-4361-98b7-aabcc0217203
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472343527 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3472343527
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3038590942
Short name T8
Test name
Test status
Simulation time 485434758484 ps
CPU time 1148.62 seconds
Started Apr 04 01:18:30 PM PDT 24
Finished Apr 04 01:37:39 PM PDT 24
Peak memory 202160 kb
Host smart-ab5ef0ae-c6f6-464e-83c4-a599d5dd4547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038590942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3038590942
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2247519495
Short name T50
Test name
Test status
Simulation time 622540148151 ps
CPU time 691.71 seconds
Started Apr 04 01:11:13 PM PDT 24
Finished Apr 04 01:22:45 PM PDT 24
Peak memory 202580 kb
Host smart-6b61bd1e-5b88-45ca-a7f6-842e7987f95b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247519495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2247519495
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1608203499
Short name T242
Test name
Test status
Simulation time 477451307096 ps
CPU time 1064.65 seconds
Started Apr 04 01:23:27 PM PDT 24
Finished Apr 04 01:41:12 PM PDT 24
Peak memory 213552 kb
Host smart-fa386fa3-6993-4890-8323-dab9d3d268dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608203499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1608203499
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1438379658
Short name T250
Test name
Test status
Simulation time 577242276667 ps
CPU time 496.72 seconds
Started Apr 04 01:15:26 PM PDT 24
Finished Apr 04 01:23:43 PM PDT 24
Peak memory 202336 kb
Host smart-50edc245-9def-46af-be2f-b4de2ef0ecd1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438379658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1438379658
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.4132410866
Short name T136
Test name
Test status
Simulation time 720453067026 ps
CPU time 451.5 seconds
Started Apr 04 01:08:23 PM PDT 24
Finished Apr 04 01:15:54 PM PDT 24
Peak memory 202316 kb
Host smart-4fe1adf4-25ff-41d7-b249-a2e884e09507
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132410866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
4132410866
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.3278694805
Short name T130
Test name
Test status
Simulation time 328820549545 ps
CPU time 309.74 seconds
Started Apr 04 01:06:51 PM PDT 24
Finished Apr 04 01:12:02 PM PDT 24
Peak memory 202236 kb
Host smart-f9e600d9-1937-478c-ad78-f31540109732
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278694805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.3278694805
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.686910280
Short name T196
Test name
Test status
Simulation time 546833706328 ps
CPU time 1153.5 seconds
Started Apr 04 01:13:36 PM PDT 24
Finished Apr 04 01:32:50 PM PDT 24
Peak memory 202216 kb
Host smart-819fe5d4-182f-426c-a39d-6d8e6134603c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686910280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gati
ng.686910280
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.3073126133
Short name T45
Test name
Test status
Simulation time 324973025355 ps
CPU time 173.89 seconds
Started Apr 04 01:20:36 PM PDT 24
Finished Apr 04 01:23:30 PM PDT 24
Peak memory 202176 kb
Host smart-c2d5fa83-91ff-4605-bae3-9f0b26c7a5dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073126133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.3073126133
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1012444929
Short name T59
Test name
Test status
Simulation time 1007243320 ps
CPU time 3.32 seconds
Started Apr 04 02:57:21 PM PDT 24
Finished Apr 04 02:57:25 PM PDT 24
Peak memory 210640 kb
Host smart-308deb4c-3f7e-4480-b9fe-63c52bb05f06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012444929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1012444929
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2800976426
Short name T140
Test name
Test status
Simulation time 328318610525 ps
CPU time 95.61 seconds
Started Apr 04 01:07:52 PM PDT 24
Finished Apr 04 01:09:27 PM PDT 24
Peak memory 202316 kb
Host smart-f6da9be2-1b50-43dc-a14b-3c49174da8cc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800976426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2800976426
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2666710926
Short name T14
Test name
Test status
Simulation time 4642533163 ps
CPU time 3.26 seconds
Started Apr 04 01:07:05 PM PDT 24
Finished Apr 04 01:07:09 PM PDT 24
Peak memory 217716 kb
Host smart-3f639921-a178-4a9a-8711-37c917a7f059
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666710926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2666710926
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.36302255
Short name T202
Test name
Test status
Simulation time 552192288859 ps
CPU time 306.02 seconds
Started Apr 04 01:06:35 PM PDT 24
Finished Apr 04 01:11:42 PM PDT 24
Peak memory 202312 kb
Host smart-c664b82d-a0e4-47fd-9590-02bae55bd800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36302255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.36302255
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3003754544
Short name T251
Test name
Test status
Simulation time 548233129412 ps
CPU time 690.57 seconds
Started Apr 04 01:07:07 PM PDT 24
Finished Apr 04 01:18:37 PM PDT 24
Peak memory 202252 kb
Host smart-3b4490d9-4a06-480a-ae2e-563307fe0fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003754544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3003754544
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1107325863
Short name T44
Test name
Test status
Simulation time 461699041753 ps
CPU time 1058.96 seconds
Started Apr 04 01:18:34 PM PDT 24
Finished Apr 04 01:36:14 PM PDT 24
Peak memory 201892 kb
Host smart-44a62877-4781-41ad-a519-92159782d82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107325863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1107325863
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.1867829594
Short name T5
Test name
Test status
Simulation time 334828901028 ps
CPU time 724.3 seconds
Started Apr 04 01:17:24 PM PDT 24
Finished Apr 04 01:29:30 PM PDT 24
Peak memory 202112 kb
Host smart-eff9b024-fec4-4e2b-9304-e639942f5d4f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867829594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.1867829594
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3030962317
Short name T102
Test name
Test status
Simulation time 8996496273 ps
CPU time 40.46 seconds
Started Apr 04 02:56:51 PM PDT 24
Finished Apr 04 02:57:32 PM PDT 24
Peak memory 201392 kb
Host smart-143f9b02-8e9b-4d01-baca-4f3e9a1eb7b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030962317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.3030962317
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3701801603
Short name T142
Test name
Test status
Simulation time 624128265820 ps
CPU time 750.6 seconds
Started Apr 04 01:19:03 PM PDT 24
Finished Apr 04 01:31:33 PM PDT 24
Peak memory 202256 kb
Host smart-1ee1f155-3f2f-4d4e-8d0a-8c5f7e6ba8ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701801603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3701801603
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3354447322
Short name T191
Test name
Test status
Simulation time 363296814801 ps
CPU time 435.3 seconds
Started Apr 04 01:17:37 PM PDT 24
Finished Apr 04 01:24:53 PM PDT 24
Peak memory 202256 kb
Host smart-13d871af-1703-4b12-941d-5148b0396b6d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354447322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3354447322
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.281480040
Short name T98
Test name
Test status
Simulation time 504149916040 ps
CPU time 288.28 seconds
Started Apr 04 01:09:40 PM PDT 24
Finished Apr 04 01:14:28 PM PDT 24
Peak memory 202264 kb
Host smart-d7c83edd-906a-4f79-b25a-88f25a40dbdd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281480040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.281480040
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1627003282
Short name T162
Test name
Test status
Simulation time 342837819335 ps
CPU time 115.8 seconds
Started Apr 04 01:22:41 PM PDT 24
Finished Apr 04 01:24:37 PM PDT 24
Peak memory 202220 kb
Host smart-890246b8-ada7-46f6-85b2-d07097e88159
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627003282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1627003282
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.552135378
Short name T230
Test name
Test status
Simulation time 492192972111 ps
CPU time 321.1 seconds
Started Apr 04 01:18:08 PM PDT 24
Finished Apr 04 01:23:29 PM PDT 24
Peak memory 202252 kb
Host smart-5e411e3a-1ddb-48a5-9475-a25b83710fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552135378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.552135378
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.4224335657
Short name T20
Test name
Test status
Simulation time 118258334162 ps
CPU time 84.81 seconds
Started Apr 04 01:17:25 PM PDT 24
Finished Apr 04 01:18:51 PM PDT 24
Peak memory 210840 kb
Host smart-f00d68a3-8b38-47f4-994e-aff8510a5035
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224335657 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.4224335657
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.726794572
Short name T297
Test name
Test status
Simulation time 515140118632 ps
CPU time 319.61 seconds
Started Apr 04 01:11:26 PM PDT 24
Finished Apr 04 01:16:45 PM PDT 24
Peak memory 202148 kb
Host smart-566b2b1b-31f2-4221-9566-4dca9bb51caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726794572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.726794572
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3892919875
Short name T138
Test name
Test status
Simulation time 587576911465 ps
CPU time 708.53 seconds
Started Apr 04 01:08:40 PM PDT 24
Finished Apr 04 01:20:29 PM PDT 24
Peak memory 202256 kb
Host smart-12ab1781-fc28-4c26-b2f1-bf9bea2ec3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892919875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3892919875
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.836444152
Short name T232
Test name
Test status
Simulation time 329373716093 ps
CPU time 160.07 seconds
Started Apr 04 01:09:07 PM PDT 24
Finished Apr 04 01:11:48 PM PDT 24
Peak memory 202368 kb
Host smart-fe309407-009d-4e84-a4c5-0e4ae0f16d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836444152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.836444152
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.2369634700
Short name T70
Test name
Test status
Simulation time 8073099184 ps
CPU time 11.48 seconds
Started Apr 04 02:57:03 PM PDT 24
Finished Apr 04 02:57:15 PM PDT 24
Peak memory 201452 kb
Host smart-eaa85053-505b-497c-a062-ed38b428dbcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369634700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.2369634700
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2210229539
Short name T376
Test name
Test status
Simulation time 530486968 ps
CPU time 1.72 seconds
Started Apr 04 01:11:34 PM PDT 24
Finished Apr 04 01:11:36 PM PDT 24
Peak memory 201936 kb
Host smart-98be8c63-6045-4867-9f90-5990b2bcdc55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210229539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2210229539
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.1301113762
Short name T271
Test name
Test status
Simulation time 658555711094 ps
CPU time 389.39 seconds
Started Apr 04 01:22:30 PM PDT 24
Finished Apr 04 01:29:00 PM PDT 24
Peak memory 202260 kb
Host smart-f592b522-9635-4c6f-8c5b-3531cd248ca1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301113762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.1301113762
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.1970581821
Short name T154
Test name
Test status
Simulation time 513752025399 ps
CPU time 272.74 seconds
Started Apr 04 01:22:06 PM PDT 24
Finished Apr 04 01:26:39 PM PDT 24
Peak memory 202260 kb
Host smart-b3398947-3cc6-4a5e-88d6-9e04f62318c2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970581821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.1970581821
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1593221670
Short name T21
Test name
Test status
Simulation time 328217602472 ps
CPU time 293.7 seconds
Started Apr 04 01:14:19 PM PDT 24
Finished Apr 04 01:19:13 PM PDT 24
Peak memory 210892 kb
Host smart-797cb393-1eb0-478d-8c24-e57795bad990
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593221670 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1593221670
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2734315761
Short name T264
Test name
Test status
Simulation time 329454824405 ps
CPU time 195.88 seconds
Started Apr 04 01:18:20 PM PDT 24
Finished Apr 04 01:21:36 PM PDT 24
Peak memory 202260 kb
Host smart-10b856b8-7c48-43de-8b31-fcdf41953f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734315761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2734315761
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.2016057279
Short name T224
Test name
Test status
Simulation time 482419715805 ps
CPU time 1060.25 seconds
Started Apr 04 01:22:32 PM PDT 24
Finished Apr 04 01:40:13 PM PDT 24
Peak memory 202240 kb
Host smart-38326cc9-5437-4d8a-b4fe-ccd9f257d4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016057279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2016057279
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2157690649
Short name T46
Test name
Test status
Simulation time 618433788877 ps
CPU time 1461.11 seconds
Started Apr 04 01:17:01 PM PDT 24
Finished Apr 04 01:41:23 PM PDT 24
Peak memory 202252 kb
Host smart-55e2c1ae-42e5-4264-8c3d-a7d792d8d3c6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157690649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2157690649
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1074366498
Short name T144
Test name
Test status
Simulation time 514470412707 ps
CPU time 276.65 seconds
Started Apr 04 01:13:06 PM PDT 24
Finished Apr 04 01:17:43 PM PDT 24
Peak memory 202340 kb
Host smart-59f2c78b-ee32-4955-b402-3d73c4412319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074366498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1074366498
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1004939339
Short name T288
Test name
Test status
Simulation time 367420296717 ps
CPU time 847.79 seconds
Started Apr 04 01:16:02 PM PDT 24
Finished Apr 04 01:30:10 PM PDT 24
Peak memory 202292 kb
Host smart-a1096f66-d031-43e0-9ee2-c4798d6d255a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004939339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.1004939339
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3920588559
Short name T153
Test name
Test status
Simulation time 514648586340 ps
CPU time 283.33 seconds
Started Apr 04 01:11:15 PM PDT 24
Finished Apr 04 01:15:58 PM PDT 24
Peak memory 202112 kb
Host smart-0ea5412f-bace-42ae-8902-9b899ffc1c18
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920588559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3920588559
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.1923570038
Short name T122
Test name
Test status
Simulation time 551522761373 ps
CPU time 350.39 seconds
Started Apr 04 01:08:12 PM PDT 24
Finished Apr 04 01:14:02 PM PDT 24
Peak memory 202264 kb
Host smart-266be452-e8b2-4ceb-b89a-9be24c110b5a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923570038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.1923570038
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.3984235257
Short name T194
Test name
Test status
Simulation time 491906700827 ps
CPU time 305.69 seconds
Started Apr 04 01:10:31 PM PDT 24
Finished Apr 04 01:15:37 PM PDT 24
Peak memory 202260 kb
Host smart-7e09f0ea-006f-4c2d-9faa-2fffe0d19853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984235257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.3984235257
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2455859416
Short name T192
Test name
Test status
Simulation time 453825246286 ps
CPU time 684.85 seconds
Started Apr 04 01:07:02 PM PDT 24
Finished Apr 04 01:18:29 PM PDT 24
Peak memory 218672 kb
Host smart-4a58b565-463a-486e-9c78-2ec7fe6502df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455859416 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2455859416
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.45471592
Short name T16
Test name
Test status
Simulation time 93443480382 ps
CPU time 81.27 seconds
Started Apr 04 01:18:30 PM PDT 24
Finished Apr 04 01:19:52 PM PDT 24
Peak memory 219100 kb
Host smart-f48aea02-1b9b-4bf2-8c8f-5097693260dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45471592 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.45471592
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3309811024
Short name T115
Test name
Test status
Simulation time 512404152 ps
CPU time 1.06 seconds
Started Apr 04 02:56:45 PM PDT 24
Finished Apr 04 02:56:46 PM PDT 24
Peak memory 201204 kb
Host smart-3e7ed501-e050-47ef-ab80-f12c84d12864
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309811024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.3309811024
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.546923440
Short name T227
Test name
Test status
Simulation time 582277795293 ps
CPU time 1529.12 seconds
Started Apr 04 01:23:04 PM PDT 24
Finished Apr 04 01:48:34 PM PDT 24
Peak memory 202496 kb
Host smart-5b185ff9-767b-467f-b1b7-81454cd88b52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546923440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
546923440
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.4074175632
Short name T272
Test name
Test status
Simulation time 96300227612 ps
CPU time 83.7 seconds
Started Apr 04 01:23:12 PM PDT 24
Finished Apr 04 01:24:36 PM PDT 24
Peak memory 211144 kb
Host smart-9ea83eaf-cd19-4fa9-b7e1-8fdbf436b882
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074175632 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.4074175632
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.1819226160
Short name T219
Test name
Test status
Simulation time 369638040159 ps
CPU time 841.87 seconds
Started Apr 04 01:15:42 PM PDT 24
Finished Apr 04 01:29:44 PM PDT 24
Peak memory 202224 kb
Host smart-d06176a9-3e85-4e73-aa9b-8dcb45ab6b2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819226160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.1819226160
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.1200026879
Short name T266
Test name
Test status
Simulation time 523319609596 ps
CPU time 1236.08 seconds
Started Apr 04 01:22:19 PM PDT 24
Finished Apr 04 01:42:55 PM PDT 24
Peak memory 202256 kb
Host smart-613e1f1c-73cf-46f6-9b59-43c5abac15f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200026879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.1200026879
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.1953522764
Short name T200
Test name
Test status
Simulation time 162980639826 ps
CPU time 94.23 seconds
Started Apr 04 01:10:32 PM PDT 24
Finished Apr 04 01:12:07 PM PDT 24
Peak memory 202216 kb
Host smart-69c64102-aeb0-4fc7-9bbf-1b1f31ade8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953522764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.1953522764
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.2372051286
Short name T317
Test name
Test status
Simulation time 167066249109 ps
CPU time 194.95 seconds
Started Apr 04 01:10:50 PM PDT 24
Finished Apr 04 01:14:05 PM PDT 24
Peak memory 202256 kb
Host smart-63d9ee3a-ee58-4283-8400-954f4c61af71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372051286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2372051286
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2877472314
Short name T165
Test name
Test status
Simulation time 498563354290 ps
CPU time 185.78 seconds
Started Apr 04 01:14:59 PM PDT 24
Finished Apr 04 01:18:04 PM PDT 24
Peak memory 202288 kb
Host smart-d7d25bdd-e4cd-4ad1-a294-fe87e31422e4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877472314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2877472314
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3377896458
Short name T289
Test name
Test status
Simulation time 497114947079 ps
CPU time 1184.87 seconds
Started Apr 04 01:16:42 PM PDT 24
Finished Apr 04 01:36:27 PM PDT 24
Peak memory 202152 kb
Host smart-29d16ac3-37ab-4aae-9ebd-d2be093cc852
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377896458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3377896458
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3436964578
Short name T99
Test name
Test status
Simulation time 174644251864 ps
CPU time 58.09 seconds
Started Apr 04 01:19:58 PM PDT 24
Finished Apr 04 01:20:56 PM PDT 24
Peak memory 202316 kb
Host smart-f3cc51b9-ab65-4bdf-bfae-613a186d3e73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436964578 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.3436964578
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.3849136565
Short name T177
Test name
Test status
Simulation time 518811903144 ps
CPU time 234.68 seconds
Started Apr 04 01:22:20 PM PDT 24
Finished Apr 04 01:26:14 PM PDT 24
Peak memory 202368 kb
Host smart-4de48712-79d5-45e1-b5e8-5f4fc824b4f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849136565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.3849136565
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2405203257
Short name T42
Test name
Test status
Simulation time 86518180153 ps
CPU time 165.88 seconds
Started Apr 04 01:22:30 PM PDT 24
Finished Apr 04 01:25:16 PM PDT 24
Peak memory 210780 kb
Host smart-e2432f85-0097-4c58-8fd8-ad5b2f07c068
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405203257 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.2405203257
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.1939988009
Short name T195
Test name
Test status
Simulation time 332479860288 ps
CPU time 555.58 seconds
Started Apr 04 01:23:13 PM PDT 24
Finished Apr 04 01:32:29 PM PDT 24
Peak memory 202260 kb
Host smart-5bf4295c-7f04-4025-ba96-f92cf1599bcf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939988009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.1939988009
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.157638362
Short name T139
Test name
Test status
Simulation time 496266769564 ps
CPU time 1133.61 seconds
Started Apr 04 01:08:13 PM PDT 24
Finished Apr 04 01:27:07 PM PDT 24
Peak memory 202316 kb
Host smart-bd1a98cd-c3b4-417a-a6e3-1dc6e8c8b965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157638362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.157638362
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.94629839
Short name T35
Test name
Test status
Simulation time 521043586047 ps
CPU time 122.53 seconds
Started Apr 04 01:15:21 PM PDT 24
Finished Apr 04 01:17:24 PM PDT 24
Peak memory 202244 kb
Host smart-3bdde92b-5b97-4223-aa5c-3fa0cabcd458
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94629839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.94629839
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.629156011
Short name T299
Test name
Test status
Simulation time 496070510452 ps
CPU time 1139.76 seconds
Started Apr 04 01:07:54 PM PDT 24
Finished Apr 04 01:26:54 PM PDT 24
Peak memory 202196 kb
Host smart-13791c27-5e07-4b2c-a924-7c2a5eab57e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629156011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.629156011
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.4149752781
Short name T330
Test name
Test status
Simulation time 8857623402 ps
CPU time 6.43 seconds
Started Apr 04 02:57:04 PM PDT 24
Finished Apr 04 02:57:10 PM PDT 24
Peak memory 201488 kb
Host smart-5655dbdf-e5f1-49a5-a7cf-e11b478ee74d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149752781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.4149752781
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1068343368
Short name T121
Test name
Test status
Simulation time 188790418050 ps
CPU time 26.77 seconds
Started Apr 04 01:10:44 PM PDT 24
Finished Apr 04 01:11:11 PM PDT 24
Peak memory 202200 kb
Host smart-e5ae6ac9-84ef-4d04-95b1-3017739a6a67
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068343368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1068343368
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2130517283
Short name T253
Test name
Test status
Simulation time 487178065930 ps
CPU time 1046.11 seconds
Started Apr 04 01:14:03 PM PDT 24
Finished Apr 04 01:31:29 PM PDT 24
Peak memory 202356 kb
Host smart-0304bb43-8ead-4e88-bda6-5723dd34f400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130517283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2130517283
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.4087735405
Short name T240
Test name
Test status
Simulation time 168586615685 ps
CPU time 34.88 seconds
Started Apr 04 01:16:03 PM PDT 24
Finished Apr 04 01:16:38 PM PDT 24
Peak memory 202352 kb
Host smart-20a9423b-a763-455d-94ae-bbae6ebbd4fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087735405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.4087735405
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.816206043
Short name T332
Test name
Test status
Simulation time 373693623454 ps
CPU time 594.35 seconds
Started Apr 04 01:18:31 PM PDT 24
Finished Apr 04 01:28:25 PM PDT 24
Peak memory 210680 kb
Host smart-50eea190-4df3-4d08-9eed-10af007e0d41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816206043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all.
816206043
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.861651905
Short name T341
Test name
Test status
Simulation time 120356763712 ps
CPU time 511.75 seconds
Started Apr 04 01:21:43 PM PDT 24
Finished Apr 04 01:30:15 PM PDT 24
Peak memory 202504 kb
Host smart-abdbe9f9-d416-43f4-ac82-18c113336ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861651905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.861651905
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2522170173
Short name T249
Test name
Test status
Simulation time 167090307511 ps
CPU time 399.39 seconds
Started Apr 04 01:22:41 PM PDT 24
Finished Apr 04 01:29:21 PM PDT 24
Peak memory 202256 kb
Host smart-37e89913-b9fe-48b4-81ea-eab30c0db85a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522170173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2522170173
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.109172483
Short name T145
Test name
Test status
Simulation time 530193120979 ps
CPU time 620.99 seconds
Started Apr 04 01:06:35 PM PDT 24
Finished Apr 04 01:16:56 PM PDT 24
Peak memory 202192 kb
Host smart-6b6e53dc-2c17-4a1b-89c1-51241163bd8c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109172483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin
g.109172483
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.2088832930
Short name T338
Test name
Test status
Simulation time 444522347534 ps
CPU time 1404.68 seconds
Started Apr 04 01:10:13 PM PDT 24
Finished Apr 04 01:33:38 PM PDT 24
Peak memory 202672 kb
Host smart-d111ee5f-f636-44a4-a58d-4348d8642095
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088832930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.2088832930
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2159159055
Short name T258
Test name
Test status
Simulation time 557974576172 ps
CPU time 1245.96 seconds
Started Apr 04 01:10:50 PM PDT 24
Finished Apr 04 01:31:36 PM PDT 24
Peak memory 202248 kb
Host smart-9b53cc79-6660-414f-afca-8d9076f3de62
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159159055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2159159055
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.3838162111
Short name T349
Test name
Test status
Simulation time 134265113438 ps
CPU time 459.36 seconds
Started Apr 04 01:11:01 PM PDT 24
Finished Apr 04 01:18:40 PM PDT 24
Peak memory 202552 kb
Host smart-e33a19a2-bec9-4deb-9812-0f29712f1706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838162111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3838162111
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2351995292
Short name T339
Test name
Test status
Simulation time 107639318304 ps
CPU time 347 seconds
Started Apr 04 01:11:35 PM PDT 24
Finished Apr 04 01:17:23 PM PDT 24
Peak memory 202564 kb
Host smart-c009a130-fd60-411e-8824-4724555be830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351995292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2351995292
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2066999619
Short name T309
Test name
Test status
Simulation time 193385396425 ps
CPU time 154.57 seconds
Started Apr 04 01:11:35 PM PDT 24
Finished Apr 04 01:14:10 PM PDT 24
Peak memory 210908 kb
Host smart-d9da7179-1438-4757-bf06-dd55f41f015a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066999619 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2066999619
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.929442487
Short name T352
Test name
Test status
Simulation time 475177847636 ps
CPU time 1401.3 seconds
Started Apr 04 01:11:58 PM PDT 24
Finished Apr 04 01:35:21 PM PDT 24
Peak memory 202628 kb
Host smart-66330b6b-f3e6-4448-8550-888da5153800
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929442487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.
929442487
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.1815568284
Short name T331
Test name
Test status
Simulation time 132483727128 ps
CPU time 434.88 seconds
Started Apr 04 01:14:50 PM PDT 24
Finished Apr 04 01:22:05 PM PDT 24
Peak memory 202624 kb
Host smart-609daab8-ccf7-4c6e-b102-592d630cddc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815568284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1815568284
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.1915289744
Short name T343
Test name
Test status
Simulation time 131837696340 ps
CPU time 676.03 seconds
Started Apr 04 01:15:21 PM PDT 24
Finished Apr 04 01:26:37 PM PDT 24
Peak memory 202556 kb
Host smart-a6d4b221-12bc-49ab-abde-8cdcb140d3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915289744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1915289744
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1130551112
Short name T277
Test name
Test status
Simulation time 344581239657 ps
CPU time 828.25 seconds
Started Apr 04 01:16:03 PM PDT 24
Finished Apr 04 01:29:51 PM PDT 24
Peak memory 202256 kb
Host smart-641b1649-003b-4aab-906f-4eac143ee5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130551112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1130551112
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2868276450
Short name T345
Test name
Test status
Simulation time 87387019652 ps
CPU time 463.63 seconds
Started Apr 04 01:16:52 PM PDT 24
Finished Apr 04 01:24:36 PM PDT 24
Peak memory 202556 kb
Host smart-35143586-0be6-4ebf-b3c5-dd888e97c0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868276450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2868276450
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3050572235
Short name T33
Test name
Test status
Simulation time 166334483082 ps
CPU time 109.97 seconds
Started Apr 04 01:17:14 PM PDT 24
Finished Apr 04 01:19:04 PM PDT 24
Peak memory 202300 kb
Host smart-d51eb4fe-d649-40b5-93fd-5fb43ab23135
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050572235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3050572235
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.3954097099
Short name T269
Test name
Test status
Simulation time 631447484886 ps
CPU time 1451.36 seconds
Started Apr 04 01:17:27 PM PDT 24
Finished Apr 04 01:41:39 PM PDT 24
Peak memory 202288 kb
Host smart-409b5164-1b20-4046-a6b1-3a957a77a38c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954097099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.3954097099
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2585750540
Short name T182
Test name
Test status
Simulation time 87876431874 ps
CPU time 297.45 seconds
Started Apr 04 01:18:32 PM PDT 24
Finished Apr 04 01:23:29 PM PDT 24
Peak memory 202616 kb
Host smart-79081d93-24d6-4901-baac-4221175de7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585750540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2585750540
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.841503948
Short name T300
Test name
Test status
Simulation time 503269117559 ps
CPU time 264.48 seconds
Started Apr 04 01:20:08 PM PDT 24
Finished Apr 04 01:24:33 PM PDT 24
Peak memory 202284 kb
Host smart-0ea5d329-dd35-41c7-b93c-0d2b8aed108e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841503948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.841503948
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.1458549846
Short name T276
Test name
Test status
Simulation time 377042179942 ps
CPU time 163.04 seconds
Started Apr 04 01:07:45 PM PDT 24
Finished Apr 04 01:10:28 PM PDT 24
Peak memory 202268 kb
Host smart-388a1882-5abc-4e19-92c4-da125fa5ff71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458549846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
1458549846
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1154372690
Short name T280
Test name
Test status
Simulation time 484814830471 ps
CPU time 1026.63 seconds
Started Apr 04 01:21:03 PM PDT 24
Finished Apr 04 01:38:10 PM PDT 24
Peak memory 202328 kb
Host smart-63fb2fec-4421-4f97-90fe-74cea4527c4a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154372690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1154372690
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.462903371
Short name T298
Test name
Test status
Simulation time 165399876731 ps
CPU time 66.67 seconds
Started Apr 04 01:21:26 PM PDT 24
Finished Apr 04 01:22:33 PM PDT 24
Peak memory 202264 kb
Host smart-060192df-7fa0-4919-8abb-865369bebee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462903371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.462903371
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1910482932
Short name T295
Test name
Test status
Simulation time 332419009307 ps
CPU time 800 seconds
Started Apr 04 01:21:53 PM PDT 24
Finished Apr 04 01:35:13 PM PDT 24
Peak memory 202260 kb
Host smart-07f6e1cc-9b22-409d-829f-c9abcc432f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910482932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1910482932
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1303861589
Short name T146
Test name
Test status
Simulation time 222865625157 ps
CPU time 424.79 seconds
Started Apr 04 01:08:03 PM PDT 24
Finished Apr 04 01:15:08 PM PDT 24
Peak memory 218552 kb
Host smart-7cf10e07-c599-4915-8d70-78781d7f2a4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303861589 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1303861589
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.3734350574
Short name T908
Test name
Test status
Simulation time 578016824 ps
CPU time 2.81 seconds
Started Apr 04 02:56:45 PM PDT 24
Finished Apr 04 02:56:48 PM PDT 24
Peak memory 201352 kb
Host smart-f11d1afa-a9e7-4cce-ac38-51e61827a296
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734350574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.3734350574
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1989116798
Short name T104
Test name
Test status
Simulation time 1020216140 ps
CPU time 5.93 seconds
Started Apr 04 02:56:53 PM PDT 24
Finished Apr 04 02:56:59 PM PDT 24
Peak memory 201364 kb
Host smart-4464cbe1-26fe-479e-9cad-85ea7b66752c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989116798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1989116798
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2481568303
Short name T112
Test name
Test status
Simulation time 724106775 ps
CPU time 1.76 seconds
Started Apr 04 02:56:36 PM PDT 24
Finished Apr 04 02:56:38 PM PDT 24
Peak memory 201196 kb
Host smart-9a3adc0a-cbbb-462c-85c2-20790338c22f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481568303 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2481568303
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2761551133
Short name T75
Test name
Test status
Simulation time 582161110 ps
CPU time 1.34 seconds
Started Apr 04 02:56:45 PM PDT 24
Finished Apr 04 02:56:46 PM PDT 24
Peak memory 201252 kb
Host smart-4e6107c7-20c1-42fd-9b6f-54480b385b9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761551133 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2761551133
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1812531732
Short name T833
Test name
Test status
Simulation time 320463183 ps
CPU time 0.87 seconds
Started Apr 04 02:56:36 PM PDT 24
Finished Apr 04 02:56:37 PM PDT 24
Peak memory 201240 kb
Host smart-c84e7eed-bef5-48d5-b69d-dc29013aa63e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812531732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1812531732
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2321540417
Short name T884
Test name
Test status
Simulation time 2609554189 ps
CPU time 2.16 seconds
Started Apr 04 02:56:39 PM PDT 24
Finished Apr 04 02:56:41 PM PDT 24
Peak memory 201288 kb
Host smart-fca2bc26-9b46-4cd6-8add-9b3b7d3b6bed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321540417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2321540417
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.4286310774
Short name T903
Test name
Test status
Simulation time 699395841 ps
CPU time 2.44 seconds
Started Apr 04 02:56:55 PM PDT 24
Finished Apr 04 02:56:57 PM PDT 24
Peak memory 201496 kb
Host smart-8aefd0a8-3423-4bf3-b751-f97f28340ec1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286310774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.4286310774
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.1993817196
Short name T871
Test name
Test status
Simulation time 4255549028 ps
CPU time 3.81 seconds
Started Apr 04 02:56:46 PM PDT 24
Finished Apr 04 02:56:50 PM PDT 24
Peak memory 201384 kb
Host smart-31d56ea2-ebb7-4655-9281-2bd5bd738325
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993817196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.1993817196
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3920022097
Short name T108
Test name
Test status
Simulation time 641958028 ps
CPU time 1.89 seconds
Started Apr 04 02:56:47 PM PDT 24
Finished Apr 04 02:56:49 PM PDT 24
Peak memory 201452 kb
Host smart-a049383c-767d-43ac-b2b3-3e2ac85e98b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920022097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3920022097
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3283736064
Short name T817
Test name
Test status
Simulation time 26338410523 ps
CPU time 68.15 seconds
Started Apr 04 02:56:42 PM PDT 24
Finished Apr 04 02:57:50 PM PDT 24
Peak memory 201456 kb
Host smart-f353ec0a-4317-46b9-91a3-b97af643e0c5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283736064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3283736064
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.2541699273
Short name T805
Test name
Test status
Simulation time 801533450 ps
CPU time 2.36 seconds
Started Apr 04 02:56:58 PM PDT 24
Finished Apr 04 02:57:00 PM PDT 24
Peak memory 201188 kb
Host smart-a1eb6e41-05cc-4f94-b682-022a97cf93ad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541699273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.2541699273
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2187292097
Short name T890
Test name
Test status
Simulation time 677986928 ps
CPU time 1.36 seconds
Started Apr 04 02:56:50 PM PDT 24
Finished Apr 04 02:56:52 PM PDT 24
Peak memory 201308 kb
Host smart-80b4b550-c757-4ecf-95ef-f767590d2d23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187292097 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.2187292097
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2389202717
Short name T845
Test name
Test status
Simulation time 491404378 ps
CPU time 1.1 seconds
Started Apr 04 02:56:53 PM PDT 24
Finished Apr 04 02:56:54 PM PDT 24
Peak memory 201224 kb
Host smart-f779d7de-c7d6-42a8-a931-492d8810b7af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389202717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2389202717
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.1265803213
Short name T891
Test name
Test status
Simulation time 336749078 ps
CPU time 1.46 seconds
Started Apr 04 02:56:51 PM PDT 24
Finished Apr 04 02:56:52 PM PDT 24
Peak memory 201244 kb
Host smart-a9a4c330-a6db-486a-ad6c-9a32921a0cca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265803213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.1265803213
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2867415050
Short name T816
Test name
Test status
Simulation time 4914345909 ps
CPU time 12.43 seconds
Started Apr 04 02:56:48 PM PDT 24
Finished Apr 04 02:57:01 PM PDT 24
Peak memory 201456 kb
Host smart-948a03e4-9b26-4023-9283-304e0e6eb373
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867415050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.2867415050
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.512732513
Short name T69
Test name
Test status
Simulation time 509612456 ps
CPU time 1.88 seconds
Started Apr 04 02:56:50 PM PDT 24
Finished Apr 04 02:56:52 PM PDT 24
Peak memory 209748 kb
Host smart-6a164570-847b-4f9b-ba0c-acf78f815ad3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512732513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.512732513
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.3800902660
Short name T58
Test name
Test status
Simulation time 4371809139 ps
CPU time 7.16 seconds
Started Apr 04 02:56:53 PM PDT 24
Finished Apr 04 02:57:01 PM PDT 24
Peak memory 201468 kb
Host smart-f2a0924f-1f28-43df-89ae-90611b8dc8ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800902660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.3800902660
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.4112642821
Short name T866
Test name
Test status
Simulation time 727064713 ps
CPU time 1.12 seconds
Started Apr 04 02:57:02 PM PDT 24
Finished Apr 04 02:57:03 PM PDT 24
Peak memory 201364 kb
Host smart-be9e5343-d34d-439d-9754-4513178010a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112642821 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.4112642821
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.763358777
Short name T105
Test name
Test status
Simulation time 363178817 ps
CPU time 1 seconds
Started Apr 04 02:57:01 PM PDT 24
Finished Apr 04 02:57:02 PM PDT 24
Peak memory 201220 kb
Host smart-a7b488d0-edf5-45e6-aaa6-0faa74f5b49b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763358777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.763358777
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2756736339
Short name T913
Test name
Test status
Simulation time 373128457 ps
CPU time 1.43 seconds
Started Apr 04 02:56:57 PM PDT 24
Finished Apr 04 02:56:59 PM PDT 24
Peak memory 201224 kb
Host smart-e97a7427-9a7c-4fbf-9d66-40fac1749d31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756736339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.2756736339
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.226725551
Short name T117
Test name
Test status
Simulation time 4110096084 ps
CPU time 3.06 seconds
Started Apr 04 02:56:52 PM PDT 24
Finished Apr 04 02:56:55 PM PDT 24
Peak memory 201452 kb
Host smart-f3965a71-dfbd-489f-86e7-4311a86f118f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226725551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.226725551
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.4284119849
Short name T822
Test name
Test status
Simulation time 535238805 ps
CPU time 2.71 seconds
Started Apr 04 02:57:01 PM PDT 24
Finished Apr 04 02:57:03 PM PDT 24
Peak memory 201524 kb
Host smart-a0a6d69d-3b6f-4fee-af52-753556859fdf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284119849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.4284119849
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.418919445
Short name T860
Test name
Test status
Simulation time 613138120 ps
CPU time 1.68 seconds
Started Apr 04 02:56:56 PM PDT 24
Finished Apr 04 02:56:58 PM PDT 24
Peak memory 201288 kb
Host smart-2bb6de52-f1be-478e-84db-894d1d02ddcc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418919445 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.418919445
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.920046541
Short name T823
Test name
Test status
Simulation time 444923903 ps
CPU time 0.96 seconds
Started Apr 04 02:56:57 PM PDT 24
Finished Apr 04 02:56:58 PM PDT 24
Peak memory 201228 kb
Host smart-23d00f32-57ab-487b-ae35-1c6866ba9996
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920046541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.920046541
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.893909083
Short name T811
Test name
Test status
Simulation time 424773747 ps
CPU time 1.67 seconds
Started Apr 04 02:57:03 PM PDT 24
Finished Apr 04 02:57:05 PM PDT 24
Peak memory 201128 kb
Host smart-bbd38ead-f957-4a7b-a097-25b2a8274c63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893909083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.893909083
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.778613858
Short name T118
Test name
Test status
Simulation time 4177873920 ps
CPU time 3.12 seconds
Started Apr 04 02:56:54 PM PDT 24
Finished Apr 04 02:56:57 PM PDT 24
Peak memory 201456 kb
Host smart-d89f3c21-5e3f-4954-8687-d08a69985cad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778613858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_c
trl_same_csr_outstanding.778613858
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2770842420
Short name T906
Test name
Test status
Simulation time 819015391 ps
CPU time 2.85 seconds
Started Apr 04 02:56:57 PM PDT 24
Finished Apr 04 02:57:00 PM PDT 24
Peak memory 217560 kb
Host smart-0bb7c18d-97a3-4264-a8d5-33496ff9c3e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770842420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2770842420
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.186001189
Short name T61
Test name
Test status
Simulation time 8477867056 ps
CPU time 22.27 seconds
Started Apr 04 02:57:02 PM PDT 24
Finished Apr 04 02:57:24 PM PDT 24
Peak memory 201456 kb
Host smart-bfff2d18-7521-4282-b009-277618ce358f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186001189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_in
tg_err.186001189
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.3931573713
Short name T74
Test name
Test status
Simulation time 448121100 ps
CPU time 1.94 seconds
Started Apr 04 02:56:50 PM PDT 24
Finished Apr 04 02:56:53 PM PDT 24
Peak memory 201220 kb
Host smart-8bd48e13-9145-4506-b8e1-71c38878948c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931573713 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.3931573713
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2583678318
Short name T830
Test name
Test status
Simulation time 490400414 ps
CPU time 1.98 seconds
Started Apr 04 02:56:59 PM PDT 24
Finished Apr 04 02:57:01 PM PDT 24
Peak memory 201192 kb
Host smart-4344b7af-b734-471a-aa20-718536006515
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583678318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.2583678318
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2688157825
Short name T795
Test name
Test status
Simulation time 413899191 ps
CPU time 0.89 seconds
Started Apr 04 02:56:57 PM PDT 24
Finished Apr 04 02:56:58 PM PDT 24
Peak memory 201192 kb
Host smart-bea5605a-3505-4ca0-ae31-5f9e0eec185e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688157825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.2688157825
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.4082413122
Short name T835
Test name
Test status
Simulation time 2214557032 ps
CPU time 2.6 seconds
Started Apr 04 02:56:58 PM PDT 24
Finished Apr 04 02:57:01 PM PDT 24
Peak memory 201280 kb
Host smart-06fa313b-170d-4b13-a01a-2444d8f5202a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082413122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.4082413122
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.3770338275
Short name T893
Test name
Test status
Simulation time 537635880 ps
CPU time 2.07 seconds
Started Apr 04 02:57:07 PM PDT 24
Finished Apr 04 02:57:10 PM PDT 24
Peak memory 201440 kb
Host smart-2ac83244-0074-4ce5-9abc-59a3f6422a7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770338275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.3770338275
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1092360238
Short name T86
Test name
Test status
Simulation time 8889111367 ps
CPU time 7.65 seconds
Started Apr 04 02:56:58 PM PDT 24
Finished Apr 04 02:57:06 PM PDT 24
Peak memory 201432 kb
Host smart-1dd4bd17-011f-4f1b-bba9-7be6791bab8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092360238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1092360238
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.2610089002
Short name T892
Test name
Test status
Simulation time 402995248 ps
CPU time 1.73 seconds
Started Apr 04 02:57:00 PM PDT 24
Finished Apr 04 02:57:02 PM PDT 24
Peak memory 201284 kb
Host smart-732a798b-4737-4f5c-b4cf-a15ef3db87b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610089002 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.2610089002
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1596131848
Short name T111
Test name
Test status
Simulation time 372904700 ps
CPU time 1.64 seconds
Started Apr 04 02:56:50 PM PDT 24
Finished Apr 04 02:56:51 PM PDT 24
Peak memory 201156 kb
Host smart-83bc9fe4-97d8-40e1-a5b2-0493e4a78c7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596131848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1596131848
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.3464669449
Short name T801
Test name
Test status
Simulation time 429829903 ps
CPU time 1.73 seconds
Started Apr 04 02:57:02 PM PDT 24
Finished Apr 04 02:57:04 PM PDT 24
Peak memory 201212 kb
Host smart-5f944c0b-7e95-4ed5-989e-f069de772cfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464669449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.3464669449
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.324747593
Short name T879
Test name
Test status
Simulation time 2065773061 ps
CPU time 3.13 seconds
Started Apr 04 02:57:01 PM PDT 24
Finished Apr 04 02:57:04 PM PDT 24
Peak memory 201228 kb
Host smart-4892db35-5864-4d1a-9ded-d526feed4d35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324747593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.324747593
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.363298839
Short name T854
Test name
Test status
Simulation time 593935442 ps
CPU time 3.64 seconds
Started Apr 04 02:56:52 PM PDT 24
Finished Apr 04 02:56:56 PM PDT 24
Peak memory 217456 kb
Host smart-93da0e63-2453-46af-bbea-5a64dd10c658
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363298839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.363298839
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.813243234
Short name T820
Test name
Test status
Simulation time 612163870 ps
CPU time 1.72 seconds
Started Apr 04 02:56:57 PM PDT 24
Finished Apr 04 02:56:59 PM PDT 24
Peak memory 201260 kb
Host smart-68805fd8-7d83-4df4-97a8-cd4beb080373
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813243234 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.813243234
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3252947991
Short name T114
Test name
Test status
Simulation time 331489987 ps
CPU time 1.47 seconds
Started Apr 04 02:57:03 PM PDT 24
Finished Apr 04 02:57:05 PM PDT 24
Peak memory 201104 kb
Host smart-894bb45e-c007-4f3b-861e-7f41264791dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252947991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.3252947991
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3777746071
Short name T910
Test name
Test status
Simulation time 427980279 ps
CPU time 1.69 seconds
Started Apr 04 02:57:00 PM PDT 24
Finished Apr 04 02:57:02 PM PDT 24
Peak memory 201176 kb
Host smart-a5321fd2-9b8f-4f15-be18-115f8f32baca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777746071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3777746071
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2017590846
Short name T889
Test name
Test status
Simulation time 4551634139 ps
CPU time 3.96 seconds
Started Apr 04 02:56:52 PM PDT 24
Finished Apr 04 02:56:56 PM PDT 24
Peak memory 201392 kb
Host smart-74016370-3bf4-4f07-ad7e-889842ca5dad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017590846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2017590846
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.983341920
Short name T68
Test name
Test status
Simulation time 628558319 ps
CPU time 2.71 seconds
Started Apr 04 02:57:03 PM PDT 24
Finished Apr 04 02:57:06 PM PDT 24
Peak memory 201428 kb
Host smart-6a787666-e8b0-4222-aadb-4c84a5b2c985
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983341920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.983341920
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1314558481
Short name T855
Test name
Test status
Simulation time 4506269229 ps
CPU time 12.29 seconds
Started Apr 04 02:56:57 PM PDT 24
Finished Apr 04 02:57:10 PM PDT 24
Peak memory 201484 kb
Host smart-170a2e2e-9229-4ec9-bbcc-dd887a0b0ee8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314558481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.1314558481
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.3249232391
Short name T89
Test name
Test status
Simulation time 373995178 ps
CPU time 1.1 seconds
Started Apr 04 02:56:53 PM PDT 24
Finished Apr 04 02:56:54 PM PDT 24
Peak memory 201224 kb
Host smart-9c193f9d-d8b4-4600-9d9d-68ba8a86475c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249232391 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.3249232391
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.783506601
Short name T846
Test name
Test status
Simulation time 484163867 ps
CPU time 1.22 seconds
Started Apr 04 02:57:04 PM PDT 24
Finished Apr 04 02:57:05 PM PDT 24
Peak memory 201192 kb
Host smart-71f33e9b-8e7d-43bf-b5fc-e3d8130829fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783506601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.783506601
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2453596102
Short name T917
Test name
Test status
Simulation time 446066827 ps
CPU time 1.7 seconds
Started Apr 04 02:56:57 PM PDT 24
Finished Apr 04 02:56:59 PM PDT 24
Peak memory 201236 kb
Host smart-4f0e330c-65ba-4710-8055-0cf6ee0ad601
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453596102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.2453596102
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3802922313
Short name T888
Test name
Test status
Simulation time 2276376182 ps
CPU time 3.39 seconds
Started Apr 04 02:56:51 PM PDT 24
Finished Apr 04 02:56:55 PM PDT 24
Peak memory 201192 kb
Host smart-a9652fb7-cf63-4dfe-9a09-d05f0b74d586
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802922313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.3802922313
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.1834024586
Short name T65
Test name
Test status
Simulation time 603428813 ps
CPU time 2.25 seconds
Started Apr 04 02:56:51 PM PDT 24
Finished Apr 04 02:56:53 PM PDT 24
Peak memory 201464 kb
Host smart-01d7a3e2-162e-46d5-b6c5-07fdb0a3c5e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834024586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.1834024586
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.4014413610
Short name T844
Test name
Test status
Simulation time 8394397481 ps
CPU time 21.65 seconds
Started Apr 04 02:56:53 PM PDT 24
Finished Apr 04 02:57:20 PM PDT 24
Peak memory 201428 kb
Host smart-e7c6e063-4d55-41c5-8b02-d6bdb9a109cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014413610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.4014413610
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.12180565
Short name T904
Test name
Test status
Simulation time 783953105 ps
CPU time 1.25 seconds
Started Apr 04 02:56:57 PM PDT 24
Finished Apr 04 02:56:59 PM PDT 24
Peak memory 201272 kb
Host smart-77f81dfd-0883-456f-86b2-d4888a18ad7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12180565 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.12180565
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2576807294
Short name T815
Test name
Test status
Simulation time 481066340 ps
CPU time 0.99 seconds
Started Apr 04 02:57:00 PM PDT 24
Finished Apr 04 02:57:01 PM PDT 24
Peak memory 201188 kb
Host smart-5d5d815c-71c1-4a6c-9d37-63eed0b4cdfd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576807294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2576807294
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3337983977
Short name T896
Test name
Test status
Simulation time 540351126 ps
CPU time 0.79 seconds
Started Apr 04 02:56:53 PM PDT 24
Finished Apr 04 02:56:54 PM PDT 24
Peak memory 201212 kb
Host smart-e1e4247f-4de8-4623-b4e1-e2e6ca152d50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337983977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3337983977
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.4006248503
Short name T813
Test name
Test status
Simulation time 4556342386 ps
CPU time 17.84 seconds
Started Apr 04 02:57:02 PM PDT 24
Finished Apr 04 02:57:20 PM PDT 24
Peak memory 201436 kb
Host smart-91e101e2-8ca0-4bee-b3da-8a1b9c06f6ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006248503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.4006248503
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3048231628
Short name T870
Test name
Test status
Simulation time 319342971 ps
CPU time 2.97 seconds
Started Apr 04 02:56:57 PM PDT 24
Finished Apr 04 02:57:00 PM PDT 24
Peak memory 201452 kb
Host smart-6eb0c88d-900a-4620-86c8-45303e54873b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048231628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3048231628
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2725624992
Short name T62
Test name
Test status
Simulation time 8421481040 ps
CPU time 22.43 seconds
Started Apr 04 02:57:02 PM PDT 24
Finished Apr 04 02:57:25 PM PDT 24
Peak memory 201444 kb
Host smart-927a4dab-8ffb-4d1c-80c1-5f59da24b6d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725624992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.2725624992
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1553176968
Short name T814
Test name
Test status
Simulation time 457250505 ps
CPU time 1.22 seconds
Started Apr 04 02:57:28 PM PDT 24
Finished Apr 04 02:57:30 PM PDT 24
Peak memory 201268 kb
Host smart-2db68d95-7404-44f7-b37e-af14a568dd04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553176968 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.1553176968
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.2429594204
Short name T872
Test name
Test status
Simulation time 401944633 ps
CPU time 1.63 seconds
Started Apr 04 02:57:18 PM PDT 24
Finished Apr 04 02:57:20 PM PDT 24
Peak memory 201216 kb
Host smart-29746fe7-1132-4b71-9c9e-a2d5fcd3b3a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429594204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.2429594204
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1739088564
Short name T867
Test name
Test status
Simulation time 541481029 ps
CPU time 0.93 seconds
Started Apr 04 02:57:04 PM PDT 24
Finished Apr 04 02:57:05 PM PDT 24
Peak memory 201224 kb
Host smart-07f8c4c0-dd5f-4926-917b-d860d88db311
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739088564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1739088564
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2653239615
Short name T916
Test name
Test status
Simulation time 2657348854 ps
CPU time 2.1 seconds
Started Apr 04 02:57:27 PM PDT 24
Finished Apr 04 02:57:29 PM PDT 24
Peak memory 201332 kb
Host smart-634e5d3a-f92e-4a6e-b22f-473a5828ac88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653239615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.2653239615
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.1767316971
Short name T831
Test name
Test status
Simulation time 566450880 ps
CPU time 2.16 seconds
Started Apr 04 02:56:56 PM PDT 24
Finished Apr 04 02:56:58 PM PDT 24
Peak memory 201440 kb
Host smart-4368fd2e-5ec0-4a16-981b-9f2642a58fc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767316971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.1767316971
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1628566446
Short name T56
Test name
Test status
Simulation time 4170106532 ps
CPU time 11.25 seconds
Started Apr 04 02:57:17 PM PDT 24
Finished Apr 04 02:57:29 PM PDT 24
Peak memory 201428 kb
Host smart-307ced4b-a7c3-42ed-819f-99c304219440
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628566446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.1628566446
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1430482911
Short name T869
Test name
Test status
Simulation time 392444824 ps
CPU time 1.87 seconds
Started Apr 04 02:57:06 PM PDT 24
Finished Apr 04 02:57:08 PM PDT 24
Peak memory 201288 kb
Host smart-6432ad35-ec3a-43fd-b88b-8d0867c6e9bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430482911 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1430482911
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1791442111
Short name T109
Test name
Test status
Simulation time 461588530 ps
CPU time 1.25 seconds
Started Apr 04 02:57:25 PM PDT 24
Finished Apr 04 02:57:26 PM PDT 24
Peak memory 201156 kb
Host smart-b0a68725-a79f-4bd3-adb9-fa4445e1d16f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791442111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.1791442111
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1221496375
Short name T856
Test name
Test status
Simulation time 505101590 ps
CPU time 1.77 seconds
Started Apr 04 02:57:08 PM PDT 24
Finished Apr 04 02:57:10 PM PDT 24
Peak memory 201216 kb
Host smart-4ce4a5a3-f428-4807-8899-7d74ea512825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221496375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1221496375
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2460508915
Short name T834
Test name
Test status
Simulation time 2504816350 ps
CPU time 5.93 seconds
Started Apr 04 02:57:03 PM PDT 24
Finished Apr 04 02:57:09 PM PDT 24
Peak memory 201244 kb
Host smart-d99ee2fa-16eb-45ed-982c-66a9d83c313f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460508915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2460508915
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1944117678
Short name T852
Test name
Test status
Simulation time 537352370 ps
CPU time 2.73 seconds
Started Apr 04 02:57:02 PM PDT 24
Finished Apr 04 02:57:05 PM PDT 24
Peak memory 201480 kb
Host smart-5e8b6daa-97ef-4537-92bb-372eb7f8097d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944117678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1944117678
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.207141563
Short name T57
Test name
Test status
Simulation time 4346384390 ps
CPU time 12.19 seconds
Started Apr 04 02:57:17 PM PDT 24
Finished Apr 04 02:57:29 PM PDT 24
Peak memory 201452 kb
Host smart-26ab863d-cfe6-4262-8c3b-54abe9db0c7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207141563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in
tg_err.207141563
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1500411570
Short name T76
Test name
Test status
Simulation time 575307086 ps
CPU time 1.07 seconds
Started Apr 04 02:57:07 PM PDT 24
Finished Apr 04 02:57:09 PM PDT 24
Peak memory 201236 kb
Host smart-40991f55-27fa-4dd2-adf0-f3c7eee04e28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500411570 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1500411570
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2917407677
Short name T101
Test name
Test status
Simulation time 579525194 ps
CPU time 0.86 seconds
Started Apr 04 02:57:04 PM PDT 24
Finished Apr 04 02:57:05 PM PDT 24
Peak memory 201192 kb
Host smart-09169518-b246-44db-848c-4d181584a6f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917407677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2917407677
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.1197034440
Short name T915
Test name
Test status
Simulation time 377095297 ps
CPU time 1.14 seconds
Started Apr 04 02:57:13 PM PDT 24
Finished Apr 04 02:57:14 PM PDT 24
Peak memory 201244 kb
Host smart-cee93560-e6ca-4f77-bbda-831ca5c15f04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197034440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.1197034440
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.542280477
Short name T832
Test name
Test status
Simulation time 4427225892 ps
CPU time 10.39 seconds
Started Apr 04 02:57:12 PM PDT 24
Finished Apr 04 02:57:23 PM PDT 24
Peak memory 201480 kb
Host smart-466e92d8-bb50-4720-b548-e67e8f31f80a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542280477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.542280477
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.127393108
Short name T858
Test name
Test status
Simulation time 4445481062 ps
CPU time 4.02 seconds
Started Apr 04 02:57:12 PM PDT 24
Finished Apr 04 02:57:16 PM PDT 24
Peak memory 201444 kb
Host smart-ed54cd69-4d88-4753-bfdb-fe3b35a94362
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127393108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.127393108
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3443768434
Short name T106
Test name
Test status
Simulation time 1293736832 ps
CPU time 2.64 seconds
Started Apr 04 02:56:49 PM PDT 24
Finished Apr 04 02:56:51 PM PDT 24
Peak memory 201416 kb
Host smart-886d629d-1015-4f54-b682-58f49dfc0514
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443768434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.3443768434
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.958064085
Short name T809
Test name
Test status
Simulation time 26019453949 ps
CPU time 88.43 seconds
Started Apr 04 02:56:36 PM PDT 24
Finished Apr 04 02:58:05 PM PDT 24
Peak memory 201452 kb
Host smart-37fd6155-8e44-4c42-b102-546ce9f80c0a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958064085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_b
ash.958064085
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.3351824946
Short name T110
Test name
Test status
Simulation time 1130981275 ps
CPU time 3.39 seconds
Started Apr 04 02:56:49 PM PDT 24
Finished Apr 04 02:56:52 PM PDT 24
Peak memory 201216 kb
Host smart-1de656fc-9a5b-46d0-ac33-f31e2231f8d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351824946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.3351824946
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2957391103
Short name T859
Test name
Test status
Simulation time 522586006 ps
CPU time 1.28 seconds
Started Apr 04 02:56:49 PM PDT 24
Finished Apr 04 02:56:51 PM PDT 24
Peak memory 201340 kb
Host smart-02482109-843e-4572-a5f6-aec2fcdfe498
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957391103 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2957391103
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.4064064808
Short name T116
Test name
Test status
Simulation time 446150791 ps
CPU time 1.07 seconds
Started Apr 04 02:56:48 PM PDT 24
Finished Apr 04 02:56:49 PM PDT 24
Peak memory 201224 kb
Host smart-899f8571-e4db-4f65-9188-bb0541f50ecb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064064808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.4064064808
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.2369522791
Short name T838
Test name
Test status
Simulation time 434352137 ps
CPU time 1.71 seconds
Started Apr 04 02:56:59 PM PDT 24
Finished Apr 04 02:57:01 PM PDT 24
Peak memory 201236 kb
Host smart-e6c98ff8-8cfc-4571-8d84-7afa070782c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369522791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.2369522791
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.1328598801
Short name T868
Test name
Test status
Simulation time 4163604901 ps
CPU time 10.74 seconds
Started Apr 04 02:56:55 PM PDT 24
Finished Apr 04 02:57:05 PM PDT 24
Peak memory 201176 kb
Host smart-5b008cdc-8938-4f64-a142-6c1b231542ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328598801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.1328598801
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2825803118
Short name T914
Test name
Test status
Simulation time 395503301 ps
CPU time 3.02 seconds
Started Apr 04 02:56:53 PM PDT 24
Finished Apr 04 02:56:56 PM PDT 24
Peak memory 217296 kb
Host smart-e2a9c87d-f865-48cf-a52b-391ecdbafe07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825803118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2825803118
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2200559017
Short name T897
Test name
Test status
Simulation time 4586957277 ps
CPU time 4.18 seconds
Started Apr 04 02:56:44 PM PDT 24
Finished Apr 04 02:56:48 PM PDT 24
Peak memory 201472 kb
Host smart-f7225515-8cc0-4b09-bbfb-7c8d1efc747f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200559017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2200559017
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2280446296
Short name T881
Test name
Test status
Simulation time 372215198 ps
CPU time 1.38 seconds
Started Apr 04 02:57:00 PM PDT 24
Finished Apr 04 02:57:02 PM PDT 24
Peak memory 201172 kb
Host smart-d3fb7ad7-9a21-497b-8cd0-02df4a9d9647
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280446296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2280446296
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3591335137
Short name T802
Test name
Test status
Simulation time 488453971 ps
CPU time 1.82 seconds
Started Apr 04 02:57:05 PM PDT 24
Finished Apr 04 02:57:07 PM PDT 24
Peak memory 201208 kb
Host smart-5aae1e49-9968-45d0-a0f8-46017176a05a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591335137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3591335137
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3638148658
Short name T861
Test name
Test status
Simulation time 393895210 ps
CPU time 1.56 seconds
Started Apr 04 02:57:02 PM PDT 24
Finished Apr 04 02:57:04 PM PDT 24
Peak memory 201184 kb
Host smart-842e2022-b568-4d4b-9a1f-897259489e7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638148658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.3638148658
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.824394135
Short name T905
Test name
Test status
Simulation time 304955207 ps
CPU time 1.38 seconds
Started Apr 04 02:57:06 PM PDT 24
Finished Apr 04 02:57:07 PM PDT 24
Peak memory 201224 kb
Host smart-16d7d86b-587b-46d2-8cac-2da6d37db720
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824394135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.824394135
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.944837529
Short name T803
Test name
Test status
Simulation time 581215908 ps
CPU time 0.85 seconds
Started Apr 04 02:57:03 PM PDT 24
Finished Apr 04 02:57:04 PM PDT 24
Peak memory 201204 kb
Host smart-61f16550-4727-46eb-b6da-dd494a023f77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944837529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.944837529
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.4043746609
Short name T850
Test name
Test status
Simulation time 341515224 ps
CPU time 1.01 seconds
Started Apr 04 02:57:09 PM PDT 24
Finished Apr 04 02:57:10 PM PDT 24
Peak memory 201216 kb
Host smart-8363ec4f-7328-4245-93e2-19f6a33a0cc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043746609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.4043746609
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.103924535
Short name T798
Test name
Test status
Simulation time 468562286 ps
CPU time 0.91 seconds
Started Apr 04 02:57:11 PM PDT 24
Finished Apr 04 02:57:12 PM PDT 24
Peak memory 201212 kb
Host smart-431005d7-9b78-4b78-b385-aa66c30c278f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103924535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.103924535
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.253576013
Short name T909
Test name
Test status
Simulation time 320610476 ps
CPU time 1.31 seconds
Started Apr 04 02:57:10 PM PDT 24
Finished Apr 04 02:57:11 PM PDT 24
Peak memory 201128 kb
Host smart-2b77523e-7aec-40d2-90f9-d7381ada2374
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253576013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.253576013
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1500785207
Short name T806
Test name
Test status
Simulation time 328056260 ps
CPU time 1.37 seconds
Started Apr 04 02:57:04 PM PDT 24
Finished Apr 04 02:57:05 PM PDT 24
Peak memory 201240 kb
Host smart-fb01ec5d-b4a4-44a9-ba09-e7ff093b3fbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500785207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1500785207
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.105313077
Short name T828
Test name
Test status
Simulation time 536977938 ps
CPU time 0.74 seconds
Started Apr 04 02:57:12 PM PDT 24
Finished Apr 04 02:57:13 PM PDT 24
Peak memory 201232 kb
Host smart-97d97f13-89b7-44fe-a047-33813f9b9e4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105313077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.105313077
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.4115248165
Short name T900
Test name
Test status
Simulation time 677268996 ps
CPU time 3.62 seconds
Started Apr 04 02:56:46 PM PDT 24
Finished Apr 04 02:56:49 PM PDT 24
Peak memory 201448 kb
Host smart-1e78edf9-0d30-406c-a3f5-a26c8bc791de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115248165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.4115248165
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2226379455
Short name T894
Test name
Test status
Simulation time 25879162223 ps
CPU time 56.97 seconds
Started Apr 04 02:57:00 PM PDT 24
Finished Apr 04 02:57:57 PM PDT 24
Peak memory 201452 kb
Host smart-51fce010-28ec-45f3-b727-1fee28ea0fa5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226379455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.2226379455
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.280582776
Short name T841
Test name
Test status
Simulation time 788342148 ps
CPU time 1.63 seconds
Started Apr 04 02:56:57 PM PDT 24
Finished Apr 04 02:56:59 PM PDT 24
Peak memory 201224 kb
Host smart-91c30c5a-2c2b-40d9-9f6d-7335ea383130
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280582776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.280582776
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.697790056
Short name T840
Test name
Test status
Simulation time 446148983 ps
CPU time 1.48 seconds
Started Apr 04 02:56:50 PM PDT 24
Finished Apr 04 02:56:52 PM PDT 24
Peak memory 201308 kb
Host smart-35d30f14-49af-4869-9a97-3a10e32a531c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697790056 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.697790056
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.33245946
Short name T103
Test name
Test status
Simulation time 442953952 ps
CPU time 1.75 seconds
Started Apr 04 02:56:48 PM PDT 24
Finished Apr 04 02:56:50 PM PDT 24
Peak memory 201220 kb
Host smart-9584cc9e-625d-4955-91c6-12385a060210
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33245946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.33245946
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.1049040963
Short name T874
Test name
Test status
Simulation time 339996123 ps
CPU time 0.79 seconds
Started Apr 04 02:56:59 PM PDT 24
Finished Apr 04 02:57:00 PM PDT 24
Peak memory 201236 kb
Host smart-1fd8ce0b-e08a-442c-89d1-14f1ea4e86e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049040963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.1049040963
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.3073538768
Short name T862
Test name
Test status
Simulation time 2688709372 ps
CPU time 6.71 seconds
Started Apr 04 02:56:55 PM PDT 24
Finished Apr 04 02:57:01 PM PDT 24
Peak memory 200980 kb
Host smart-ded94573-e499-44d9-99f9-a982bb462019
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073538768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.3073538768
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.191239649
Short name T839
Test name
Test status
Simulation time 424763299 ps
CPU time 2.82 seconds
Started Apr 04 02:56:35 PM PDT 24
Finished Apr 04 02:56:38 PM PDT 24
Peak memory 201548 kb
Host smart-faa6b02c-186a-4881-ab66-89280b255f45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191239649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.191239649
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.3099883635
Short name T877
Test name
Test status
Simulation time 8355688339 ps
CPU time 20.54 seconds
Started Apr 04 02:56:51 PM PDT 24
Finished Apr 04 02:57:12 PM PDT 24
Peak memory 201492 kb
Host smart-31e20d56-ef13-4172-aba7-51192f07ed98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099883635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.3099883635
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3332012989
Short name T911
Test name
Test status
Simulation time 382862382 ps
CPU time 1.62 seconds
Started Apr 04 02:57:04 PM PDT 24
Finished Apr 04 02:57:06 PM PDT 24
Peak memory 201232 kb
Host smart-f93151d5-85b1-41ba-b3dc-9e4f55c8f885
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332012989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3332012989
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1171309332
Short name T800
Test name
Test status
Simulation time 436157838 ps
CPU time 1.69 seconds
Started Apr 04 02:57:04 PM PDT 24
Finished Apr 04 02:57:05 PM PDT 24
Peak memory 201248 kb
Host smart-142d1419-0d25-4aaa-be41-998877803796
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171309332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1171309332
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1435544669
Short name T853
Test name
Test status
Simulation time 501797393 ps
CPU time 0.82 seconds
Started Apr 04 02:57:03 PM PDT 24
Finished Apr 04 02:57:09 PM PDT 24
Peak memory 201224 kb
Host smart-c1d2d594-0ccb-4a27-8879-b5767bd4b29a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435544669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1435544669
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2813166689
Short name T825
Test name
Test status
Simulation time 500718571 ps
CPU time 0.94 seconds
Started Apr 04 02:57:04 PM PDT 24
Finished Apr 04 02:57:05 PM PDT 24
Peak memory 201196 kb
Host smart-28a0bc37-75b9-44e5-91db-28d36f68b833
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813166689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2813166689
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1070620803
Short name T848
Test name
Test status
Simulation time 493194725 ps
CPU time 1.34 seconds
Started Apr 04 02:57:04 PM PDT 24
Finished Apr 04 02:57:05 PM PDT 24
Peak memory 201236 kb
Host smart-931408b8-c3e2-4c93-a060-1b14fe09dccb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070620803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1070620803
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1689884020
Short name T808
Test name
Test status
Simulation time 467591384 ps
CPU time 0.72 seconds
Started Apr 04 02:57:06 PM PDT 24
Finished Apr 04 02:57:07 PM PDT 24
Peak memory 201240 kb
Host smart-d09e9942-7b87-4110-925e-c56f6b441ef1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689884020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1689884020
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.3675872885
Short name T819
Test name
Test status
Simulation time 474254134 ps
CPU time 1.53 seconds
Started Apr 04 02:57:11 PM PDT 24
Finished Apr 04 02:57:12 PM PDT 24
Peak memory 201212 kb
Host smart-16f38b20-bf34-470c-b41c-2edb47d431c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675872885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.3675872885
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3463755450
Short name T804
Test name
Test status
Simulation time 396075139 ps
CPU time 0.85 seconds
Started Apr 04 02:57:08 PM PDT 24
Finished Apr 04 02:57:09 PM PDT 24
Peak memory 201228 kb
Host smart-2b225259-9e9f-4e02-aa83-1679ee3c2dd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463755450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3463755450
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2672865571
Short name T836
Test name
Test status
Simulation time 319989446 ps
CPU time 0.85 seconds
Started Apr 04 02:57:02 PM PDT 24
Finished Apr 04 02:57:03 PM PDT 24
Peak memory 201232 kb
Host smart-e7e570f8-2351-469c-a22f-84ec64feb6d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672865571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2672865571
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.464104739
Short name T863
Test name
Test status
Simulation time 475322435 ps
CPU time 0.94 seconds
Started Apr 04 02:57:14 PM PDT 24
Finished Apr 04 02:57:15 PM PDT 24
Peak memory 201240 kb
Host smart-a0da360a-201f-431c-8ad0-336b621deee4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464104739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.464104739
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.4187600791
Short name T842
Test name
Test status
Simulation time 925240633 ps
CPU time 2.07 seconds
Started Apr 04 02:56:53 PM PDT 24
Finished Apr 04 02:56:56 PM PDT 24
Peak memory 201412 kb
Host smart-f1dad6c9-711a-4ed0-a15c-d2727d30e07d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187600791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.4187600791
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.296360853
Short name T119
Test name
Test status
Simulation time 568368340 ps
CPU time 2.05 seconds
Started Apr 04 02:56:34 PM PDT 24
Finished Apr 04 02:56:36 PM PDT 24
Peak memory 201228 kb
Host smart-f4ef91e0-6924-48e1-8976-c225c9e75307
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296360853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_re
set.296360853
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.1752288647
Short name T873
Test name
Test status
Simulation time 677505999 ps
CPU time 1.79 seconds
Started Apr 04 02:56:42 PM PDT 24
Finished Apr 04 02:56:49 PM PDT 24
Peak memory 201240 kb
Host smart-8f2655ce-4fcc-4fc4-be33-541672ff3e7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752288647 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.1752288647
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.8916644
Short name T107
Test name
Test status
Simulation time 363855359 ps
CPU time 1 seconds
Started Apr 04 02:56:46 PM PDT 24
Finished Apr 04 02:56:48 PM PDT 24
Peak memory 201228 kb
Host smart-63f2d302-362b-4576-9ba3-a86d5c56ca23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8916644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.8916644
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.432645921
Short name T829
Test name
Test status
Simulation time 406100304 ps
CPU time 0.84 seconds
Started Apr 04 02:56:39 PM PDT 24
Finished Apr 04 02:56:40 PM PDT 24
Peak memory 201296 kb
Host smart-a183d1de-0a71-4bdb-9b21-2eaea9d2ddc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432645921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.432645921
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1441125957
Short name T54
Test name
Test status
Simulation time 2488264103 ps
CPU time 1.53 seconds
Started Apr 04 02:56:37 PM PDT 24
Finished Apr 04 02:56:39 PM PDT 24
Peak memory 201304 kb
Host smart-dab16da0-8526-40bd-b425-fd8b9086d8e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441125957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1441125957
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2424287640
Short name T912
Test name
Test status
Simulation time 517104324 ps
CPU time 2.69 seconds
Started Apr 04 02:56:46 PM PDT 24
Finished Apr 04 02:56:48 PM PDT 24
Peak memory 209680 kb
Host smart-609a44dc-1e04-43b0-8486-1439873a56a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424287640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2424287640
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2968378212
Short name T895
Test name
Test status
Simulation time 4349433866 ps
CPU time 6.92 seconds
Started Apr 04 02:56:40 PM PDT 24
Finished Apr 04 02:56:47 PM PDT 24
Peak memory 201472 kb
Host smart-2f83b9e8-8b3c-463d-a58a-e22adde350e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968378212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2968378212
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2275988411
Short name T875
Test name
Test status
Simulation time 540583663 ps
CPU time 1.31 seconds
Started Apr 04 02:57:02 PM PDT 24
Finished Apr 04 02:57:03 PM PDT 24
Peak memory 201232 kb
Host smart-5d62e8ad-5c8f-438c-893e-f958c2705e1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275988411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.2275988411
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2231664498
Short name T899
Test name
Test status
Simulation time 310860467 ps
CPU time 1.03 seconds
Started Apr 04 02:57:02 PM PDT 24
Finished Apr 04 02:57:03 PM PDT 24
Peak memory 201172 kb
Host smart-6bd8560d-a530-444a-b703-d03caf57e649
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231664498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2231664498
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.3405192743
Short name T886
Test name
Test status
Simulation time 468423097 ps
CPU time 0.75 seconds
Started Apr 04 02:57:04 PM PDT 24
Finished Apr 04 02:57:05 PM PDT 24
Peak memory 201172 kb
Host smart-9185a196-baa5-463a-8593-6ec74c69310f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405192743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.3405192743
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2240996738
Short name T796
Test name
Test status
Simulation time 514540861 ps
CPU time 1.85 seconds
Started Apr 04 02:57:03 PM PDT 24
Finished Apr 04 02:57:05 PM PDT 24
Peak memory 201172 kb
Host smart-d84ce82b-8746-470d-9bbc-7c3cb6eacffe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240996738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2240996738
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3611395976
Short name T797
Test name
Test status
Simulation time 481121855 ps
CPU time 1.72 seconds
Started Apr 04 02:57:04 PM PDT 24
Finished Apr 04 02:57:06 PM PDT 24
Peak memory 201212 kb
Host smart-e54cc6b9-45ec-4290-b80f-26af5ee21382
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611395976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3611395976
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2897078103
Short name T847
Test name
Test status
Simulation time 464570738 ps
CPU time 1.16 seconds
Started Apr 04 02:56:58 PM PDT 24
Finished Apr 04 02:56:59 PM PDT 24
Peak memory 201220 kb
Host smart-42942434-4b19-4c6c-8adc-84c3682d7fd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897078103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2897078103
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.392467505
Short name T857
Test name
Test status
Simulation time 442573122 ps
CPU time 0.68 seconds
Started Apr 04 02:57:25 PM PDT 24
Finished Apr 04 02:57:26 PM PDT 24
Peak memory 201204 kb
Host smart-0b734a57-a0ff-4af5-baf3-6369b9d25f4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392467505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.392467505
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3357010125
Short name T824
Test name
Test status
Simulation time 450923056 ps
CPU time 0.92 seconds
Started Apr 04 02:57:16 PM PDT 24
Finished Apr 04 02:57:18 PM PDT 24
Peak memory 201236 kb
Host smart-e42e2f4e-57e2-4806-94e6-01e229add96e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357010125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3357010125
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.2976435792
Short name T902
Test name
Test status
Simulation time 496888333 ps
CPU time 0.9 seconds
Started Apr 04 02:57:03 PM PDT 24
Finished Apr 04 02:57:04 PM PDT 24
Peak memory 201204 kb
Host smart-def057ca-6ce4-4708-9fa7-3dba850be581
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976435792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.2976435792
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.619407063
Short name T865
Test name
Test status
Simulation time 352554429 ps
CPU time 1.49 seconds
Started Apr 04 02:57:06 PM PDT 24
Finished Apr 04 02:57:08 PM PDT 24
Peak memory 201184 kb
Host smart-f73d34e5-489a-49a4-ad54-733846926b26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619407063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.619407063
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2027486385
Short name T864
Test name
Test status
Simulation time 508057148 ps
CPU time 2.04 seconds
Started Apr 04 02:56:55 PM PDT 24
Finished Apr 04 02:56:57 PM PDT 24
Peak memory 201268 kb
Host smart-dd634204-8358-43cf-b108-65bfbbe3986f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027486385 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2027486385
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4006027417
Short name T885
Test name
Test status
Simulation time 380378142 ps
CPU time 1.06 seconds
Started Apr 04 02:57:00 PM PDT 24
Finished Apr 04 02:57:01 PM PDT 24
Peak memory 201180 kb
Host smart-18f8f6c1-e06a-43c0-a507-ca84b7ea9204
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006027417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.4006027417
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.2638869924
Short name T880
Test name
Test status
Simulation time 496475443 ps
CPU time 0.85 seconds
Started Apr 04 02:57:00 PM PDT 24
Finished Apr 04 02:57:01 PM PDT 24
Peak memory 201240 kb
Host smart-73376146-224d-4368-8354-efc1248ff9ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638869924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.2638869924
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1188457754
Short name T807
Test name
Test status
Simulation time 4646232209 ps
CPU time 10.81 seconds
Started Apr 04 02:56:55 PM PDT 24
Finished Apr 04 02:57:06 PM PDT 24
Peak memory 201544 kb
Host smart-27ca95fc-66dd-4d97-bae7-aa7789c1baaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188457754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.1188457754
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4272253830
Short name T918
Test name
Test status
Simulation time 868203045 ps
CPU time 1.77 seconds
Started Apr 04 02:57:01 PM PDT 24
Finished Apr 04 02:57:02 PM PDT 24
Peak memory 201508 kb
Host smart-ff06f3ba-42c8-4b51-af23-c5b43c992d66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272253830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.4272253830
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3731778926
Short name T837
Test name
Test status
Simulation time 4543738256 ps
CPU time 4.38 seconds
Started Apr 04 02:57:00 PM PDT 24
Finished Apr 04 02:57:04 PM PDT 24
Peak memory 201400 kb
Host smart-168cc654-8994-42e5-8886-487c53c7f61b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731778926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3731778926
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.3958693336
Short name T882
Test name
Test status
Simulation time 607412836 ps
CPU time 1.44 seconds
Started Apr 04 02:57:03 PM PDT 24
Finished Apr 04 02:57:05 PM PDT 24
Peak memory 201296 kb
Host smart-2b2e90a2-6da2-4f0c-8dd7-bb652f33093f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958693336 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.3958693336
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3202208357
Short name T827
Test name
Test status
Simulation time 560141434 ps
CPU time 0.99 seconds
Started Apr 04 02:57:01 PM PDT 24
Finished Apr 04 02:57:02 PM PDT 24
Peak memory 201236 kb
Host smart-8d1d1eb5-c4f7-4f23-a77d-980a91afbdc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202208357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3202208357
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.4085248068
Short name T818
Test name
Test status
Simulation time 517981899 ps
CPU time 1.86 seconds
Started Apr 04 02:56:59 PM PDT 24
Finished Apr 04 02:57:01 PM PDT 24
Peak memory 201212 kb
Host smart-9c383cbc-b414-4ab1-9bfb-e768239780a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085248068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.4085248068
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1752634041
Short name T55
Test name
Test status
Simulation time 5017760593 ps
CPU time 8.05 seconds
Started Apr 04 02:56:59 PM PDT 24
Finished Apr 04 02:57:07 PM PDT 24
Peak memory 201460 kb
Host smart-43a2ef28-1e5b-403a-a6f3-5dda5a29518a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752634041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.1752634041
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.2632538304
Short name T849
Test name
Test status
Simulation time 469314069 ps
CPU time 3.17 seconds
Started Apr 04 02:56:54 PM PDT 24
Finished Apr 04 02:56:58 PM PDT 24
Peak memory 201444 kb
Host smart-501cfd41-8b7e-462d-9072-e04eb659cb22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632538304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.2632538304
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.515745274
Short name T898
Test name
Test status
Simulation time 4069092452 ps
CPU time 6.02 seconds
Started Apr 04 02:57:00 PM PDT 24
Finished Apr 04 02:57:07 PM PDT 24
Peak memory 201424 kb
Host smart-330de156-246b-46c2-a873-f83d4562083a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515745274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.515745274
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.190025829
Short name T883
Test name
Test status
Simulation time 512877905 ps
CPU time 1.55 seconds
Started Apr 04 02:57:00 PM PDT 24
Finished Apr 04 02:57:02 PM PDT 24
Peak memory 201272 kb
Host smart-744c2aa5-850f-48c6-9d68-631c195777db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190025829 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.190025829
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.3963459049
Short name T100
Test name
Test status
Simulation time 433261070 ps
CPU time 1.02 seconds
Started Apr 04 02:57:03 PM PDT 24
Finished Apr 04 02:57:04 PM PDT 24
Peak memory 201108 kb
Host smart-ea5ae0a8-f4e1-488f-b596-7c679b57708f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963459049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.3963459049
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.4047271589
Short name T810
Test name
Test status
Simulation time 550802206 ps
CPU time 0.94 seconds
Started Apr 04 02:57:01 PM PDT 24
Finished Apr 04 02:57:02 PM PDT 24
Peak memory 201204 kb
Host smart-a0343a93-5db8-482e-9db9-a3bb5a0d1e9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047271589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.4047271589
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3099885174
Short name T821
Test name
Test status
Simulation time 2592740857 ps
CPU time 9.12 seconds
Started Apr 04 02:56:54 PM PDT 24
Finished Apr 04 02:57:03 PM PDT 24
Peak memory 201284 kb
Host smart-63d28fb6-1ae4-4dfe-b148-40d4a5af9763
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099885174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3099885174
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.117201565
Short name T812
Test name
Test status
Simulation time 419146704 ps
CPU time 2.43 seconds
Started Apr 04 02:56:58 PM PDT 24
Finished Apr 04 02:57:00 PM PDT 24
Peak memory 201460 kb
Host smart-97d9eb29-84be-4452-9db9-d6cd7a8bb251
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117201565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.117201565
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1551630499
Short name T878
Test name
Test status
Simulation time 8757577883 ps
CPU time 8.2 seconds
Started Apr 04 02:57:00 PM PDT 24
Finished Apr 04 02:57:08 PM PDT 24
Peak memory 201288 kb
Host smart-fe09606d-63a7-409b-af4f-e167c9749bfa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551630499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1551630499
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1165803041
Short name T907
Test name
Test status
Simulation time 636823824 ps
CPU time 1.67 seconds
Started Apr 04 02:57:17 PM PDT 24
Finished Apr 04 02:57:20 PM PDT 24
Peak memory 201320 kb
Host smart-55945cf8-53b7-4077-8ca4-39025e19d24a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165803041 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1165803041
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2449282273
Short name T113
Test name
Test status
Simulation time 543762946 ps
CPU time 1.99 seconds
Started Apr 04 02:56:56 PM PDT 24
Finished Apr 04 02:56:59 PM PDT 24
Peak memory 201228 kb
Host smart-165e5f0c-d6de-49f5-96b1-d0d8077a7886
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449282273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2449282273
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1162299875
Short name T876
Test name
Test status
Simulation time 390381629 ps
CPU time 0.91 seconds
Started Apr 04 02:56:57 PM PDT 24
Finished Apr 04 02:56:58 PM PDT 24
Peak memory 201244 kb
Host smart-7c7372da-b18c-4a00-a2d7-429d1c71ff51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162299875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1162299875
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2069657884
Short name T53
Test name
Test status
Simulation time 2283383370 ps
CPU time 2.95 seconds
Started Apr 04 02:56:52 PM PDT 24
Finished Apr 04 02:56:56 PM PDT 24
Peak memory 201284 kb
Host smart-5aa60b54-b93c-448b-a223-4f95e36f1a91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069657884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2069657884
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.93342807
Short name T60
Test name
Test status
Simulation time 425818550 ps
CPU time 2.78 seconds
Started Apr 04 02:56:59 PM PDT 24
Finished Apr 04 02:57:02 PM PDT 24
Peak memory 201524 kb
Host smart-129f9a06-3930-4e65-80a4-fcdc54719578
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93342807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.93342807
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1682583633
Short name T887
Test name
Test status
Simulation time 4268365338 ps
CPU time 12.18 seconds
Started Apr 04 02:56:46 PM PDT 24
Finished Apr 04 02:56:58 PM PDT 24
Peak memory 201524 kb
Host smart-f995ff9a-d4e0-451e-9f20-a8391d313614
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682583633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1682583633
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1638221311
Short name T901
Test name
Test status
Simulation time 508770720 ps
CPU time 1.88 seconds
Started Apr 04 02:56:59 PM PDT 24
Finished Apr 04 02:57:01 PM PDT 24
Peak memory 201304 kb
Host smart-381975e0-6a12-4194-b463-30d612b7872f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638221311 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.1638221311
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.446859981
Short name T851
Test name
Test status
Simulation time 470255626 ps
CPU time 1.08 seconds
Started Apr 04 02:57:04 PM PDT 24
Finished Apr 04 02:57:05 PM PDT 24
Peak memory 201236 kb
Host smart-9db1a1da-4263-45eb-ae7f-59690f326fc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446859981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.446859981
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3984468820
Short name T799
Test name
Test status
Simulation time 492075282 ps
CPU time 1.07 seconds
Started Apr 04 02:56:50 PM PDT 24
Finished Apr 04 02:56:52 PM PDT 24
Peak memory 201224 kb
Host smart-b5251ff5-637b-40a9-bfb5-4caab553413f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984468820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3984468820
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2292375476
Short name T826
Test name
Test status
Simulation time 2437243669 ps
CPU time 8.92 seconds
Started Apr 04 02:56:59 PM PDT 24
Finished Apr 04 02:57:08 PM PDT 24
Peak memory 201304 kb
Host smart-f635b5fb-12cd-43b4-b1e1-2e9013213761
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292375476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2292375476
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2840316527
Short name T66
Test name
Test status
Simulation time 436364114 ps
CPU time 3.09 seconds
Started Apr 04 02:57:02 PM PDT 24
Finished Apr 04 02:57:05 PM PDT 24
Peak memory 210732 kb
Host smart-94fe900e-d1c8-4263-a4e4-b7e0c69dfb3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840316527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2840316527
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.862162445
Short name T843
Test name
Test status
Simulation time 8516109064 ps
CPU time 7.47 seconds
Started Apr 04 02:56:53 PM PDT 24
Finished Apr 04 02:57:01 PM PDT 24
Peak memory 201452 kb
Host smart-91307071-1005-4ef9-bbe7-206f5c21b70b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862162445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_int
g_err.862162445
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.2394222264
Short name T748
Test name
Test status
Simulation time 497284334 ps
CPU time 0.88 seconds
Started Apr 04 01:06:34 PM PDT 24
Finished Apr 04 01:06:35 PM PDT 24
Peak memory 201888 kb
Host smart-88d9222c-1bbc-4e8b-a074-f103e1077fc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394222264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.2394222264
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.834654039
Short name T450
Test name
Test status
Simulation time 166137723131 ps
CPU time 93.35 seconds
Started Apr 04 01:06:22 PM PDT 24
Finished Apr 04 01:07:55 PM PDT 24
Peak memory 202328 kb
Host smart-0a23525a-9925-4ac3-8e05-f73bbf4bc398
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834654039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gatin
g.834654039
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3246857110
Short name T243
Test name
Test status
Simulation time 481230188392 ps
CPU time 598.56 seconds
Started Apr 04 01:06:20 PM PDT 24
Finished Apr 04 01:16:19 PM PDT 24
Peak memory 202384 kb
Host smart-82ab9262-5ce6-48dd-9058-9c35bd315d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246857110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3246857110
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1803248998
Short name T691
Test name
Test status
Simulation time 491193586531 ps
CPU time 1068.4 seconds
Started Apr 04 01:06:22 PM PDT 24
Finished Apr 04 01:24:11 PM PDT 24
Peak memory 202248 kb
Host smart-e8992b6b-a2ec-489e-9e9c-b7152cc68207
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803248998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1803248998
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.3520750568
Short name T285
Test name
Test status
Simulation time 482132307003 ps
CPU time 574.73 seconds
Started Apr 04 01:06:21 PM PDT 24
Finished Apr 04 01:15:55 PM PDT 24
Peak memory 202252 kb
Host smart-b1d32562-58f8-44af-a22c-bec592b03960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520750568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3520750568
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.3749328316
Short name T554
Test name
Test status
Simulation time 493279533653 ps
CPU time 145.34 seconds
Started Apr 04 01:06:22 PM PDT 24
Finished Apr 04 01:08:47 PM PDT 24
Peak memory 202324 kb
Host smart-64dfbc66-85af-4376-b6bf-2f78be034772
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749328316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.3749328316
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1003953713
Short name T739
Test name
Test status
Simulation time 256499424910 ps
CPU time 162 seconds
Started Apr 04 01:06:22 PM PDT 24
Finished Apr 04 01:09:04 PM PDT 24
Peak memory 202288 kb
Host smart-352185e3-51b2-4b2b-9666-13d818e96b6b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003953713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1003953713
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2499357928
Short name T539
Test name
Test status
Simulation time 581691006920 ps
CPU time 673.98 seconds
Started Apr 04 01:06:22 PM PDT 24
Finished Apr 04 01:17:36 PM PDT 24
Peak memory 202240 kb
Host smart-0927498e-d219-4b7b-bcbb-12ece82122ad
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499357928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2499357928
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.833868117
Short name T402
Test name
Test status
Simulation time 95884040144 ps
CPU time 457.16 seconds
Started Apr 04 01:06:35 PM PDT 24
Finished Apr 04 01:14:13 PM PDT 24
Peak memory 202588 kb
Host smart-3dcaee05-990d-4a8d-81e1-7c832476ce63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833868117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.833868117
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2643054683
Short name T576
Test name
Test status
Simulation time 27752687570 ps
CPU time 39.78 seconds
Started Apr 04 01:06:36 PM PDT 24
Finished Apr 04 01:07:17 PM PDT 24
Peak memory 202032 kb
Host smart-e11acdfe-817e-42de-9979-9e3c79ba6e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643054683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2643054683
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.174639696
Short name T760
Test name
Test status
Simulation time 5333054519 ps
CPU time 13.85 seconds
Started Apr 04 01:06:34 PM PDT 24
Finished Apr 04 01:06:48 PM PDT 24
Peak memory 202136 kb
Host smart-3f306934-5e0b-424e-bbe6-7df6c0769824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174639696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.174639696
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2978540193
Short name T64
Test name
Test status
Simulation time 4538559030 ps
CPU time 3.49 seconds
Started Apr 04 01:06:33 PM PDT 24
Finished Apr 04 01:06:37 PM PDT 24
Peak memory 217728 kb
Host smart-306bcd3a-4229-4cdb-8e85-94959250426c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978540193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2978540193
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.243785142
Short name T542
Test name
Test status
Simulation time 5669967430 ps
CPU time 10.71 seconds
Started Apr 04 01:06:21 PM PDT 24
Finished Apr 04 01:06:32 PM PDT 24
Peak memory 202032 kb
Host smart-48623b9f-13a9-46df-aafa-5109a60b0f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243785142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.243785142
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2420618811
Short name T728
Test name
Test status
Simulation time 192635846955 ps
CPU time 108.03 seconds
Started Apr 04 01:06:33 PM PDT 24
Finished Apr 04 01:08:21 PM PDT 24
Peak memory 202188 kb
Host smart-0a942c13-c049-4c3b-be46-3666058d7832
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420618811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2420618811
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2867588251
Short name T36
Test name
Test status
Simulation time 26815993001 ps
CPU time 41.54 seconds
Started Apr 04 01:06:35 PM PDT 24
Finished Apr 04 01:07:17 PM PDT 24
Peak memory 210588 kb
Host smart-cf7f3501-14ec-41a1-ae2d-9f3bec3b38c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867588251 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2867588251
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.193577790
Short name T616
Test name
Test status
Simulation time 505413796 ps
CPU time 1.81 seconds
Started Apr 04 01:06:51 PM PDT 24
Finished Apr 04 01:06:54 PM PDT 24
Peak memory 201860 kb
Host smart-0e3fd8c3-cb02-49ad-888e-8dd51bed754a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193577790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.193577790
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1990444095
Short name T685
Test name
Test status
Simulation time 163689283819 ps
CPU time 58.37 seconds
Started Apr 04 01:06:34 PM PDT 24
Finished Apr 04 01:07:33 PM PDT 24
Peak memory 202340 kb
Host smart-9def8a2d-5376-45d3-8fab-6026fcc51800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990444095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1990444095
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.1695901648
Short name T766
Test name
Test status
Simulation time 171264292821 ps
CPU time 56.94 seconds
Started Apr 04 01:06:36 PM PDT 24
Finished Apr 04 01:07:34 PM PDT 24
Peak memory 202228 kb
Host smart-2fa8bae6-9e76-4eb1-bd35-02284f1feb20
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695901648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.1695901648
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.3509674253
Short name T603
Test name
Test status
Simulation time 171195510893 ps
CPU time 172 seconds
Started Apr 04 01:06:35 PM PDT 24
Finished Apr 04 01:09:27 PM PDT 24
Peak memory 202196 kb
Host smart-107b77ef-411e-4ab1-8ebf-825a52ad5c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509674253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3509674253
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2195788830
Short name T620
Test name
Test status
Simulation time 164906016796 ps
CPU time 100.81 seconds
Started Apr 04 01:06:34 PM PDT 24
Finished Apr 04 01:08:15 PM PDT 24
Peak memory 202256 kb
Host smart-4d2232ac-2285-41f3-950d-e5f18bafcd83
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195788830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2195788830
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3982879383
Short name T216
Test name
Test status
Simulation time 362908039273 ps
CPU time 762.5 seconds
Started Apr 04 01:06:36 PM PDT 24
Finished Apr 04 01:19:20 PM PDT 24
Peak memory 202336 kb
Host smart-bd393893-ad53-4ad1-b6d2-12047f7c133d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982879383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3982879383
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1448842252
Short name T729
Test name
Test status
Simulation time 385074407294 ps
CPU time 829.06 seconds
Started Apr 04 01:06:34 PM PDT 24
Finished Apr 04 01:20:23 PM PDT 24
Peak memory 202156 kb
Host smart-e0084693-331a-4aba-9511-064941e0c1bb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448842252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1448842252
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.3268533336
Short name T7
Test name
Test status
Simulation time 88876473265 ps
CPU time 454.74 seconds
Started Apr 04 01:06:51 PM PDT 24
Finished Apr 04 01:14:25 PM PDT 24
Peak memory 202652 kb
Host smart-6f000a6b-d2a8-4f27-9d45-a60e195b8ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268533336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.3268533336
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2617382402
Short name T411
Test name
Test status
Simulation time 39406739621 ps
CPU time 46.38 seconds
Started Apr 04 01:06:51 PM PDT 24
Finished Apr 04 01:07:39 PM PDT 24
Peak memory 202004 kb
Host smart-ed367c16-145c-4591-ac78-4f630071d973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617382402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2617382402
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2699400902
Short name T481
Test name
Test status
Simulation time 4770786971 ps
CPU time 2.76 seconds
Started Apr 04 01:06:51 PM PDT 24
Finished Apr 04 01:06:55 PM PDT 24
Peak memory 202016 kb
Host smart-0bcea8e5-71cc-40f5-820c-752cebed166f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699400902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2699400902
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.239581681
Short name T72
Test name
Test status
Simulation time 4434684848 ps
CPU time 11.06 seconds
Started Apr 04 01:06:50 PM PDT 24
Finished Apr 04 01:07:02 PM PDT 24
Peak memory 217780 kb
Host smart-7b1e98ab-2157-4032-9e38-07f4cab8f72a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239581681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.239581681
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.1501527779
Short name T421
Test name
Test status
Simulation time 5782260544 ps
CPU time 4.51 seconds
Started Apr 04 01:06:35 PM PDT 24
Finished Apr 04 01:06:40 PM PDT 24
Peak memory 202064 kb
Host smart-202e98d0-7cc9-486a-b0d0-a9b62a1495d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501527779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1501527779
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.2516387579
Short name T484
Test name
Test status
Simulation time 886450243669 ps
CPU time 437.2 seconds
Started Apr 04 01:06:50 PM PDT 24
Finished Apr 04 01:14:08 PM PDT 24
Peak memory 210784 kb
Host smart-77a25b95-fdc6-4053-a2b2-8fb5c771e1fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516387579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
2516387579
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.725666093
Short name T405
Test name
Test status
Simulation time 55456381063 ps
CPU time 146.7 seconds
Started Apr 04 01:06:51 PM PDT 24
Finished Apr 04 01:09:19 PM PDT 24
Peak memory 210852 kb
Host smart-42f8d801-f337-40e8-a647-4c4de82f7e4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725666093 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.725666093
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3029137864
Short name T692
Test name
Test status
Simulation time 367360386 ps
CPU time 0.82 seconds
Started Apr 04 01:10:12 PM PDT 24
Finished Apr 04 01:10:13 PM PDT 24
Peak memory 201968 kb
Host smart-f1356638-c3c0-43ff-8872-aa661c983f86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029137864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3029137864
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.3093177498
Short name T259
Test name
Test status
Simulation time 322369120125 ps
CPU time 135.2 seconds
Started Apr 04 01:10:02 PM PDT 24
Finished Apr 04 01:12:17 PM PDT 24
Peak memory 202228 kb
Host smart-14e70713-d779-4a1f-ac93-16041c881c85
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093177498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.3093177498
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.1413386752
Short name T244
Test name
Test status
Simulation time 162616309572 ps
CPU time 107.07 seconds
Started Apr 04 01:10:00 PM PDT 24
Finished Apr 04 01:11:48 PM PDT 24
Peak memory 202224 kb
Host smart-f29784fb-ab6b-4612-b251-d489f91ee6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413386752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.1413386752
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.2684586663
Short name T549
Test name
Test status
Simulation time 166121937498 ps
CPU time 106.81 seconds
Started Apr 04 01:09:51 PM PDT 24
Finished Apr 04 01:11:38 PM PDT 24
Peak memory 202216 kb
Host smart-797a3aad-4e75-4a9e-b3d4-3a7c138e7aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684586663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.2684586663
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3912846423
Short name T10
Test name
Test status
Simulation time 495210525551 ps
CPU time 277.12 seconds
Started Apr 04 01:09:51 PM PDT 24
Finished Apr 04 01:14:28 PM PDT 24
Peak memory 202156 kb
Host smart-42011006-f343-40cb-a0ba-2428ce8c7fe8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912846423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.3912846423
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.2224754308
Short name T286
Test name
Test status
Simulation time 320572781818 ps
CPU time 384.92 seconds
Started Apr 04 01:09:51 PM PDT 24
Finished Apr 04 01:16:16 PM PDT 24
Peak memory 202272 kb
Host smart-c8a7b90b-119c-4582-b991-4bc9853f1a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224754308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.2224754308
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.984227900
Short name T475
Test name
Test status
Simulation time 500844555488 ps
CPU time 1178.54 seconds
Started Apr 04 01:09:50 PM PDT 24
Finished Apr 04 01:29:29 PM PDT 24
Peak memory 202120 kb
Host smart-0c56a424-6970-40db-bd9b-29fed9a9417c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=984227900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fixe
d.984227900
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.2651729370
Short name T270
Test name
Test status
Simulation time 569143184222 ps
CPU time 1200.53 seconds
Started Apr 04 01:09:50 PM PDT 24
Finished Apr 04 01:29:51 PM PDT 24
Peak memory 202276 kb
Host smart-4d861e7d-3bdc-4017-838c-ed2943ed2717
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651729370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.2651729370
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.157448296
Short name T671
Test name
Test status
Simulation time 406551379986 ps
CPU time 911.2 seconds
Started Apr 04 01:10:01 PM PDT 24
Finished Apr 04 01:25:13 PM PDT 24
Peak memory 202224 kb
Host smart-f37df4a3-bf0d-4004-9026-ff7d0c48e399
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157448296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.157448296
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.3638426421
Short name T342
Test name
Test status
Simulation time 82586797761 ps
CPU time 262.6 seconds
Started Apr 04 01:10:01 PM PDT 24
Finished Apr 04 01:14:23 PM PDT 24
Peak memory 202548 kb
Host smart-679e1dca-42fb-48cc-8e28-4c8cfe591905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638426421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3638426421
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.690639460
Short name T409
Test name
Test status
Simulation time 43708029824 ps
CPU time 25.37 seconds
Started Apr 04 01:10:02 PM PDT 24
Finished Apr 04 01:10:27 PM PDT 24
Peak memory 201988 kb
Host smart-d429b939-7398-4355-951d-ee990f9ccefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690639460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.690639460
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2179032122
Short name T649
Test name
Test status
Simulation time 3183377752 ps
CPU time 2.46 seconds
Started Apr 04 01:10:01 PM PDT 24
Finished Apr 04 01:10:04 PM PDT 24
Peak memory 202052 kb
Host smart-55c5eef9-c2eb-4d62-9f8b-a8a58cbdc424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179032122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2179032122
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.1889095924
Short name T380
Test name
Test status
Simulation time 5447877475 ps
CPU time 5.03 seconds
Started Apr 04 01:09:52 PM PDT 24
Finished Apr 04 01:09:57 PM PDT 24
Peak memory 201992 kb
Host smart-2cdda426-401b-48c3-afee-bccc79c12c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889095924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1889095924
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3669546587
Short name T39
Test name
Test status
Simulation time 218317731146 ps
CPU time 243.91 seconds
Started Apr 04 01:10:13 PM PDT 24
Finished Apr 04 01:14:17 PM PDT 24
Peak memory 218488 kb
Host smart-0a5e41ce-bc1e-4ccd-bce0-955e384e1431
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669546587 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3669546587
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.1656869703
Short name T699
Test name
Test status
Simulation time 373989189 ps
CPU time 1.48 seconds
Started Apr 04 01:10:41 PM PDT 24
Finished Apr 04 01:10:43 PM PDT 24
Peak memory 201976 kb
Host smart-56ca6586-cdbb-4b68-973c-02f1996892b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656869703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1656869703
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.229943888
Short name T697
Test name
Test status
Simulation time 161265005924 ps
CPU time 96.76 seconds
Started Apr 04 01:10:32 PM PDT 24
Finished Apr 04 01:12:09 PM PDT 24
Peak memory 202332 kb
Host smart-4c7c7e3b-1990-4624-a726-c5c7ee40a71e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229943888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gati
ng.229943888
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3432331558
Short name T419
Test name
Test status
Simulation time 493584359885 ps
CPU time 607.47 seconds
Started Apr 04 01:10:32 PM PDT 24
Finished Apr 04 01:20:39 PM PDT 24
Peak memory 202284 kb
Host smart-f99977da-d142-4c0e-a349-7eabf54a481e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432331558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3432331558
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.1320276140
Short name T197
Test name
Test status
Simulation time 326068676195 ps
CPU time 764.86 seconds
Started Apr 04 01:10:22 PM PDT 24
Finished Apr 04 01:23:08 PM PDT 24
Peak memory 202204 kb
Host smart-a504bbd7-ec29-49ec-8aa3-3c2a5eac2d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320276140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1320276140
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.315336574
Short name T386
Test name
Test status
Simulation time 497237827740 ps
CPU time 303.33 seconds
Started Apr 04 01:10:32 PM PDT 24
Finished Apr 04 01:15:36 PM PDT 24
Peak memory 202236 kb
Host smart-eaa5646f-4caa-493d-99a0-9bc6d419f2cd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=315336574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fixe
d.315336574
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.998588467
Short name T302
Test name
Test status
Simulation time 535637632768 ps
CPU time 295.75 seconds
Started Apr 04 01:10:31 PM PDT 24
Finished Apr 04 01:15:27 PM PDT 24
Peak memory 202280 kb
Host smart-6ff61185-17f3-47a1-a3d2-ead140534f1f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998588467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_
wakeup.998588467
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.2013575355
Short name T746
Test name
Test status
Simulation time 398311731140 ps
CPU time 340.54 seconds
Started Apr 04 01:10:32 PM PDT 24
Finished Apr 04 01:16:12 PM PDT 24
Peak memory 202224 kb
Host smart-5be18c29-cbcc-4d53-bef8-87bb7680373d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013575355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.2013575355
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3530009839
Short name T478
Test name
Test status
Simulation time 63885367760 ps
CPU time 361.61 seconds
Started Apr 04 01:10:33 PM PDT 24
Finished Apr 04 01:16:35 PM PDT 24
Peak memory 202560 kb
Host smart-c81586e9-5f79-44ef-ac84-eaa4805c69dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530009839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3530009839
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.2244203435
Short name T529
Test name
Test status
Simulation time 30264021221 ps
CPU time 17.92 seconds
Started Apr 04 01:10:32 PM PDT 24
Finished Apr 04 01:10:50 PM PDT 24
Peak memory 202028 kb
Host smart-569c0eab-d733-45a1-b940-223a9e6007f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244203435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2244203435
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1109533903
Short name T461
Test name
Test status
Simulation time 4664152883 ps
CPU time 5.93 seconds
Started Apr 04 01:10:31 PM PDT 24
Finished Apr 04 01:10:37 PM PDT 24
Peak memory 201980 kb
Host smart-1ef5b997-cda3-478b-a628-4641160cf58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109533903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1109533903
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.914564166
Short name T429
Test name
Test status
Simulation time 5974555762 ps
CPU time 4.36 seconds
Started Apr 04 01:10:23 PM PDT 24
Finished Apr 04 01:10:28 PM PDT 24
Peak memory 202072 kb
Host smart-2b094756-3367-4c91-95f1-8c17e4a1b32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914564166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.914564166
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.1165869164
Short name T283
Test name
Test status
Simulation time 204698630791 ps
CPU time 432.95 seconds
Started Apr 04 01:10:43 PM PDT 24
Finished Apr 04 01:17:56 PM PDT 24
Peak memory 202284 kb
Host smart-0ab6f558-1577-4e87-8a07-05d00a7df7b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165869164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.1165869164
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.342993113
Short name T451
Test name
Test status
Simulation time 439934597 ps
CPU time 0.85 seconds
Started Apr 04 01:11:13 PM PDT 24
Finished Apr 04 01:11:14 PM PDT 24
Peak memory 201872 kb
Host smart-084e3fb2-ef2b-4ac8-a607-17ab459a1cc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342993113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.342993113
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.803158542
Short name T523
Test name
Test status
Simulation time 333150470292 ps
CPU time 67.4 seconds
Started Apr 04 01:10:42 PM PDT 24
Finished Apr 04 01:11:50 PM PDT 24
Peak memory 202416 kb
Host smart-84d10db5-c01f-4b4f-9cff-b4310aa1cb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803158542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.803158542
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.4129305198
Short name T374
Test name
Test status
Simulation time 330918831351 ps
CPU time 754.22 seconds
Started Apr 04 01:10:44 PM PDT 24
Finished Apr 04 01:23:18 PM PDT 24
Peak memory 202216 kb
Host smart-ef43c219-57cd-4de2-bd56-17909c728347
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129305198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.4129305198
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.3237575135
Short name T279
Test name
Test status
Simulation time 164356618383 ps
CPU time 98.83 seconds
Started Apr 04 01:10:40 PM PDT 24
Finished Apr 04 01:12:20 PM PDT 24
Peak memory 202304 kb
Host smart-575a9e6d-8467-4261-acfa-70d3d74af6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237575135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.3237575135
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1656037494
Short name T593
Test name
Test status
Simulation time 167638470170 ps
CPU time 396.55 seconds
Started Apr 04 01:10:42 PM PDT 24
Finished Apr 04 01:17:18 PM PDT 24
Peak memory 202188 kb
Host smart-35d9d555-c104-4464-8624-8bb3d28e03b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656037494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1656037494
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.2943771249
Short name T432
Test name
Test status
Simulation time 582526190322 ps
CPU time 319.28 seconds
Started Apr 04 01:10:46 PM PDT 24
Finished Apr 04 01:16:06 PM PDT 24
Peak memory 202264 kb
Host smart-2d091981-da81-4c44-a718-aa69e58fdc84
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943771249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.2943771249
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.3484899855
Short name T418
Test name
Test status
Simulation time 32570734780 ps
CPU time 75.16 seconds
Started Apr 04 01:11:00 PM PDT 24
Finished Apr 04 01:12:15 PM PDT 24
Peak memory 202024 kb
Host smart-65b79d11-df59-4fb3-a36f-199a909571c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484899855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.3484899855
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.250943945
Short name T700
Test name
Test status
Simulation time 3436142110 ps
CPU time 9.03 seconds
Started Apr 04 01:11:00 PM PDT 24
Finished Apr 04 01:11:09 PM PDT 24
Peak memory 202136 kb
Host smart-e59a7893-87fc-4ed4-a926-d44767695e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250943945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.250943945
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.2105469029
Short name T364
Test name
Test status
Simulation time 6014019814 ps
CPU time 14.55 seconds
Started Apr 04 01:10:42 PM PDT 24
Finished Apr 04 01:10:57 PM PDT 24
Peak memory 202072 kb
Host smart-7c8e7813-0bdb-48f5-90b4-1627487a401c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105469029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.2105469029
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1926747230
Short name T281
Test name
Test status
Simulation time 135477122947 ps
CPU time 211.69 seconds
Started Apr 04 01:11:02 PM PDT 24
Finished Apr 04 01:14:34 PM PDT 24
Peak memory 211048 kb
Host smart-6cc75796-3ab4-47a1-821a-70fc6dd8d7ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926747230 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1926747230
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3171149026
Short name T575
Test name
Test status
Simulation time 165713540114 ps
CPU time 101.91 seconds
Started Apr 04 01:11:25 PM PDT 24
Finished Apr 04 01:13:07 PM PDT 24
Peak memory 202180 kb
Host smart-34d4062b-9c8d-401c-88f0-55acff4738d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171149026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3171149026
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.744322205
Short name T467
Test name
Test status
Simulation time 499436087735 ps
CPU time 1179.29 seconds
Started Apr 04 01:11:15 PM PDT 24
Finished Apr 04 01:30:55 PM PDT 24
Peak memory 202172 kb
Host smart-5e0b331e-5bf1-4151-8e33-2a4dfd8bbed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744322205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.744322205
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.286908590
Short name T611
Test name
Test status
Simulation time 318088160453 ps
CPU time 188.46 seconds
Started Apr 04 01:11:15 PM PDT 24
Finished Apr 04 01:14:23 PM PDT 24
Peak memory 202220 kb
Host smart-b9c0acbc-94f6-4acd-807b-4b36dd8de25d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=286908590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrup
t_fixed.286908590
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.4140571486
Short name T222
Test name
Test status
Simulation time 167532928209 ps
CPU time 66.48 seconds
Started Apr 04 01:11:14 PM PDT 24
Finished Apr 04 01:12:21 PM PDT 24
Peak memory 202244 kb
Host smart-f6f7b4e9-43ca-4656-bd3c-d9823f1d18dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140571486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.4140571486
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1084771536
Short name T727
Test name
Test status
Simulation time 329894420687 ps
CPU time 504.04 seconds
Started Apr 04 01:11:14 PM PDT 24
Finished Apr 04 01:19:38 PM PDT 24
Peak memory 202348 kb
Host smart-cdce072e-aaae-4561-8a61-3314ec6fbc9b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084771536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1084771536
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2628039696
Short name T684
Test name
Test status
Simulation time 206578436602 ps
CPU time 178.32 seconds
Started Apr 04 01:11:28 PM PDT 24
Finished Apr 04 01:14:27 PM PDT 24
Peak memory 202176 kb
Host smart-fc6723a6-271c-4740-8c5f-e1c790ec5f47
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628039696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2628039696
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.4246778139
Short name T565
Test name
Test status
Simulation time 24203363268 ps
CPU time 60.55 seconds
Started Apr 04 01:11:28 PM PDT 24
Finished Apr 04 01:12:29 PM PDT 24
Peak memory 201984 kb
Host smart-835b52bd-d78c-41e8-b894-39a8ba2d993a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246778139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.4246778139
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2555087139
Short name T703
Test name
Test status
Simulation time 4177352331 ps
CPU time 10.35 seconds
Started Apr 04 01:11:28 PM PDT 24
Finished Apr 04 01:11:39 PM PDT 24
Peak memory 202016 kb
Host smart-7ff8ed93-424f-44f4-8714-29fb792f2f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555087139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2555087139
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.113711757
Short name T546
Test name
Test status
Simulation time 6085732549 ps
CPU time 17.12 seconds
Started Apr 04 01:11:14 PM PDT 24
Finished Apr 04 01:11:32 PM PDT 24
Peak memory 201956 kb
Host smart-a1138d8a-e81e-4088-904b-06b50a8ec151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113711757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.113711757
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1203732357
Short name T29
Test name
Test status
Simulation time 451732808630 ps
CPU time 1052.58 seconds
Started Apr 04 01:11:34 PM PDT 24
Finished Apr 04 01:29:07 PM PDT 24
Peak memory 202324 kb
Host smart-211aa89c-c411-4d66-889c-8868fb2eebb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203732357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1203732357
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.1916749776
Short name T521
Test name
Test status
Simulation time 494206705 ps
CPU time 1.18 seconds
Started Apr 04 01:12:07 PM PDT 24
Finished Apr 04 01:12:08 PM PDT 24
Peak memory 201968 kb
Host smart-981bcf37-81b4-4dbc-8c29-ce43469ccabf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916749776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1916749776
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3363941273
Short name T199
Test name
Test status
Simulation time 162580090150 ps
CPU time 349.59 seconds
Started Apr 04 01:11:57 PM PDT 24
Finished Apr 04 01:17:47 PM PDT 24
Peak memory 202260 kb
Host smart-e0619f39-fb10-46e9-8eef-d067782185f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363941273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3363941273
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.687583017
Short name T638
Test name
Test status
Simulation time 199772855939 ps
CPU time 461.27 seconds
Started Apr 04 01:11:57 PM PDT 24
Finished Apr 04 01:19:38 PM PDT 24
Peak memory 202100 kb
Host smart-568ae3ab-77d4-413e-86bc-d4f6bb5cc3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687583017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.687583017
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3331463542
Short name T204
Test name
Test status
Simulation time 495977742445 ps
CPU time 556.34 seconds
Started Apr 04 01:11:44 PM PDT 24
Finished Apr 04 01:21:01 PM PDT 24
Peak memory 202272 kb
Host smart-17fe2d84-8045-46eb-ba35-777783656dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331463542 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3331463542
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.2421870628
Short name T26
Test name
Test status
Simulation time 492226451214 ps
CPU time 1179.03 seconds
Started Apr 04 01:11:49 PM PDT 24
Finished Apr 04 01:31:29 PM PDT 24
Peak memory 202236 kb
Host smart-c5573ef7-930b-4155-901e-750a740acd5d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421870628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.2421870628
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.2382688302
Short name T126
Test name
Test status
Simulation time 166286419694 ps
CPU time 371.27 seconds
Started Apr 04 01:11:49 PM PDT 24
Finished Apr 04 01:18:01 PM PDT 24
Peak memory 202304 kb
Host smart-b572b580-6b2c-442f-91dc-a4f082753cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382688302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.2382688302
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.3387128664
Short name T504
Test name
Test status
Simulation time 323190966880 ps
CPU time 800.87 seconds
Started Apr 04 01:11:49 PM PDT 24
Finished Apr 04 01:25:10 PM PDT 24
Peak memory 202240 kb
Host smart-add564cc-88cf-4345-ad3b-7409bb93561c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387128664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.3387128664
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2438603746
Short name T190
Test name
Test status
Simulation time 187133962107 ps
CPU time 431.72 seconds
Started Apr 04 01:11:46 PM PDT 24
Finished Apr 04 01:18:58 PM PDT 24
Peak memory 202324 kb
Host smart-f4a93d9b-c8e8-468e-95d2-97e8627e15e1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438603746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2438603746
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3889996109
Short name T389
Test name
Test status
Simulation time 617857210292 ps
CPU time 378.26 seconds
Started Apr 04 01:11:45 PM PDT 24
Finished Apr 04 01:18:04 PM PDT 24
Peak memory 202236 kb
Host smart-12cb5765-385c-42a4-9434-9ddc662cc918
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889996109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.3889996109
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3521968006
Short name T648
Test name
Test status
Simulation time 78065871100 ps
CPU time 306.74 seconds
Started Apr 04 01:11:59 PM PDT 24
Finished Apr 04 01:17:06 PM PDT 24
Peak memory 202512 kb
Host smart-1406ab6f-8568-4546-87c8-d17504974dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521968006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3521968006
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.4172078285
Short name T604
Test name
Test status
Simulation time 32179994548 ps
CPU time 11.28 seconds
Started Apr 04 01:11:57 PM PDT 24
Finished Apr 04 01:12:08 PM PDT 24
Peak memory 201948 kb
Host smart-a7c46774-0283-4c99-9d0f-7d652dcb44c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172078285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.4172078285
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.3341167382
Short name T787
Test name
Test status
Simulation time 4357229112 ps
CPU time 10.53 seconds
Started Apr 04 01:11:57 PM PDT 24
Finished Apr 04 01:12:08 PM PDT 24
Peak memory 202080 kb
Host smart-9d324083-cf72-42ba-b388-ed7579ec3cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341167382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3341167382
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.130343270
Short name T502
Test name
Test status
Simulation time 6131319138 ps
CPU time 16.86 seconds
Started Apr 04 01:11:45 PM PDT 24
Finished Apr 04 01:12:02 PM PDT 24
Peak memory 202020 kb
Host smart-a7b02978-524a-4c14-8b0c-4d353fbe2b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130343270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.130343270
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.811816030
Short name T88
Test name
Test status
Simulation time 89482861274 ps
CPU time 212.65 seconds
Started Apr 04 01:11:59 PM PDT 24
Finished Apr 04 01:15:32 PM PDT 24
Peak memory 218716 kb
Host smart-48931901-259c-4662-827e-fdcb0c301115
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811816030 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.811816030
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2924952133
Short name T180
Test name
Test status
Simulation time 432808252 ps
CPU time 0.88 seconds
Started Apr 04 01:12:31 PM PDT 24
Finished Apr 04 01:12:32 PM PDT 24
Peak memory 201900 kb
Host smart-cc282a12-13ba-40de-b052-1cd97d1e82fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924952133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2924952133
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3394914492
Short name T28
Test name
Test status
Simulation time 387489032998 ps
CPU time 513.27 seconds
Started Apr 04 01:12:17 PM PDT 24
Finished Apr 04 01:20:51 PM PDT 24
Peak memory 202340 kb
Host smart-5841594c-8468-44f9-ad3e-7ba6c03b0699
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394914492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3394914492
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2933242679
Short name T496
Test name
Test status
Simulation time 522847694275 ps
CPU time 725.21 seconds
Started Apr 04 01:12:16 PM PDT 24
Finished Apr 04 01:24:22 PM PDT 24
Peak memory 202156 kb
Host smart-f61f531a-c0ec-4674-ac65-12c1b1492d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933242679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2933242679
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1847595833
Short name T11
Test name
Test status
Simulation time 329583732378 ps
CPU time 179.52 seconds
Started Apr 04 01:12:17 PM PDT 24
Finished Apr 04 01:15:16 PM PDT 24
Peak memory 202204 kb
Host smart-f1316e95-83b9-4de1-94d3-aaebd70a96ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847595833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1847595833
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.3285927019
Short name T444
Test name
Test status
Simulation time 321830407296 ps
CPU time 695.55 seconds
Started Apr 04 01:12:17 PM PDT 24
Finished Apr 04 01:23:53 PM PDT 24
Peak memory 202112 kb
Host smart-22f77655-3939-42ee-954e-ff0f7f7d0fe4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285927019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.3285927019
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.1599121963
Short name T675
Test name
Test status
Simulation time 325903518818 ps
CPU time 205.58 seconds
Started Apr 04 01:12:17 PM PDT 24
Finished Apr 04 01:15:43 PM PDT 24
Peak memory 202196 kb
Host smart-d9983f49-a21e-4dae-88b2-8506ec39ea4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599121963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.1599121963
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1194250392
Short name T683
Test name
Test status
Simulation time 162895800505 ps
CPU time 83.28 seconds
Started Apr 04 01:12:18 PM PDT 24
Finished Apr 04 01:13:41 PM PDT 24
Peak memory 202272 kb
Host smart-4afaa1f8-1e1d-4dcc-bd63-fd2b78de28b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194250392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1194250392
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.2830553318
Short name T235
Test name
Test status
Simulation time 176964285422 ps
CPU time 379.6 seconds
Started Apr 04 01:12:18 PM PDT 24
Finished Apr 04 01:18:37 PM PDT 24
Peak memory 202300 kb
Host smart-c96b0a99-1b00-44ca-8557-a5b7b9a71788
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830553318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.2830553318
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.2486885908
Short name T634
Test name
Test status
Simulation time 415757168810 ps
CPU time 446.92 seconds
Started Apr 04 01:12:17 PM PDT 24
Finished Apr 04 01:19:45 PM PDT 24
Peak memory 202292 kb
Host smart-4302da8f-f1a6-4d1e-a35c-a9332f09ad02
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486885908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.2486885908
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.4061781088
Short name T673
Test name
Test status
Simulation time 87240831022 ps
CPU time 345.98 seconds
Started Apr 04 01:12:32 PM PDT 24
Finished Apr 04 01:18:18 PM PDT 24
Peak memory 202608 kb
Host smart-03e37527-c52b-4de0-96a7-51a1509ee7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061781088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.4061781088
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1856918664
Short name T753
Test name
Test status
Simulation time 26101054699 ps
CPU time 54 seconds
Started Apr 04 01:12:32 PM PDT 24
Finished Apr 04 01:13:26 PM PDT 24
Peak memory 202036 kb
Host smart-2545b378-9997-472f-8556-9c66b589b149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856918664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1856918664
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.2270545861
Short name T472
Test name
Test status
Simulation time 3888878952 ps
CPU time 9.86 seconds
Started Apr 04 01:12:16 PM PDT 24
Finished Apr 04 01:12:26 PM PDT 24
Peak memory 202068 kb
Host smart-adc894da-a483-4e1e-94a1-f48ad9db9c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270545861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.2270545861
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.2954562899
Short name T617
Test name
Test status
Simulation time 6033421307 ps
CPU time 4.05 seconds
Started Apr 04 01:12:08 PM PDT 24
Finished Apr 04 01:12:12 PM PDT 24
Peak memory 202072 kb
Host smart-b9edae02-c3e9-45b9-a47c-8903688af565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954562899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.2954562899
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.331603820
Short name T362
Test name
Test status
Simulation time 85534245074 ps
CPU time 202.37 seconds
Started Apr 04 01:12:31 PM PDT 24
Finished Apr 04 01:15:53 PM PDT 24
Peak memory 202112 kb
Host smart-a9a2d3e1-9067-4984-a462-a0c813ed6118
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331603820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
331603820
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.4233809494
Short name T327
Test name
Test status
Simulation time 26377506637 ps
CPU time 133.5 seconds
Started Apr 04 01:12:33 PM PDT 24
Finished Apr 04 01:14:47 PM PDT 24
Peak memory 210892 kb
Host smart-bccd272d-1e66-44d7-b960-90e7c3963010
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233809494 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.4233809494
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.4076037752
Short name T682
Test name
Test status
Simulation time 502111480 ps
CPU time 1.13 seconds
Started Apr 04 01:12:54 PM PDT 24
Finished Apr 04 01:12:55 PM PDT 24
Peak memory 201940 kb
Host smart-84cc2bce-1fda-4ffe-94f4-f231755fb031
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076037752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.4076037752
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.297965134
Short name T581
Test name
Test status
Simulation time 160665110262 ps
CPU time 173.37 seconds
Started Apr 04 01:12:54 PM PDT 24
Finished Apr 04 01:15:47 PM PDT 24
Peak memory 202328 kb
Host smart-10bdda0b-1129-4d1d-b894-d25edda0468c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297965134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gati
ng.297965134
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.2888534527
Short name T642
Test name
Test status
Simulation time 162151154845 ps
CPU time 366.4 seconds
Started Apr 04 01:12:53 PM PDT 24
Finished Apr 04 01:18:59 PM PDT 24
Peak memory 202212 kb
Host smart-5c45b3ee-e583-451d-8cc2-0988179b889c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888534527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.2888534527
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1529329395
Short name T239
Test name
Test status
Simulation time 156906211532 ps
CPU time 374.25 seconds
Started Apr 04 01:12:43 PM PDT 24
Finished Apr 04 01:18:57 PM PDT 24
Peak memory 202320 kb
Host smart-86ee3fac-719b-4409-a078-72999c1f8992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529329395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1529329395
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.4110600458
Short name T446
Test name
Test status
Simulation time 161209913378 ps
CPU time 374.49 seconds
Started Apr 04 01:12:43 PM PDT 24
Finished Apr 04 01:18:58 PM PDT 24
Peak memory 202300 kb
Host smart-4cfcc3d4-2045-41f8-9623-e88e6c308769
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110600458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.4110600458
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.1384903140
Short name T319
Test name
Test status
Simulation time 333415028229 ps
CPU time 133.98 seconds
Started Apr 04 01:12:32 PM PDT 24
Finished Apr 04 01:14:46 PM PDT 24
Peak memory 202240 kb
Host smart-ac29077b-fe70-4e1e-a48f-f90599e6aa6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384903140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1384903140
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.3245339563
Short name T544
Test name
Test status
Simulation time 167987409404 ps
CPU time 401.6 seconds
Started Apr 04 01:12:43 PM PDT 24
Finished Apr 04 01:19:25 PM PDT 24
Peak memory 202224 kb
Host smart-06471912-2133-4fa7-b809-ac30da03df56
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245339563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.3245339563
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1616195235
Short name T788
Test name
Test status
Simulation time 199648946702 ps
CPU time 133.58 seconds
Started Apr 04 01:12:44 PM PDT 24
Finished Apr 04 01:14:58 PM PDT 24
Peak memory 202336 kb
Host smart-a40a7963-5d41-406c-b952-1a9574538bda
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616195235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1616195235
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.2673425860
Short name T630
Test name
Test status
Simulation time 609683510130 ps
CPU time 342.96 seconds
Started Apr 04 01:12:54 PM PDT 24
Finished Apr 04 01:18:37 PM PDT 24
Peak memory 202228 kb
Host smart-510aa7fe-94ff-4f32-954c-81f5582029cb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673425860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.2673425860
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.2900509573
Short name T157
Test name
Test status
Simulation time 109405964298 ps
CPU time 416.97 seconds
Started Apr 04 01:12:54 PM PDT 24
Finished Apr 04 01:19:51 PM PDT 24
Peak memory 202632 kb
Host smart-4341851b-1f21-40a1-af48-fefa94806fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900509573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.2900509573
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2002524363
Short name T179
Test name
Test status
Simulation time 26131203200 ps
CPU time 21.04 seconds
Started Apr 04 01:12:55 PM PDT 24
Finished Apr 04 01:13:16 PM PDT 24
Peak memory 202096 kb
Host smart-1f91fcdf-dc57-4be3-93fe-3d59680b8453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002524363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2002524363
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.3709872514
Short name T462
Test name
Test status
Simulation time 2927412592 ps
CPU time 2.3 seconds
Started Apr 04 01:12:53 PM PDT 24
Finished Apr 04 01:12:55 PM PDT 24
Peak memory 201920 kb
Host smart-f824af9c-e01e-42ef-b747-7c80f7d34960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709872514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.3709872514
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.2916628073
Short name T573
Test name
Test status
Simulation time 5639859977 ps
CPU time 7.55 seconds
Started Apr 04 01:12:30 PM PDT 24
Finished Apr 04 01:12:38 PM PDT 24
Peak memory 202004 kb
Host smart-877744ff-2fb3-444c-9c52-530b6e4f340c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916628073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.2916628073
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.427015172
Short name T225
Test name
Test status
Simulation time 331180526823 ps
CPU time 95.46 seconds
Started Apr 04 01:12:53 PM PDT 24
Finished Apr 04 01:14:29 PM PDT 24
Peak memory 202204 kb
Host smart-71dfa94a-6115-4abf-af49-9cc0644a4fcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427015172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
427015172
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2514777726
Short name T15
Test name
Test status
Simulation time 138381069422 ps
CPU time 194.33 seconds
Started Apr 04 01:12:55 PM PDT 24
Finished Apr 04 01:16:10 PM PDT 24
Peak memory 218836 kb
Host smart-ae36132b-db51-41fa-b421-12cd64e10265
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514777726 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2514777726
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.935697276
Short name T672
Test name
Test status
Simulation time 438328383 ps
CPU time 1.59 seconds
Started Apr 04 01:13:25 PM PDT 24
Finished Apr 04 01:13:27 PM PDT 24
Peak memory 201852 kb
Host smart-e21b2b26-f3a7-47d9-85af-ba0f77c1d751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935697276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.935697276
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.982746070
Short name T237
Test name
Test status
Simulation time 228409357441 ps
CPU time 13.41 seconds
Started Apr 04 01:13:05 PM PDT 24
Finished Apr 04 01:13:18 PM PDT 24
Peak memory 202244 kb
Host smart-d5e670dd-8aff-4efe-a5c3-692e5f6ad9d2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982746070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gati
ng.982746070
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.2893277889
Short name T293
Test name
Test status
Simulation time 321229888091 ps
CPU time 491.49 seconds
Started Apr 04 01:13:02 PM PDT 24
Finished Apr 04 01:21:13 PM PDT 24
Peak memory 202268 kb
Host smart-20ebd74d-6591-4fa8-96e1-bbd188914303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893277889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2893277889
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1040533348
Short name T551
Test name
Test status
Simulation time 492655426947 ps
CPU time 574.74 seconds
Started Apr 04 01:13:03 PM PDT 24
Finished Apr 04 01:22:38 PM PDT 24
Peak memory 202232 kb
Host smart-207b2a93-dab2-4339-b041-6a170cd13bb0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040533348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1040533348
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.2202662799
Short name T506
Test name
Test status
Simulation time 157991788920 ps
CPU time 47.04 seconds
Started Apr 04 01:12:54 PM PDT 24
Finished Apr 04 01:13:41 PM PDT 24
Peak memory 202248 kb
Host smart-4aaa50d4-d0be-4085-b90f-a0aa089c5a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202662799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.2202662799
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.3363028796
Short name T161
Test name
Test status
Simulation time 486107143138 ps
CPU time 270.56 seconds
Started Apr 04 01:12:54 PM PDT 24
Finished Apr 04 01:17:24 PM PDT 24
Peak memory 202272 kb
Host smart-cb0f785e-fe39-4a96-989b-9c68d201cc92
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363028796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.3363028796
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.1887236462
Short name T96
Test name
Test status
Simulation time 451628117828 ps
CPU time 323.84 seconds
Started Apr 04 01:13:04 PM PDT 24
Finished Apr 04 01:18:28 PM PDT 24
Peak memory 202184 kb
Host smart-f574d8e0-03d4-45c5-8a79-02e1fa4d2c67
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887236462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.1887236462
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.3275349504
Short name T482
Test name
Test status
Simulation time 604099702253 ps
CPU time 401.89 seconds
Started Apr 04 01:13:05 PM PDT 24
Finished Apr 04 01:19:47 PM PDT 24
Peak memory 202216 kb
Host smart-ab0fac3e-a6dc-4eb6-8d67-bc31e43720b7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275349504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.3275349504
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.400859068
Short name T333
Test name
Test status
Simulation time 117102309400 ps
CPU time 443.66 seconds
Started Apr 04 01:13:11 PM PDT 24
Finished Apr 04 01:20:34 PM PDT 24
Peak memory 202660 kb
Host smart-7f345984-0a1e-4fb9-83fa-15bd89383639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400859068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.400859068
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.155562963
Short name T711
Test name
Test status
Simulation time 32896079057 ps
CPU time 37.64 seconds
Started Apr 04 01:13:13 PM PDT 24
Finished Apr 04 01:13:51 PM PDT 24
Peak memory 202064 kb
Host smart-fbd4d9ef-3e1b-4bcc-9913-1a958159007a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155562963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.155562963
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.4227996036
Short name T416
Test name
Test status
Simulation time 5183322393 ps
CPU time 2.18 seconds
Started Apr 04 01:13:13 PM PDT 24
Finished Apr 04 01:13:16 PM PDT 24
Peak memory 202064 kb
Host smart-d90befae-8e79-4d8c-aebc-1259090a7ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227996036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.4227996036
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.2645814062
Short name T511
Test name
Test status
Simulation time 5853460523 ps
CPU time 13.93 seconds
Started Apr 04 01:12:53 PM PDT 24
Finished Apr 04 01:13:07 PM PDT 24
Peak memory 202016 kb
Host smart-3e39c08c-a94e-459a-b0f3-73afe9ee4799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645814062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.2645814062
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.3894312087
Short name T282
Test name
Test status
Simulation time 182553948745 ps
CPU time 107.05 seconds
Started Apr 04 01:13:24 PM PDT 24
Finished Apr 04 01:15:11 PM PDT 24
Peak memory 202264 kb
Host smart-c210697f-d126-4d29-a6d5-6b6676fc56a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894312087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.3894312087
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.27788235
Short name T687
Test name
Test status
Simulation time 61762646980 ps
CPU time 123.92 seconds
Started Apr 04 01:13:26 PM PDT 24
Finished Apr 04 01:15:30 PM PDT 24
Peak memory 210952 kb
Host smart-5b4feffc-d98f-4c41-a7af-1003ed5b200d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27788235 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.27788235
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.992619056
Short name T664
Test name
Test status
Simulation time 311759568 ps
CPU time 1 seconds
Started Apr 04 01:13:46 PM PDT 24
Finished Apr 04 01:13:47 PM PDT 24
Peak memory 201880 kb
Host smart-8593648f-c38e-418d-bada-078e8e2fabdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992619056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.992619056
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.234274030
Short name T213
Test name
Test status
Simulation time 496326592303 ps
CPU time 1016.58 seconds
Started Apr 04 01:13:37 PM PDT 24
Finished Apr 04 01:30:34 PM PDT 24
Peak memory 202100 kb
Host smart-cd30a97e-6b9e-4be5-ae61-be8cc46f13f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234274030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.234274030
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.4283256240
Short name T646
Test name
Test status
Simulation time 328865030777 ps
CPU time 756.25 seconds
Started Apr 04 01:13:37 PM PDT 24
Finished Apr 04 01:26:13 PM PDT 24
Peak memory 202088 kb
Host smart-beaef72f-70c5-4e35-9a95-a1ad8bb2a5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283256240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.4283256240
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.55974247
Short name T752
Test name
Test status
Simulation time 167372549855 ps
CPU time 389.45 seconds
Started Apr 04 01:13:37 PM PDT 24
Finished Apr 04 01:20:06 PM PDT 24
Peak memory 202276 kb
Host smart-52729d5d-a522-46b8-b9b7-785f1983fb68
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=55974247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt
_fixed.55974247
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.1749548562
Short name T238
Test name
Test status
Simulation time 328442438044 ps
CPU time 363.28 seconds
Started Apr 04 01:13:25 PM PDT 24
Finished Apr 04 01:19:29 PM PDT 24
Peak memory 202280 kb
Host smart-7e5289a0-5dfe-4893-b206-fd858196f0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749548562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.1749548562
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.1926637037
Short name T359
Test name
Test status
Simulation time 494143241114 ps
CPU time 286.49 seconds
Started Apr 04 01:13:24 PM PDT 24
Finished Apr 04 01:18:11 PM PDT 24
Peak memory 202076 kb
Host smart-d29a8297-30e6-41c1-8440-b10177104150
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926637037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.1926637037
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1407668635
Short name T590
Test name
Test status
Simulation time 564377426706 ps
CPU time 655.88 seconds
Started Apr 04 01:13:35 PM PDT 24
Finished Apr 04 01:24:31 PM PDT 24
Peak memory 202336 kb
Host smart-74db9ae6-33dd-499f-9524-3b300f86ef39
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407668635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1407668635
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.3290563145
Short name T605
Test name
Test status
Simulation time 601227787970 ps
CPU time 1274.49 seconds
Started Apr 04 01:13:36 PM PDT 24
Finished Apr 04 01:34:51 PM PDT 24
Peak memory 202152 kb
Host smart-a4ff1dda-381c-49b8-bc71-2a397bd78ede
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290563145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.3290563145
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.3397571473
Short name T340
Test name
Test status
Simulation time 137044751844 ps
CPU time 503.21 seconds
Started Apr 04 01:13:46 PM PDT 24
Finished Apr 04 01:22:09 PM PDT 24
Peak memory 202548 kb
Host smart-2f229f61-ba0d-4217-b847-92c8282598dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397571473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.3397571473
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.47804429
Short name T598
Test name
Test status
Simulation time 42106482243 ps
CPU time 26.65 seconds
Started Apr 04 01:13:48 PM PDT 24
Finished Apr 04 01:14:15 PM PDT 24
Peak memory 202032 kb
Host smart-4016c62d-168c-45c8-83bb-4a5b5b4a3cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47804429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.47804429
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.1510626212
Short name T755
Test name
Test status
Simulation time 3401644945 ps
CPU time 2.81 seconds
Started Apr 04 01:13:46 PM PDT 24
Finished Apr 04 01:13:48 PM PDT 24
Peak memory 202068 kb
Host smart-b40341cd-ce62-419a-af35-064468cc7cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510626212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.1510626212
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2357090158
Short name T361
Test name
Test status
Simulation time 5864954778 ps
CPU time 14.83 seconds
Started Apr 04 01:13:24 PM PDT 24
Finished Apr 04 01:13:39 PM PDT 24
Peak memory 202004 kb
Host smart-d6e23739-bda3-4c0d-b8bb-b189c3cf27ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357090158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2357090158
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.1116850310
Short name T530
Test name
Test status
Simulation time 330829202195 ps
CPU time 760.41 seconds
Started Apr 04 01:13:46 PM PDT 24
Finished Apr 04 01:26:26 PM PDT 24
Peak memory 202236 kb
Host smart-5a3bd3cb-353e-4f3d-90f0-583a875b5673
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116850310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.1116850310
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.657470117
Short name T22
Test name
Test status
Simulation time 320519440652 ps
CPU time 91.28 seconds
Started Apr 04 01:13:47 PM PDT 24
Finished Apr 04 01:15:19 PM PDT 24
Peak memory 210584 kb
Host smart-fc478539-3d22-4991-872e-ee3ec215436e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657470117 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.657470117
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1726384239
Short name T518
Test name
Test status
Simulation time 304660794 ps
CPU time 1.36 seconds
Started Apr 04 01:14:19 PM PDT 24
Finished Apr 04 01:14:21 PM PDT 24
Peak memory 201976 kb
Host smart-662dcb76-0cc4-4dc7-8ded-dff57f4073b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726384239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1726384239
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3810054368
Short name T562
Test name
Test status
Simulation time 186696119725 ps
CPU time 51.28 seconds
Started Apr 04 01:14:09 PM PDT 24
Finished Apr 04 01:15:01 PM PDT 24
Peak memory 202148 kb
Host smart-dd514713-61a4-4050-bc28-611b4e896c72
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810054368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3810054368
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1747015394
Short name T665
Test name
Test status
Simulation time 163605169330 ps
CPU time 93.26 seconds
Started Apr 04 01:14:11 PM PDT 24
Finished Apr 04 01:15:45 PM PDT 24
Peak memory 202228 kb
Host smart-ac75047e-5af1-4602-ba18-a017180cbac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747015394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1747015394
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2847323355
Short name T628
Test name
Test status
Simulation time 165207495001 ps
CPU time 358.48 seconds
Started Apr 04 01:13:58 PM PDT 24
Finished Apr 04 01:19:57 PM PDT 24
Peak memory 202184 kb
Host smart-ba91249f-e100-4e9b-91eb-ef70915caddb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847323355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2847323355
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.466606866
Short name T143
Test name
Test status
Simulation time 489894432839 ps
CPU time 286.41 seconds
Started Apr 04 01:13:58 PM PDT 24
Finished Apr 04 01:18:45 PM PDT 24
Peak memory 202248 kb
Host smart-f1756980-d7fb-4fda-800f-e2b0ec29904f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466606866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.466606866
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.1815160742
Short name T531
Test name
Test status
Simulation time 331777525290 ps
CPU time 201.91 seconds
Started Apr 04 01:13:57 PM PDT 24
Finished Apr 04 01:17:19 PM PDT 24
Peak memory 202368 kb
Host smart-25d17a79-4496-42c7-b820-4ce6532fb606
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815160742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.1815160742
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2830657140
Short name T174
Test name
Test status
Simulation time 538254884633 ps
CPU time 232.18 seconds
Started Apr 04 01:13:58 PM PDT 24
Finished Apr 04 01:17:50 PM PDT 24
Peak memory 202224 kb
Host smart-5b53b3d1-a225-4848-b2e4-51be037a7a57
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830657140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2830657140
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.4168028638
Short name T84
Test name
Test status
Simulation time 396796344870 ps
CPU time 449.65 seconds
Started Apr 04 01:13:57 PM PDT 24
Finished Apr 04 01:21:27 PM PDT 24
Peak memory 202140 kb
Host smart-3dcdee68-4906-4003-b143-ab3cef15141b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168028638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.4168028638
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.2979422787
Short name T37
Test name
Test status
Simulation time 105289588719 ps
CPU time 338.99 seconds
Started Apr 04 01:14:08 PM PDT 24
Finished Apr 04 01:19:48 PM PDT 24
Peak memory 202544 kb
Host smart-c7711d8a-3078-43ff-a0d1-b67ade465f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979422787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2979422787
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.386240111
Short name T357
Test name
Test status
Simulation time 25037010960 ps
CPU time 7.97 seconds
Started Apr 04 01:14:09 PM PDT 24
Finished Apr 04 01:14:18 PM PDT 24
Peak memory 202092 kb
Host smart-258bf130-6cce-4673-b4bd-7556357b4cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386240111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.386240111
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.9681906
Short name T488
Test name
Test status
Simulation time 4458557786 ps
CPU time 7.29 seconds
Started Apr 04 01:14:11 PM PDT 24
Finished Apr 04 01:14:19 PM PDT 24
Peak memory 202028 kb
Host smart-5289c8e8-81fc-4b68-989a-7b5465ea21f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9681906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.9681906
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.3972041577
Short name T717
Test name
Test status
Simulation time 5974779469 ps
CPU time 5.94 seconds
Started Apr 04 01:13:46 PM PDT 24
Finished Apr 04 01:13:52 PM PDT 24
Peak memory 201984 kb
Host smart-6f439f9e-739c-4fa5-97ea-775ae2ddd272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972041577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3972041577
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.1241510115
Short name T666
Test name
Test status
Simulation time 413639515259 ps
CPU time 484.88 seconds
Started Apr 04 01:14:19 PM PDT 24
Finished Apr 04 01:22:24 PM PDT 24
Peak memory 202220 kb
Host smart-ebc7f91c-e270-45b5-8b84-d7e5eb100b16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241510115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.1241510115
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1481612736
Short name T650
Test name
Test status
Simulation time 368839268 ps
CPU time 1.44 seconds
Started Apr 04 01:07:04 PM PDT 24
Finished Apr 04 01:07:05 PM PDT 24
Peak memory 201976 kb
Host smart-51f2da69-a3c8-4749-9f42-090c27028358
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481612736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1481612736
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3646398428
Short name T203
Test name
Test status
Simulation time 523687132581 ps
CPU time 1201.06 seconds
Started Apr 04 01:06:50 PM PDT 24
Finished Apr 04 01:26:52 PM PDT 24
Peak memory 202212 kb
Host smart-a55b9f2d-984a-420a-9a55-95bf27a24f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646398428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3646398428
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.984072281
Short name T572
Test name
Test status
Simulation time 162818584182 ps
CPU time 183.91 seconds
Started Apr 04 01:06:51 PM PDT 24
Finished Apr 04 01:09:56 PM PDT 24
Peak memory 202264 kb
Host smart-69622b61-605c-439c-be41-6ed9a3126c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984072281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.984072281
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.96218041
Short name T599
Test name
Test status
Simulation time 326186995043 ps
CPU time 717.42 seconds
Started Apr 04 01:06:51 PM PDT 24
Finished Apr 04 01:18:50 PM PDT 24
Peak memory 202216 kb
Host smart-2464a491-2cc9-44bf-afb9-f19a3a274846
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=96218041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt_
fixed.96218041
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.4219340541
Short name T173
Test name
Test status
Simulation time 484307998337 ps
CPU time 62.95 seconds
Started Apr 04 01:06:51 PM PDT 24
Finished Apr 04 01:07:55 PM PDT 24
Peak memory 202220 kb
Host smart-63c52450-19e6-454f-b75a-acca42e5f729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219340541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.4219340541
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.2000846656
Short name T443
Test name
Test status
Simulation time 487786245323 ps
CPU time 1229.86 seconds
Started Apr 04 01:06:49 PM PDT 24
Finished Apr 04 01:27:19 PM PDT 24
Peak memory 202140 kb
Host smart-895e45a5-f858-45dc-a66f-9720ad7df0c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000846656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.2000846656
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.2215351102
Short name T247
Test name
Test status
Simulation time 561375959216 ps
CPU time 1195.74 seconds
Started Apr 04 01:06:50 PM PDT 24
Finished Apr 04 01:26:46 PM PDT 24
Peak memory 202264 kb
Host smart-96cdd25f-5b7c-44bf-8672-6f162a47607c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215351102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.2215351102
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2768344844
Short name T486
Test name
Test status
Simulation time 205504145745 ps
CPU time 499.92 seconds
Started Apr 04 01:06:50 PM PDT 24
Finished Apr 04 01:15:10 PM PDT 24
Peak memory 202184 kb
Host smart-399bba73-1eb3-4ce5-baae-a0efa987238e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768344844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2768344844
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.215014738
Short name T792
Test name
Test status
Simulation time 90843913597 ps
CPU time 453.57 seconds
Started Apr 04 01:07:01 PM PDT 24
Finished Apr 04 01:14:36 PM PDT 24
Peak memory 202608 kb
Host smart-a8e23471-0a97-4237-ad5e-d004410765de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215014738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.215014738
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.1271229308
Short name T580
Test name
Test status
Simulation time 40762347965 ps
CPU time 47.64 seconds
Started Apr 04 01:07:03 PM PDT 24
Finished Apr 04 01:07:52 PM PDT 24
Peak memory 201704 kb
Host smart-7e2e6229-001b-4c8b-82fe-19f43d501d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271229308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.1271229308
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3390384788
Short name T412
Test name
Test status
Simulation time 4578299332 ps
CPU time 6.68 seconds
Started Apr 04 01:07:05 PM PDT 24
Finished Apr 04 01:07:12 PM PDT 24
Peak memory 202032 kb
Host smart-e8738855-e044-4989-872d-bc04bfe1fc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390384788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3390384788
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.1323708144
Short name T566
Test name
Test status
Simulation time 6003012942 ps
CPU time 4.02 seconds
Started Apr 04 01:06:50 PM PDT 24
Finished Apr 04 01:06:54 PM PDT 24
Peak memory 202076 kb
Host smart-d4f11454-d654-4c4e-ad9d-2fa27d46f742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323708144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.1323708144
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.640478070
Short name T596
Test name
Test status
Simulation time 204121530088 ps
CPU time 62.62 seconds
Started Apr 04 01:07:02 PM PDT 24
Finished Apr 04 01:08:06 PM PDT 24
Peak memory 202236 kb
Host smart-9785896e-3212-42cb-ad3b-4649e130015b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640478070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.640478070
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1064462484
Short name T19
Test name
Test status
Simulation time 286846140089 ps
CPU time 247.92 seconds
Started Apr 04 01:07:03 PM PDT 24
Finished Apr 04 01:11:12 PM PDT 24
Peak memory 210892 kb
Host smart-a4563d16-7ce9-4300-8e2e-18096c0d1a72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064462484 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1064462484
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1954807609
Short name T726
Test name
Test status
Simulation time 496361170 ps
CPU time 0.83 seconds
Started Apr 04 01:14:48 PM PDT 24
Finished Apr 04 01:14:50 PM PDT 24
Peak memory 201952 kb
Host smart-56a968a4-3d07-40ed-83e6-dc0d00213120
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954807609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1954807609
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.4187074176
Short name T207
Test name
Test status
Simulation time 168349507040 ps
CPU time 93.2 seconds
Started Apr 04 01:14:38 PM PDT 24
Finished Apr 04 01:16:11 PM PDT 24
Peak memory 202324 kb
Host smart-749a4488-cd8b-404a-8a93-0a97c903a94b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187074176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.4187074176
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1396459162
Short name T520
Test name
Test status
Simulation time 484641966228 ps
CPU time 296.78 seconds
Started Apr 04 01:14:32 PM PDT 24
Finished Apr 04 01:19:29 PM PDT 24
Peak memory 202212 kb
Host smart-6f895f11-15da-407f-be69-c3a7566da94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396459162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1396459162
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3868213246
Short name T516
Test name
Test status
Simulation time 326449195298 ps
CPU time 771.58 seconds
Started Apr 04 01:14:29 PM PDT 24
Finished Apr 04 01:27:21 PM PDT 24
Peak memory 202220 kb
Host smart-2009327d-d885-4cc0-bd42-9cf4cdd9823b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868213246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3868213246
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3987079709
Short name T607
Test name
Test status
Simulation time 486759582714 ps
CPU time 580.61 seconds
Started Apr 04 01:14:29 PM PDT 24
Finished Apr 04 01:24:10 PM PDT 24
Peak memory 202236 kb
Host smart-bff6fd0b-56e3-4d35-979f-bfb71dab37ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987079709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3987079709
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.2577044995
Short name T641
Test name
Test status
Simulation time 169515142900 ps
CPU time 375.98 seconds
Started Apr 04 01:14:28 PM PDT 24
Finished Apr 04 01:20:45 PM PDT 24
Peak memory 202148 kb
Host smart-ad66ad5a-0e43-44ec-9fcf-30b8f91c71dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577044995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.2577044995
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.520925425
Short name T303
Test name
Test status
Simulation time 385521703344 ps
CPU time 462.76 seconds
Started Apr 04 01:14:29 PM PDT 24
Finished Apr 04 01:22:12 PM PDT 24
Peak memory 202180 kb
Host smart-bf8796e0-feeb-4abc-8f4e-3633ed66f8ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520925425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.520925425
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.113184856
Short name T159
Test name
Test status
Simulation time 199141540185 ps
CPU time 114.94 seconds
Started Apr 04 01:14:39 PM PDT 24
Finished Apr 04 01:16:36 PM PDT 24
Peak memory 202236 kb
Host smart-8e062a4f-5ce9-4df1-856a-81130fb7dae7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113184856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
adc_ctrl_filters_wakeup_fixed.113184856
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.3264837020
Short name T781
Test name
Test status
Simulation time 25302834904 ps
CPU time 5.23 seconds
Started Apr 04 01:14:49 PM PDT 24
Finished Apr 04 01:14:54 PM PDT 24
Peak memory 202084 kb
Host smart-b5e4a522-fa13-47d5-a2a7-2ded96fe7fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264837020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3264837020
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.3028443584
Short name T582
Test name
Test status
Simulation time 4956703098 ps
CPU time 6.75 seconds
Started Apr 04 01:14:48 PM PDT 24
Finished Apr 04 01:14:56 PM PDT 24
Peak memory 202072 kb
Host smart-cf9a3977-75b9-4f3a-8a60-9af08f4be598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028443584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.3028443584
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.2125261930
Short name T783
Test name
Test status
Simulation time 5588940167 ps
CPU time 14.09 seconds
Started Apr 04 01:14:19 PM PDT 24
Finished Apr 04 01:14:33 PM PDT 24
Peak memory 202004 kb
Host smart-58200a83-fb46-4766-910b-89d32a95a080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125261930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2125261930
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.633926750
Short name T644
Test name
Test status
Simulation time 470744185890 ps
CPU time 1404.7 seconds
Started Apr 04 01:14:50 PM PDT 24
Finished Apr 04 01:38:15 PM PDT 24
Peak memory 212836 kb
Host smart-e0a61335-2834-4c16-876b-626cf6836737
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633926750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.
633926750
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.3827575942
Short name T690
Test name
Test status
Simulation time 34601455602 ps
CPU time 37.55 seconds
Started Apr 04 01:14:50 PM PDT 24
Finished Apr 04 01:15:28 PM PDT 24
Peak memory 210588 kb
Host smart-b702902c-1e2d-434b-a99a-22daf66407a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827575942 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.3827575942
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2036014027
Short name T762
Test name
Test status
Simulation time 498281742 ps
CPU time 1.73 seconds
Started Apr 04 01:15:21 PM PDT 24
Finished Apr 04 01:15:23 PM PDT 24
Peak memory 201972 kb
Host smart-485e3ce8-cdc4-45ab-a76a-429f4a44574f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036014027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2036014027
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2430188211
Short name T315
Test name
Test status
Simulation time 537481066251 ps
CPU time 1246.53 seconds
Started Apr 04 01:15:03 PM PDT 24
Finished Apr 04 01:35:50 PM PDT 24
Peak memory 202228 kb
Host smart-e256f9c3-ddaf-421f-bd6d-c9433883092c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430188211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2430188211
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.743560215
Short name T128
Test name
Test status
Simulation time 162021155291 ps
CPU time 384.18 seconds
Started Apr 04 01:14:59 PM PDT 24
Finished Apr 04 01:21:23 PM PDT 24
Peak memory 202220 kb
Host smart-301ac4c5-1283-4c15-9ec1-61df10cc0c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743560215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.743560215
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.3698507186
Short name T543
Test name
Test status
Simulation time 162553705918 ps
CPU time 353.65 seconds
Started Apr 04 01:15:00 PM PDT 24
Finished Apr 04 01:20:53 PM PDT 24
Peak memory 202244 kb
Host smart-d86766ca-59b9-4fcf-a8ef-5d810e22979f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698507186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.3698507186
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2186876937
Short name T78
Test name
Test status
Simulation time 331128231405 ps
CPU time 418.38 seconds
Started Apr 04 01:15:01 PM PDT 24
Finished Apr 04 01:21:59 PM PDT 24
Peak memory 202200 kb
Host smart-43cd293a-f6bd-443f-828a-ef1585653991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186876937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2186876937
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1666256138
Short name T436
Test name
Test status
Simulation time 160425755131 ps
CPU time 194.81 seconds
Started Apr 04 01:15:02 PM PDT 24
Finished Apr 04 01:18:17 PM PDT 24
Peak memory 202316 kb
Host smart-5524d9e7-3666-40e9-82a3-3fb840c2144b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666256138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1666256138
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.2225448405
Short name T268
Test name
Test status
Simulation time 168911811646 ps
CPU time 107.62 seconds
Started Apr 04 01:14:59 PM PDT 24
Finished Apr 04 01:16:47 PM PDT 24
Peak memory 202280 kb
Host smart-6b55aa12-2154-4f71-8360-d61bfebc0edf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225448405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.2225448405
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.4269243901
Short name T747
Test name
Test status
Simulation time 205670570335 ps
CPU time 486.49 seconds
Started Apr 04 01:15:00 PM PDT 24
Finished Apr 04 01:23:06 PM PDT 24
Peak memory 202192 kb
Host smart-9b25ad6b-3312-4624-a3d8-9941b999e67e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269243901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.4269243901
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.4106668716
Short name T453
Test name
Test status
Simulation time 22106344467 ps
CPU time 25.6 seconds
Started Apr 04 01:15:22 PM PDT 24
Finished Apr 04 01:15:47 PM PDT 24
Peak memory 202020 kb
Host smart-6450a7bf-4836-4cd4-bc69-9331747424db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106668716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.4106668716
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.3060397510
Short name T583
Test name
Test status
Simulation time 4012119193 ps
CPU time 10.37 seconds
Started Apr 04 01:15:22 PM PDT 24
Finished Apr 04 01:15:32 PM PDT 24
Peak memory 202024 kb
Host smart-3d0f3628-5dc3-4738-b45c-50e3ac0fa30c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060397510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.3060397510
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2713145636
Short name T519
Test name
Test status
Simulation time 5686391913 ps
CPU time 7.06 seconds
Started Apr 04 01:14:59 PM PDT 24
Finished Apr 04 01:15:06 PM PDT 24
Peak memory 202068 kb
Host smart-a3eeffab-ff7a-4606-a235-8b8745d18d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713145636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2713145636
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3462421963
Short name T533
Test name
Test status
Simulation time 38736938734 ps
CPU time 87.08 seconds
Started Apr 04 01:15:21 PM PDT 24
Finished Apr 04 01:16:48 PM PDT 24
Peak memory 210624 kb
Host smart-25c27b99-6834-48e1-9fc2-20fcb3515392
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462421963 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3462421963
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.1403804065
Short name T633
Test name
Test status
Simulation time 368611829 ps
CPU time 0.84 seconds
Started Apr 04 01:15:42 PM PDT 24
Finished Apr 04 01:15:44 PM PDT 24
Peak memory 201968 kb
Host smart-7b3750d1-18da-4a4a-8bee-d0c832f33362
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403804065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1403804065
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2706913390
Short name T686
Test name
Test status
Simulation time 418862558852 ps
CPU time 948.55 seconds
Started Apr 04 01:15:26 PM PDT 24
Finished Apr 04 01:31:15 PM PDT 24
Peak memory 202256 kb
Host smart-b3622dd1-22f1-4d85-b0d0-5513f009ab38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706913390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2706913390
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2558974066
Short name T254
Test name
Test status
Simulation time 314349527254 ps
CPU time 337.15 seconds
Started Apr 04 01:15:22 PM PDT 24
Finished Apr 04 01:20:59 PM PDT 24
Peak memory 202268 kb
Host smart-c492a6ff-7736-4956-bf72-adb4a9fd6dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558974066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2558974066
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1862572124
Short name T85
Test name
Test status
Simulation time 487872008460 ps
CPU time 277.06 seconds
Started Apr 04 01:15:27 PM PDT 24
Finished Apr 04 01:20:04 PM PDT 24
Peak memory 202192 kb
Host smart-222e4c46-18ee-4bd6-923c-1f24f7c6fba4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862572124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1862572124
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3032402708
Short name T491
Test name
Test status
Simulation time 491831345237 ps
CPU time 1137.53 seconds
Started Apr 04 01:15:21 PM PDT 24
Finished Apr 04 01:34:19 PM PDT 24
Peak memory 202212 kb
Host smart-15b5e857-ebed-4afa-afbc-77459c1ebb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032402708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3032402708
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.2235525621
Short name T79
Test name
Test status
Simulation time 168873983701 ps
CPU time 356.91 seconds
Started Apr 04 01:15:21 PM PDT 24
Finished Apr 04 01:21:18 PM PDT 24
Peak memory 202228 kb
Host smart-98153a05-c6fd-458f-b5d4-40af8b41ae25
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235525621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.2235525621
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2313244459
Short name T226
Test name
Test status
Simulation time 205622327982 ps
CPU time 58.26 seconds
Started Apr 04 01:15:27 PM PDT 24
Finished Apr 04 01:16:26 PM PDT 24
Peak memory 202176 kb
Host smart-893d0221-5ac4-423b-b333-81a9ee92ee99
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313244459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2313244459
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.705726288
Short name T742
Test name
Test status
Simulation time 612419863933 ps
CPU time 377 seconds
Started Apr 04 01:15:26 PM PDT 24
Finished Apr 04 01:21:44 PM PDT 24
Peak memory 202204 kb
Host smart-b010d12f-7b5b-4561-8192-2cd3135fee93
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705726288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
adc_ctrl_filters_wakeup_fixed.705726288
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3686133638
Short name T794
Test name
Test status
Simulation time 107353897901 ps
CPU time 537.99 seconds
Started Apr 04 01:15:42 PM PDT 24
Finished Apr 04 01:24:42 PM PDT 24
Peak memory 202504 kb
Host smart-3ad67f82-3aae-43fb-a654-46caf8648876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686133638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3686133638
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.4166382075
Short name T170
Test name
Test status
Simulation time 38792468365 ps
CPU time 10.74 seconds
Started Apr 04 01:15:27 PM PDT 24
Finished Apr 04 01:15:38 PM PDT 24
Peak memory 201992 kb
Host smart-85c2740c-8434-40f1-aabe-f6058c5e6118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166382075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.4166382075
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3993966532
Short name T667
Test name
Test status
Simulation time 2742042920 ps
CPU time 6.43 seconds
Started Apr 04 01:15:27 PM PDT 24
Finished Apr 04 01:15:33 PM PDT 24
Peak memory 201996 kb
Host smart-78b5603c-e8b6-4f07-ab5e-613e4634bc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993966532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3993966532
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.110352923
Short name T414
Test name
Test status
Simulation time 5980130823 ps
CPU time 7.46 seconds
Started Apr 04 01:15:22 PM PDT 24
Finished Apr 04 01:15:30 PM PDT 24
Peak memory 202032 kb
Host smart-5de70e0a-2628-438d-a1d1-827e8e764032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110352923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.110352923
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.527206008
Short name T735
Test name
Test status
Simulation time 30491770767 ps
CPU time 39.4 seconds
Started Apr 04 01:15:44 PM PDT 24
Finished Apr 04 01:16:24 PM PDT 24
Peak memory 210956 kb
Host smart-f96235da-b936-49ab-a22d-e034d1caea9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527206008 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.527206008
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1862007215
Short name T606
Test name
Test status
Simulation time 308196849 ps
CPU time 1.31 seconds
Started Apr 04 01:15:59 PM PDT 24
Finished Apr 04 01:16:00 PM PDT 24
Peak memory 201976 kb
Host smart-e1d0cbb2-0f6d-4f7a-b50d-2d0aa6ad64b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862007215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1862007215
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3884141209
Short name T622
Test name
Test status
Simulation time 493583162118 ps
CPU time 271.59 seconds
Started Apr 04 01:16:01 PM PDT 24
Finished Apr 04 01:20:34 PM PDT 24
Peak memory 202264 kb
Host smart-9bd5d68d-13a5-42b8-93ef-5a05774841a8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884141209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3884141209
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.679985585
Short name T135
Test name
Test status
Simulation time 335361708162 ps
CPU time 851.65 seconds
Started Apr 04 01:15:54 PM PDT 24
Finished Apr 04 01:30:06 PM PDT 24
Peak memory 202196 kb
Host smart-4f89763f-a91a-4eb0-8d6f-37a0a427f5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679985585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.679985585
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.2152159400
Short name T306
Test name
Test status
Simulation time 321654286390 ps
CPU time 577.78 seconds
Started Apr 04 01:15:44 PM PDT 24
Finished Apr 04 01:25:23 PM PDT 24
Peak memory 202248 kb
Host smart-86e6591d-5c8b-43a0-9aeb-3fe1c26f67ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152159400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2152159400
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.1074411709
Short name T415
Test name
Test status
Simulation time 162581165691 ps
CPU time 90.66 seconds
Started Apr 04 01:15:54 PM PDT 24
Finished Apr 04 01:17:25 PM PDT 24
Peak memory 202268 kb
Host smart-431fa786-e617-4bdd-a0f0-33b6ebde6941
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074411709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.1074411709
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.1859438607
Short name T772
Test name
Test status
Simulation time 330930357311 ps
CPU time 415.76 seconds
Started Apr 04 01:15:42 PM PDT 24
Finished Apr 04 01:22:38 PM PDT 24
Peak memory 202096 kb
Host smart-1ff974e5-a5dc-44e9-96f0-c14408a7ce09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859438607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.1859438607
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1538696956
Short name T517
Test name
Test status
Simulation time 490172915041 ps
CPU time 78.42 seconds
Started Apr 04 01:15:43 PM PDT 24
Finished Apr 04 01:17:02 PM PDT 24
Peak memory 202236 kb
Host smart-d7ffd884-cbf7-4acc-9417-6b7f759e7d89
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538696956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1538696956
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1098583926
Short name T260
Test name
Test status
Simulation time 338827370763 ps
CPU time 395.2 seconds
Started Apr 04 01:16:01 PM PDT 24
Finished Apr 04 01:22:37 PM PDT 24
Peak memory 202196 kb
Host smart-d74c577b-6342-400d-bb29-a2e4f098493c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098583926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1098583926
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.1117157253
Short name T548
Test name
Test status
Simulation time 393114943473 ps
CPU time 233.23 seconds
Started Apr 04 01:15:55 PM PDT 24
Finished Apr 04 01:19:49 PM PDT 24
Peak memory 202148 kb
Host smart-23caac77-db05-439d-a2c6-f80f8aae92a0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117157253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.1117157253
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.3152168841
Short name T765
Test name
Test status
Simulation time 135194361474 ps
CPU time 458.48 seconds
Started Apr 04 01:15:53 PM PDT 24
Finished Apr 04 01:23:32 PM PDT 24
Peak memory 202564 kb
Host smart-1b64bbdd-f4f3-423e-af45-c699c79274ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152168841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3152168841
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.3431707027
Short name T360
Test name
Test status
Simulation time 26710552672 ps
CPU time 32.57 seconds
Started Apr 04 01:15:56 PM PDT 24
Finished Apr 04 01:16:29 PM PDT 24
Peak memory 202076 kb
Host smart-3ccc219d-9920-4945-8473-2e808f85a1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431707027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.3431707027
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3744246128
Short name T674
Test name
Test status
Simulation time 5166362131 ps
CPU time 11.88 seconds
Started Apr 04 01:15:54 PM PDT 24
Finished Apr 04 01:16:06 PM PDT 24
Peak memory 202096 kb
Host smart-dcec4352-fc88-49ae-9166-6c2c6912ac73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744246128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3744246128
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.758082939
Short name T541
Test name
Test status
Simulation time 5876367082 ps
CPU time 14.32 seconds
Started Apr 04 01:15:42 PM PDT 24
Finished Apr 04 01:15:57 PM PDT 24
Peak memory 201988 kb
Host smart-6fe40a0a-4318-410c-918d-b80dbfcddad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758082939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.758082939
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.90479979
Short name T163
Test name
Test status
Simulation time 330569956530 ps
CPU time 181.51 seconds
Started Apr 04 01:15:54 PM PDT 24
Finished Apr 04 01:18:55 PM PDT 24
Peak memory 202300 kb
Host smart-e8ac6343-637e-4c95-9fd7-7f30aadf7d46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90479979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.90479979
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.3489350609
Short name T87
Test name
Test status
Simulation time 42533984324 ps
CPU time 103.17 seconds
Started Apr 04 01:15:57 PM PDT 24
Finished Apr 04 01:17:41 PM PDT 24
Peak memory 210592 kb
Host smart-bb5326cb-efb2-4246-80cc-2f1e1c6b1680
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489350609 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.3489350609
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.3854788257
Short name T460
Test name
Test status
Simulation time 448300936 ps
CPU time 1.55 seconds
Started Apr 04 01:16:13 PM PDT 24
Finished Apr 04 01:16:16 PM PDT 24
Peak memory 201968 kb
Host smart-02527877-a320-4a5b-aa82-b71f16e87d5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854788257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3854788257
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.272168063
Short name T193
Test name
Test status
Simulation time 166865544277 ps
CPU time 329.93 seconds
Started Apr 04 01:16:04 PM PDT 24
Finished Apr 04 01:21:35 PM PDT 24
Peak memory 202248 kb
Host smart-86ef2e0c-a69d-4243-916f-25863b2d1541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272168063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.272168063
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3770495029
Short name T95
Test name
Test status
Simulation time 328298212562 ps
CPU time 770.79 seconds
Started Apr 04 01:16:04 PM PDT 24
Finished Apr 04 01:28:55 PM PDT 24
Peak memory 202172 kb
Host smart-feaf0bb2-044d-450b-a51a-fd73a6020390
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770495029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3770495029
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.1899527984
Short name T313
Test name
Test status
Simulation time 326022326117 ps
CPU time 760.47 seconds
Started Apr 04 01:16:00 PM PDT 24
Finished Apr 04 01:28:41 PM PDT 24
Peak memory 202204 kb
Host smart-f3aeb4d6-cdd2-4436-bc9e-e9b819fc2986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899527984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1899527984
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.3765108115
Short name T397
Test name
Test status
Simulation time 317625319381 ps
CPU time 707.24 seconds
Started Apr 04 01:15:56 PM PDT 24
Finished Apr 04 01:27:43 PM PDT 24
Peak memory 202148 kb
Host smart-363f3aa2-7e21-45b8-b7cf-3f44c8350680
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765108115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.3765108115
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.2246664120
Short name T663
Test name
Test status
Simulation time 590633470159 ps
CPU time 1315.71 seconds
Started Apr 04 01:16:03 PM PDT 24
Finished Apr 04 01:37:59 PM PDT 24
Peak memory 202240 kb
Host smart-26137515-535a-4723-9eaf-479c899b3b9f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246664120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.2246664120
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.3732389817
Short name T447
Test name
Test status
Simulation time 92610249371 ps
CPU time 356.58 seconds
Started Apr 04 01:16:15 PM PDT 24
Finished Apr 04 01:22:11 PM PDT 24
Peak memory 202556 kb
Host smart-30a9224e-7b92-4978-9aaf-d6aea2bdb366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732389817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.3732389817
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3727510789
Short name T586
Test name
Test status
Simulation time 38720820332 ps
CPU time 34.35 seconds
Started Apr 04 01:16:13 PM PDT 24
Finished Apr 04 01:16:48 PM PDT 24
Peak memory 201956 kb
Host smart-b12d3323-1f13-4f40-804d-5fb2ee6532ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727510789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3727510789
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.4252138402
Short name T756
Test name
Test status
Simulation time 4036954228 ps
CPU time 4.89 seconds
Started Apr 04 01:16:11 PM PDT 24
Finished Apr 04 01:16:16 PM PDT 24
Peak memory 202024 kb
Host smart-217cd1ad-9af7-4c0d-88fb-3d66c3929485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252138402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.4252138402
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.3902600197
Short name T761
Test name
Test status
Simulation time 5826036706 ps
CPU time 4.25 seconds
Started Apr 04 01:16:00 PM PDT 24
Finished Apr 04 01:16:05 PM PDT 24
Peak memory 202016 kb
Host smart-4693fba3-e9b4-4872-bd02-b57c08587165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902600197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.3902600197
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.1845536937
Short name T449
Test name
Test status
Simulation time 330217205170 ps
CPU time 403.62 seconds
Started Apr 04 01:16:12 PM PDT 24
Finished Apr 04 01:22:57 PM PDT 24
Peak memory 202312 kb
Host smart-9b262d06-83aa-427a-90b7-4ac98df9536d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845536937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.1845536937
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.828683573
Short name T786
Test name
Test status
Simulation time 142581618502 ps
CPU time 152.1 seconds
Started Apr 04 01:16:12 PM PDT 24
Finished Apr 04 01:18:45 PM PDT 24
Peak memory 218360 kb
Host smart-2aa012e3-8ebc-4987-afff-b4ae98ff7bf8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828683573 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.828683573
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1282984651
Short name T536
Test name
Test status
Simulation time 402161804 ps
CPU time 1.52 seconds
Started Apr 04 01:16:34 PM PDT 24
Finished Apr 04 01:16:36 PM PDT 24
Peak memory 201968 kb
Host smart-6b9ae4d0-a221-44ce-9d4d-e06b4af14532
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282984651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1282984651
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.1461307960
Short name T758
Test name
Test status
Simulation time 346461681244 ps
CPU time 416.15 seconds
Started Apr 04 01:16:22 PM PDT 24
Finished Apr 04 01:23:18 PM PDT 24
Peak memory 202260 kb
Host smart-7f55c66b-0f62-4a66-a3f2-516c7798a05f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461307960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.1461307960
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2138155032
Short name T495
Test name
Test status
Simulation time 175883483882 ps
CPU time 438.7 seconds
Started Apr 04 01:16:21 PM PDT 24
Finished Apr 04 01:23:41 PM PDT 24
Peak memory 202256 kb
Host smart-751bc8df-201a-4bd3-b903-9de0ee6fa0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138155032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2138155032
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.4227657499
Short name T132
Test name
Test status
Simulation time 491749806504 ps
CPU time 536.36 seconds
Started Apr 04 01:16:12 PM PDT 24
Finished Apr 04 01:25:08 PM PDT 24
Peak memory 202284 kb
Host smart-016f3008-701f-4fcb-b9fc-0bb24db2e41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227657499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.4227657499
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.2683526998
Short name T373
Test name
Test status
Simulation time 319270290105 ps
CPU time 199.25 seconds
Started Apr 04 01:16:23 PM PDT 24
Finished Apr 04 01:19:42 PM PDT 24
Peak memory 202208 kb
Host smart-bc72c352-bf59-40dd-a268-c59c3e70a9e4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683526998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.2683526998
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.2352838837
Short name T147
Test name
Test status
Simulation time 166744433832 ps
CPU time 352.74 seconds
Started Apr 04 01:16:13 PM PDT 24
Finished Apr 04 01:22:07 PM PDT 24
Peak memory 202312 kb
Host smart-c60ca48e-bedd-4a4f-8819-c4d2a7e275e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352838837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.2352838837
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.587937582
Short name T470
Test name
Test status
Simulation time 326283643454 ps
CPU time 730.63 seconds
Started Apr 04 01:16:14 PM PDT 24
Finished Apr 04 01:28:25 PM PDT 24
Peak memory 202244 kb
Host smart-60e5f93a-9bb5-40a3-bc59-f899bd674649
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=587937582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixe
d.587937582
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.2964666138
Short name T713
Test name
Test status
Simulation time 190118571712 ps
CPU time 221.18 seconds
Started Apr 04 01:16:23 PM PDT 24
Finished Apr 04 01:20:05 PM PDT 24
Peak memory 202348 kb
Host smart-95d8990a-c8f1-4d24-ba6c-8d4c31979c5b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964666138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.2964666138
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.3690221183
Short name T505
Test name
Test status
Simulation time 200847042579 ps
CPU time 453.52 seconds
Started Apr 04 01:16:23 PM PDT 24
Finished Apr 04 01:23:57 PM PDT 24
Peak memory 202176 kb
Host smart-61c7c0b2-a170-4903-9c95-24f95f5e5b0a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690221183 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.3690221183
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.166914145
Short name T52
Test name
Test status
Simulation time 75699626608 ps
CPU time 302.96 seconds
Started Apr 04 01:16:23 PM PDT 24
Finished Apr 04 01:21:26 PM PDT 24
Peak memory 202544 kb
Host smart-7cd646a7-6713-46f5-bebc-6f15ac1a1ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166914145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.166914145
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.3760909040
Short name T423
Test name
Test status
Simulation time 22131142885 ps
CPU time 11.21 seconds
Started Apr 04 01:16:23 PM PDT 24
Finished Apr 04 01:16:34 PM PDT 24
Peak memory 201960 kb
Host smart-b8d95258-e620-480c-87e6-bf6aebdb68a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760909040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.3760909040
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1417277312
Short name T749
Test name
Test status
Simulation time 3423486256 ps
CPU time 2.65 seconds
Started Apr 04 01:16:21 PM PDT 24
Finished Apr 04 01:16:24 PM PDT 24
Peak memory 202040 kb
Host smart-96c5345c-9757-4c0d-a1b0-a4fe3d6331a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417277312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1417277312
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.2097133848
Short name T47
Test name
Test status
Simulation time 5731994734 ps
CPU time 3.72 seconds
Started Apr 04 01:16:14 PM PDT 24
Finished Apr 04 01:16:18 PM PDT 24
Peak memory 202068 kb
Host smart-d7e0285e-6a1a-478c-aacd-19e857c9f8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097133848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.2097133848
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.3975588896
Short name T676
Test name
Test status
Simulation time 211390706565 ps
CPU time 185.56 seconds
Started Apr 04 01:16:31 PM PDT 24
Finished Apr 04 01:19:37 PM PDT 24
Peak memory 202332 kb
Host smart-e5726280-f901-4e68-afcf-22f3e0741261
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975588896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.3975588896
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.43209523
Short name T262
Test name
Test status
Simulation time 102985845991 ps
CPU time 181.17 seconds
Started Apr 04 01:16:22 PM PDT 24
Finished Apr 04 01:19:24 PM PDT 24
Peak memory 210924 kb
Host smart-3e556dd6-82d8-4225-ab93-f4c3626c4bd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43209523 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.43209523
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.3689836534
Short name T587
Test name
Test status
Simulation time 423667667 ps
CPU time 1.08 seconds
Started Apr 04 01:16:51 PM PDT 24
Finished Apr 04 01:16:52 PM PDT 24
Peak memory 201928 kb
Host smart-12609eb5-5a63-4b28-a754-157d85cfbb31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689836534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.3689836534
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.3522637870
Short name T156
Test name
Test status
Simulation time 530664774517 ps
CPU time 229.11 seconds
Started Apr 04 01:16:40 PM PDT 24
Finished Apr 04 01:20:29 PM PDT 24
Peak memory 202360 kb
Host smart-ecc10232-dcc6-40dd-b9fd-5ebbf37a53c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522637870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.3522637870
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3948931241
Short name T81
Test name
Test status
Simulation time 487654482484 ps
CPU time 302.65 seconds
Started Apr 04 01:16:32 PM PDT 24
Finished Apr 04 01:21:35 PM PDT 24
Peak memory 202288 kb
Host smart-cd4c5775-0458-4158-b753-442c89c318a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948931241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3948931241
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.4267922662
Short name T591
Test name
Test status
Simulation time 332203305971 ps
CPU time 687.69 seconds
Started Apr 04 01:16:40 PM PDT 24
Finished Apr 04 01:28:07 PM PDT 24
Peak memory 202140 kb
Host smart-a401c6be-be77-478c-9629-11040aa2a7ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267922662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.4267922662
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.621425934
Short name T134
Test name
Test status
Simulation time 330523768714 ps
CPU time 350.12 seconds
Started Apr 04 01:16:31 PM PDT 24
Finished Apr 04 01:22:22 PM PDT 24
Peak memory 202316 kb
Host smart-715a0c29-f09e-4d64-9040-11201ad7e2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621425934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.621425934
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.628068404
Short name T793
Test name
Test status
Simulation time 481017221850 ps
CPU time 512.85 seconds
Started Apr 04 01:16:32 PM PDT 24
Finished Apr 04 01:25:05 PM PDT 24
Peak memory 202180 kb
Host smart-f7028a3e-f52e-436b-8304-d14b49f6c0f9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=628068404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixe
d.628068404
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.2624785684
Short name T732
Test name
Test status
Simulation time 367431783197 ps
CPU time 224.16 seconds
Started Apr 04 01:16:42 PM PDT 24
Finished Apr 04 01:20:26 PM PDT 24
Peak memory 202212 kb
Host smart-1d225605-aa87-467c-b7c0-ca6900197ad6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624785684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.2624785684
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.193714904
Short name T493
Test name
Test status
Simulation time 204513596123 ps
CPU time 124.73 seconds
Started Apr 04 01:16:42 PM PDT 24
Finished Apr 04 01:18:46 PM PDT 24
Peak memory 202264 kb
Host smart-1f48185e-d833-4c4f-88bc-c52e785bf534
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193714904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
adc_ctrl_filters_wakeup_fixed.193714904
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.3027013367
Short name T656
Test name
Test status
Simulation time 47287896334 ps
CPU time 53.54 seconds
Started Apr 04 01:16:41 PM PDT 24
Finished Apr 04 01:17:34 PM PDT 24
Peak memory 202048 kb
Host smart-8d3175f5-f413-457c-b597-fafb67f59381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027013367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.3027013367
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.2837736249
Short name T597
Test name
Test status
Simulation time 2746306044 ps
CPU time 3.76 seconds
Started Apr 04 01:16:40 PM PDT 24
Finished Apr 04 01:16:45 PM PDT 24
Peak memory 202088 kb
Host smart-dc9ae785-c29a-4632-bd4a-b3b52e013b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837736249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.2837736249
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1922824901
Short name T391
Test name
Test status
Simulation time 5798848455 ps
CPU time 15.3 seconds
Started Apr 04 01:16:32 PM PDT 24
Finished Apr 04 01:16:48 PM PDT 24
Peak memory 202060 kb
Host smart-69b9f54e-636a-4888-976a-b165bdfb62a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922824901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1922824901
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.565519021
Short name T653
Test name
Test status
Simulation time 341772294777 ps
CPU time 171.24 seconds
Started Apr 04 01:16:51 PM PDT 24
Finished Apr 04 01:19:43 PM PDT 24
Peak memory 202248 kb
Host smart-64e72789-3930-4ae1-990f-753769737f40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565519021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all.
565519021
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.693514849
Short name T435
Test name
Test status
Simulation time 397567633 ps
CPU time 1.09 seconds
Started Apr 04 01:17:11 PM PDT 24
Finished Apr 04 01:17:12 PM PDT 24
Peak memory 201876 kb
Host smart-a17a4310-be88-49cf-b9f5-1c88071ff06c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693514849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.693514849
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.180645903
Short name T312
Test name
Test status
Simulation time 328235447530 ps
CPU time 684.32 seconds
Started Apr 04 01:17:03 PM PDT 24
Finished Apr 04 01:28:27 PM PDT 24
Peak memory 202320 kb
Host smart-746190be-a00a-4b9d-9cf6-52c370b29cb9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180645903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gati
ng.180645903
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.175660024
Short name T273
Test name
Test status
Simulation time 165189583020 ps
CPU time 186.8 seconds
Started Apr 04 01:17:02 PM PDT 24
Finished Apr 04 01:20:09 PM PDT 24
Peak memory 202168 kb
Host smart-643084cc-4e15-4ff5-ad05-9ae8eef42c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175660024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.175660024
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.3905015231
Short name T212
Test name
Test status
Simulation time 164936338423 ps
CPU time 99.71 seconds
Started Apr 04 01:16:51 PM PDT 24
Finished Apr 04 01:18:31 PM PDT 24
Peak memory 202160 kb
Host smart-80b00541-6527-45b9-9205-14897f4099dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905015231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3905015231
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.952647355
Short name T678
Test name
Test status
Simulation time 161487440454 ps
CPU time 37.84 seconds
Started Apr 04 01:17:01 PM PDT 24
Finished Apr 04 01:17:39 PM PDT 24
Peak memory 202188 kb
Host smart-3d3311d3-dda5-4161-86a3-6a894730a149
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=952647355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.952647355
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3801521508
Short name T390
Test name
Test status
Simulation time 169308307300 ps
CPU time 103.48 seconds
Started Apr 04 01:16:52 PM PDT 24
Finished Apr 04 01:18:36 PM PDT 24
Peak memory 202144 kb
Host smart-df5638de-82b2-4c91-98e9-cd8b1611a35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801521508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3801521508
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.3809615232
Short name T396
Test name
Test status
Simulation time 319272514095 ps
CPU time 187.96 seconds
Started Apr 04 01:16:52 PM PDT 24
Finished Apr 04 01:20:00 PM PDT 24
Peak memory 202220 kb
Host smart-9b73ad1c-6ce6-4e64-8327-b3a2dbf0efe9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809615232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.3809615232
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3029629520
Short name T189
Test name
Test status
Simulation time 344056111054 ps
CPU time 819.35 seconds
Started Apr 04 01:17:01 PM PDT 24
Finished Apr 04 01:30:41 PM PDT 24
Peak memory 202352 kb
Host smart-296d9963-2528-4df3-b2f7-48e8e74f7bf2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029629520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3029629520
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.896393451
Short name T614
Test name
Test status
Simulation time 110717311324 ps
CPU time 586.02 seconds
Started Apr 04 01:17:11 PM PDT 24
Finished Apr 04 01:26:57 PM PDT 24
Peak memory 202604 kb
Host smart-dfc533c1-b056-4b97-ae43-73afb0210714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896393451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.896393451
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.3230364153
Short name T688
Test name
Test status
Simulation time 27812859650 ps
CPU time 32.61 seconds
Started Apr 04 01:17:01 PM PDT 24
Finished Apr 04 01:17:34 PM PDT 24
Peak memory 202028 kb
Host smart-be59b67e-4ae6-436f-9c91-2ee0deba201f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230364153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.3230364153
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.60661453
Short name T768
Test name
Test status
Simulation time 3750423937 ps
CPU time 2.68 seconds
Started Apr 04 01:17:02 PM PDT 24
Finished Apr 04 01:17:05 PM PDT 24
Peak memory 201988 kb
Host smart-e28c637f-6796-463a-a9c3-007574183bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60661453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.60661453
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2014887673
Short name T744
Test name
Test status
Simulation time 5768239030 ps
CPU time 3.87 seconds
Started Apr 04 01:16:51 PM PDT 24
Finished Apr 04 01:16:55 PM PDT 24
Peak memory 202060 kb
Host smart-1808f649-3d7a-49c6-84d4-282530b4fafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014887673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2014887673
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3743849026
Short name T659
Test name
Test status
Simulation time 48707301143 ps
CPU time 30.03 seconds
Started Apr 04 01:17:12 PM PDT 24
Finished Apr 04 01:17:43 PM PDT 24
Peak memory 202352 kb
Host smart-efc7368d-fbda-47ca-90ef-2a80ebc5507c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743849026 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3743849026
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.185148647
Short name T439
Test name
Test status
Simulation time 437297744 ps
CPU time 0.75 seconds
Started Apr 04 01:17:26 PM PDT 24
Finished Apr 04 01:17:27 PM PDT 24
Peak memory 201968 kb
Host smart-8f254cb6-f71e-4f1f-bf7c-cdaef1cd359a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185148647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.185148647
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3405600839
Short name T310
Test name
Test status
Simulation time 160354294704 ps
CPU time 18.02 seconds
Started Apr 04 01:17:25 PM PDT 24
Finished Apr 04 01:17:44 PM PDT 24
Peak memory 202164 kb
Host smart-f2fe086d-382f-4013-be2c-9dc1eba6ca25
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405600839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3405600839
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.611369301
Short name T304
Test name
Test status
Simulation time 328715724869 ps
CPU time 394.52 seconds
Started Apr 04 01:17:26 PM PDT 24
Finished Apr 04 01:24:01 PM PDT 24
Peak memory 202340 kb
Host smart-c8e00852-5515-4722-853f-25387410493a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611369301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.611369301
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.3947244853
Short name T311
Test name
Test status
Simulation time 491467456060 ps
CPU time 1078.78 seconds
Started Apr 04 01:17:25 PM PDT 24
Finished Apr 04 01:35:25 PM PDT 24
Peak memory 202316 kb
Host smart-4adba8e3-f0a1-471a-9d2c-30637e2dfb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947244853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.3947244853
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1818106571
Short name T30
Test name
Test status
Simulation time 165081315726 ps
CPU time 42.08 seconds
Started Apr 04 01:17:11 PM PDT 24
Finished Apr 04 01:17:53 PM PDT 24
Peak memory 202272 kb
Host smart-056d51fe-a4f5-4fc0-a59b-4b2e949c5778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818106571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1818106571
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.377541313
Short name T625
Test name
Test status
Simulation time 330105449037 ps
CPU time 748.78 seconds
Started Apr 04 01:17:12 PM PDT 24
Finished Apr 04 01:29:41 PM PDT 24
Peak memory 202128 kb
Host smart-84162783-524c-40af-9f20-7fca68c6face
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=377541313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe
d.377541313
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.560933194
Short name T545
Test name
Test status
Simulation time 199598421811 ps
CPU time 446.86 seconds
Started Apr 04 01:17:26 PM PDT 24
Finished Apr 04 01:24:53 PM PDT 24
Peak memory 202248 kb
Host smart-4264f224-22cf-45b5-87bc-b0e56711051f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560933194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.560933194
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.614634653
Short name T588
Test name
Test status
Simulation time 66969923568 ps
CPU time 431.32 seconds
Started Apr 04 01:17:24 PM PDT 24
Finished Apr 04 01:24:36 PM PDT 24
Peak memory 202628 kb
Host smart-5b0225e8-c6f7-480e-865d-7295ff28dfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614634653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.614634653
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.778223691
Short name T775
Test name
Test status
Simulation time 21888073496 ps
CPU time 53.58 seconds
Started Apr 04 01:17:24 PM PDT 24
Finished Apr 04 01:18:19 PM PDT 24
Peak memory 202076 kb
Host smart-a71d6818-2831-4a04-9d21-2bac85d9fde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778223691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.778223691
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.619594840
Short name T741
Test name
Test status
Simulation time 5180251027 ps
CPU time 6.95 seconds
Started Apr 04 01:17:25 PM PDT 24
Finished Apr 04 01:17:33 PM PDT 24
Peak memory 202064 kb
Host smart-03a03263-88c3-42fa-978a-954bce403233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619594840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.619594840
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1683367180
Short name T365
Test name
Test status
Simulation time 5570075943 ps
CPU time 13.57 seconds
Started Apr 04 01:17:12 PM PDT 24
Finished Apr 04 01:17:26 PM PDT 24
Peak memory 201984 kb
Host smart-00383d6f-4e79-4fbe-981f-1a74b3c2f683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683367180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1683367180
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3019344182
Short name T563
Test name
Test status
Simulation time 457896498 ps
CPU time 0.69 seconds
Started Apr 04 01:18:08 PM PDT 24
Finished Apr 04 01:18:09 PM PDT 24
Peak memory 201964 kb
Host smart-718b651e-205f-43a3-ac34-f29a13757928
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019344182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3019344182
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3736428711
Short name T465
Test name
Test status
Simulation time 162069636960 ps
CPU time 26.01 seconds
Started Apr 04 01:17:38 PM PDT 24
Finished Apr 04 01:18:04 PM PDT 24
Peak memory 202256 kb
Host smart-34cbc15f-84b1-472f-85bd-7225d11d8515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736428711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3736428711
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1753324544
Short name T707
Test name
Test status
Simulation time 497783381557 ps
CPU time 101.31 seconds
Started Apr 04 01:17:39 PM PDT 24
Finished Apr 04 01:19:20 PM PDT 24
Peak memory 202300 kb
Host smart-eab41302-2a69-4298-8cc6-3108fe75fd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753324544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1753324544
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2177637989
Short name T629
Test name
Test status
Simulation time 167778215969 ps
CPU time 353.6 seconds
Started Apr 04 01:17:37 PM PDT 24
Finished Apr 04 01:23:31 PM PDT 24
Peak memory 202240 kb
Host smart-52ea3bdb-5211-4116-bfc1-65a79687885c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177637989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2177637989
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.363506577
Short name T124
Test name
Test status
Simulation time 159872316096 ps
CPU time 128.36 seconds
Started Apr 04 01:17:37 PM PDT 24
Finished Apr 04 01:19:45 PM PDT 24
Peak memory 202236 kb
Host smart-23b237e2-eab0-43eb-8393-1be51edad68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363506577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.363506577
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.553899174
Short name T716
Test name
Test status
Simulation time 168198786383 ps
CPU time 371.76 seconds
Started Apr 04 01:17:36 PM PDT 24
Finished Apr 04 01:23:48 PM PDT 24
Peak memory 202212 kb
Host smart-d6d639b1-f481-48b3-9ab5-804e9a5921dd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=553899174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fixe
d.553899174
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.484252390
Short name T185
Test name
Test status
Simulation time 433138488822 ps
CPU time 198.2 seconds
Started Apr 04 01:17:36 PM PDT 24
Finished Apr 04 01:20:54 PM PDT 24
Peak memory 202220 kb
Host smart-56b2a887-5d81-46b3-be53-137abe30eba1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484252390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_
wakeup.484252390
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3094907062
Short name T585
Test name
Test status
Simulation time 396227862439 ps
CPU time 234.85 seconds
Started Apr 04 01:17:37 PM PDT 24
Finished Apr 04 01:21:32 PM PDT 24
Peak memory 202160 kb
Host smart-a145a9ea-c7b9-4a23-9a64-f01832e42338
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094907062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3094907062
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.1590928615
Short name T555
Test name
Test status
Simulation time 94173989593 ps
CPU time 352.9 seconds
Started Apr 04 01:17:55 PM PDT 24
Finished Apr 04 01:23:48 PM PDT 24
Peak memory 202516 kb
Host smart-a311a576-abd9-4e03-ae5f-cc410e160d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590928615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.1590928615
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.323428261
Short name T442
Test name
Test status
Simulation time 28601565868 ps
CPU time 31.14 seconds
Started Apr 04 01:17:55 PM PDT 24
Finished Apr 04 01:18:27 PM PDT 24
Peak memory 202128 kb
Host smart-18680d81-1d51-4363-9ccf-fee0e8fe7377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323428261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.323428261
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.2962592933
Short name T694
Test name
Test status
Simulation time 3901043260 ps
CPU time 5 seconds
Started Apr 04 01:17:56 PM PDT 24
Finished Apr 04 01:18:01 PM PDT 24
Peak memory 202100 kb
Host smart-11614b84-b1e9-48d1-b4d2-2ea6e8a57eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962592933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.2962592933
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.1936053203
Short name T669
Test name
Test status
Simulation time 5556301569 ps
CPU time 3 seconds
Started Apr 04 01:17:38 PM PDT 24
Finished Apr 04 01:17:41 PM PDT 24
Peak memory 201996 kb
Host smart-6e999b7c-5164-49d9-a4b1-4c600047d040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936053203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.1936053203
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.801737646
Short name T151
Test name
Test status
Simulation time 347472570008 ps
CPU time 213.57 seconds
Started Apr 04 01:17:56 PM PDT 24
Finished Apr 04 01:21:30 PM PDT 24
Peak memory 202304 kb
Host smart-70a023e0-6710-445d-8d9f-ae1e1ea8c312
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801737646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
801737646
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.3340156509
Short name T17
Test name
Test status
Simulation time 106290889223 ps
CPU time 194.54 seconds
Started Apr 04 01:17:55 PM PDT 24
Finished Apr 04 01:21:11 PM PDT 24
Peak memory 210912 kb
Host smart-cf970c30-861d-430e-8f87-9ec34ee72bdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340156509 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.3340156509
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1346505278
Short name T458
Test name
Test status
Simulation time 395883831 ps
CPU time 0.89 seconds
Started Apr 04 01:07:11 PM PDT 24
Finished Apr 04 01:07:13 PM PDT 24
Peak memory 201864 kb
Host smart-01c28878-e859-45ad-b0fb-fd353bce754d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346505278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1346505278
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.2394322569
Short name T564
Test name
Test status
Simulation time 329672428688 ps
CPU time 702 seconds
Started Apr 04 01:07:05 PM PDT 24
Finished Apr 04 01:18:47 PM PDT 24
Peak memory 202196 kb
Host smart-85e5094c-0873-480a-912e-7428884cad12
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394322569 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.2394322569
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1612145643
Short name T307
Test name
Test status
Simulation time 492417952002 ps
CPU time 541.59 seconds
Started Apr 04 01:07:01 PM PDT 24
Finished Apr 04 01:16:03 PM PDT 24
Peak memory 202136 kb
Host smart-8e843543-dc22-486e-88f0-e42a0e544c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612145643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1612145643
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2321855410
Short name T368
Test name
Test status
Simulation time 163726808894 ps
CPU time 184.15 seconds
Started Apr 04 01:07:01 PM PDT 24
Finished Apr 04 01:10:06 PM PDT 24
Peak memory 202228 kb
Host smart-dffe80d6-f411-44b9-adc0-756c8f3c4f90
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321855410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.2321855410
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.938824623
Short name T626
Test name
Test status
Simulation time 161957975685 ps
CPU time 60.22 seconds
Started Apr 04 01:07:04 PM PDT 24
Finished Apr 04 01:08:04 PM PDT 24
Peak memory 202196 kb
Host smart-fbb32111-90f8-41b0-ace3-5f2d2eac2093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938824623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.938824623
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.3819429618
Short name T513
Test name
Test status
Simulation time 164393342759 ps
CPU time 200.97 seconds
Started Apr 04 01:07:01 PM PDT 24
Finished Apr 04 01:10:23 PM PDT 24
Peak memory 202264 kb
Host smart-89ba3107-537f-481b-b501-8f47a54b9256
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819429618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.3819429618
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.1733615618
Short name T218
Test name
Test status
Simulation time 235125714856 ps
CPU time 564.18 seconds
Started Apr 04 01:07:02 PM PDT 24
Finished Apr 04 01:16:28 PM PDT 24
Peak memory 202216 kb
Host smart-0dcf09ca-9c11-4c18-a38f-00b0da352f47
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733615618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.1733615618
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1800066463
Short name T553
Test name
Test status
Simulation time 209920726040 ps
CPU time 434.38 seconds
Started Apr 04 01:07:05 PM PDT 24
Finished Apr 04 01:14:20 PM PDT 24
Peak memory 202224 kb
Host smart-b84f16d6-1cb5-4b66-a200-e7ef023d2332
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800066463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1800066463
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.2799669162
Short name T51
Test name
Test status
Simulation time 71764614112 ps
CPU time 316.74 seconds
Started Apr 04 01:07:06 PM PDT 24
Finished Apr 04 01:12:23 PM PDT 24
Peak memory 202560 kb
Host smart-230f34ab-870f-4d45-bac2-21e5729374d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799669162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.2799669162
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.4071037079
Short name T500
Test name
Test status
Simulation time 42569436136 ps
CPU time 24.52 seconds
Started Apr 04 01:07:02 PM PDT 24
Finished Apr 04 01:07:28 PM PDT 24
Peak memory 202092 kb
Host smart-00936f7c-503b-49cc-b028-7b88b268c4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071037079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.4071037079
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.3567357988
Short name T740
Test name
Test status
Simulation time 3125685545 ps
CPU time 2.38 seconds
Started Apr 04 01:07:02 PM PDT 24
Finished Apr 04 01:07:04 PM PDT 24
Peak memory 202088 kb
Host smart-1a435fad-59cc-45c5-ba92-3ed17d6701f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567357988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.3567357988
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3453614489
Short name T63
Test name
Test status
Simulation time 4050009241 ps
CPU time 3 seconds
Started Apr 04 01:07:11 PM PDT 24
Finished Apr 04 01:07:15 PM PDT 24
Peak memory 217696 kb
Host smart-1b07b089-d53e-4bae-8c40-6b4164c9d02c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453614489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3453614489
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.2432277639
Short name T160
Test name
Test status
Simulation time 5788445438 ps
CPU time 2.78 seconds
Started Apr 04 01:07:02 PM PDT 24
Finished Apr 04 01:07:06 PM PDT 24
Peak memory 201984 kb
Host smart-64de16cf-ca0d-44bc-aec2-d5bd1bc684c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432277639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2432277639
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3722332479
Short name T294
Test name
Test status
Simulation time 212919688281 ps
CPU time 484.57 seconds
Started Apr 04 01:07:04 PM PDT 24
Finished Apr 04 01:15:09 PM PDT 24
Peak memory 202208 kb
Host smart-677d93ff-24ab-4fc8-8d6a-8be049991680
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722332479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3722332479
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.446076757
Short name T618
Test name
Test status
Simulation time 392991089 ps
CPU time 0.85 seconds
Started Apr 04 01:18:07 PM PDT 24
Finished Apr 04 01:18:08 PM PDT 24
Peak memory 201968 kb
Host smart-7bbb2d93-fb93-4c39-96cf-848a5285b95a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446076757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.446076757
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.2333048666
Short name T234
Test name
Test status
Simulation time 333217048043 ps
CPU time 780.77 seconds
Started Apr 04 01:18:06 PM PDT 24
Finished Apr 04 01:31:07 PM PDT 24
Peak memory 202268 kb
Host smart-753c0554-8fec-4a6c-a03b-b220fe5c6079
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333048666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.2333048666
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1299598202
Short name T252
Test name
Test status
Simulation time 159846412915 ps
CPU time 94.47 seconds
Started Apr 04 01:18:07 PM PDT 24
Finished Apr 04 01:19:42 PM PDT 24
Peak memory 202264 kb
Host smart-10d2c42b-75d0-46d4-b05d-f3f9787520c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299598202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1299598202
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3750460547
Short name T763
Test name
Test status
Simulation time 169496572898 ps
CPU time 409.95 seconds
Started Apr 04 01:18:08 PM PDT 24
Finished Apr 04 01:24:58 PM PDT 24
Peak memory 202288 kb
Host smart-34c1cc7d-682e-4cfa-9ddf-b23174e16bb9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750460547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3750460547
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.1610457689
Short name T734
Test name
Test status
Simulation time 158592878438 ps
CPU time 182.44 seconds
Started Apr 04 01:18:07 PM PDT 24
Finished Apr 04 01:21:10 PM PDT 24
Peak memory 202248 kb
Host smart-530873f3-86c7-492e-b13a-2a0c2c29e7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610457689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.1610457689
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.3605595040
Short name T168
Test name
Test status
Simulation time 329301733860 ps
CPU time 803.54 seconds
Started Apr 04 01:18:07 PM PDT 24
Finished Apr 04 01:31:30 PM PDT 24
Peak memory 202220 kb
Host smart-1eefb486-8662-4358-bb09-6b418673168e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605595040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.3605595040
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2788131537
Short name T704
Test name
Test status
Simulation time 560684651393 ps
CPU time 681.98 seconds
Started Apr 04 01:18:09 PM PDT 24
Finished Apr 04 01:29:31 PM PDT 24
Peak memory 202380 kb
Host smart-60f6400f-834e-4341-9537-7150c93d6977
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788131537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2788131537
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3537142412
Short name T613
Test name
Test status
Simulation time 202749332724 ps
CPU time 90.23 seconds
Started Apr 04 01:18:08 PM PDT 24
Finished Apr 04 01:19:38 PM PDT 24
Peak memory 202208 kb
Host smart-723bf8c9-e786-4d25-9695-317f3c57d718
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537142412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3537142412
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2683903251
Short name T579
Test name
Test status
Simulation time 108492018907 ps
CPU time 427.73 seconds
Started Apr 04 01:18:06 PM PDT 24
Finished Apr 04 01:25:14 PM PDT 24
Peak memory 202468 kb
Host smart-a522e942-3a12-49d9-ae99-a54d2c89be14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683903251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2683903251
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.1121799519
Short name T355
Test name
Test status
Simulation time 24881775675 ps
CPU time 14.48 seconds
Started Apr 04 01:18:07 PM PDT 24
Finished Apr 04 01:18:22 PM PDT 24
Peak memory 202044 kb
Host smart-f2b06f55-f4c5-488e-90c6-226508cd4610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121799519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.1121799519
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3933408187
Short name T503
Test name
Test status
Simulation time 2750514841 ps
CPU time 3.74 seconds
Started Apr 04 01:18:08 PM PDT 24
Finished Apr 04 01:18:12 PM PDT 24
Peak memory 202072 kb
Host smart-713c41dc-1797-4e61-8dd4-b4ea6006c227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933408187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3933408187
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.3641306983
Short name T615
Test name
Test status
Simulation time 5628279325 ps
CPU time 12.49 seconds
Started Apr 04 01:18:09 PM PDT 24
Finished Apr 04 01:18:21 PM PDT 24
Peak memory 202072 kb
Host smart-1cbd3bb9-32a5-47c4-a73f-11d41e8e0b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641306983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3641306983
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1422811548
Short name T701
Test name
Test status
Simulation time 165039877706 ps
CPU time 89.91 seconds
Started Apr 04 01:18:08 PM PDT 24
Finished Apr 04 01:19:38 PM PDT 24
Peak memory 202316 kb
Host smart-52a743c4-3f2c-489d-b415-7afc28103847
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422811548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1422811548
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1613677124
Short name T785
Test name
Test status
Simulation time 162470162409 ps
CPU time 165.48 seconds
Started Apr 04 01:18:08 PM PDT 24
Finished Apr 04 01:20:53 PM PDT 24
Peak memory 210792 kb
Host smart-666a7053-7c64-4f76-b279-2a406aee0ce1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613677124 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1613677124
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.625959148
Short name T367
Test name
Test status
Simulation time 411618895 ps
CPU time 1.57 seconds
Started Apr 04 01:18:31 PM PDT 24
Finished Apr 04 01:18:33 PM PDT 24
Peak memory 202028 kb
Host smart-1c47f265-df06-4cfa-99ad-3b6b6c333aa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625959148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.625959148
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1802805379
Short name T186
Test name
Test status
Simulation time 506114823557 ps
CPU time 144.69 seconds
Started Apr 04 01:18:20 PM PDT 24
Finished Apr 04 01:20:44 PM PDT 24
Peak memory 202340 kb
Host smart-096a8034-f1cd-4f32-b85a-a5ede5f6192f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802805379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1802805379
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.1897295872
Short name T394
Test name
Test status
Simulation time 497089988151 ps
CPU time 358.55 seconds
Started Apr 04 01:18:19 PM PDT 24
Finished Apr 04 01:24:18 PM PDT 24
Peak memory 202232 kb
Host smart-c2dd4b0c-9c92-4558-a0f2-900f6ea5a91d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897295872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.1897295872
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2787463616
Short name T175
Test name
Test status
Simulation time 333413680539 ps
CPU time 133.86 seconds
Started Apr 04 01:18:19 PM PDT 24
Finished Apr 04 01:20:33 PM PDT 24
Peak memory 202168 kb
Host smart-405e9b5c-781a-494b-92e9-3575aae6ae3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787463616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2787463616
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.1349868039
Short name T378
Test name
Test status
Simulation time 483010345128 ps
CPU time 299.48 seconds
Started Apr 04 01:18:23 PM PDT 24
Finished Apr 04 01:23:22 PM PDT 24
Peak memory 202304 kb
Host smart-1d89ca38-9460-4f64-822d-02a46ec92a34
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349868039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.1349868039
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.554327314
Short name T125
Test name
Test status
Simulation time 418669558782 ps
CPU time 948.54 seconds
Started Apr 04 01:18:20 PM PDT 24
Finished Apr 04 01:34:09 PM PDT 24
Peak memory 202272 kb
Host smart-535a5008-9794-4ca1-a01f-8994d196624f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554327314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_
wakeup.554327314
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3665383519
Short name T479
Test name
Test status
Simulation time 397640329707 ps
CPU time 927.67 seconds
Started Apr 04 01:18:23 PM PDT 24
Finished Apr 04 01:33:51 PM PDT 24
Peak memory 202228 kb
Host smart-9ba829fb-98c0-486a-b39c-58bc5ffe23eb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665383519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3665383519
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2390001972
Short name T426
Test name
Test status
Simulation time 36294024866 ps
CPU time 76.72 seconds
Started Apr 04 01:18:31 PM PDT 24
Finished Apr 04 01:19:48 PM PDT 24
Peak memory 201984 kb
Host smart-20470219-239f-429d-8cb9-6a53538aca28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390001972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2390001972
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.899334213
Short name T25
Test name
Test status
Simulation time 5102159661 ps
CPU time 1.88 seconds
Started Apr 04 01:18:34 PM PDT 24
Finished Apr 04 01:18:37 PM PDT 24
Peak memory 201708 kb
Host smart-6fe3fd2f-136d-4af1-bd93-baf5987c1a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899334213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.899334213
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2263602751
Short name T779
Test name
Test status
Simulation time 5960533775 ps
CPU time 4.62 seconds
Started Apr 04 01:18:08 PM PDT 24
Finished Apr 04 01:18:13 PM PDT 24
Peak memory 202032 kb
Host smart-1cd1ee1d-b287-45f1-977f-8bb7ae503192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263602751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2263602751
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3496097927
Short name T67
Test name
Test status
Simulation time 652750041 ps
CPU time 0.68 seconds
Started Apr 04 01:18:51 PM PDT 24
Finished Apr 04 01:18:52 PM PDT 24
Peak memory 201976 kb
Host smart-cb9adab8-60e4-4cbd-ba91-269dca8d4228
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496097927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3496097927
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.4106695098
Short name T120
Test name
Test status
Simulation time 349340198298 ps
CPU time 201.44 seconds
Started Apr 04 01:18:42 PM PDT 24
Finished Apr 04 01:22:04 PM PDT 24
Peak memory 202272 kb
Host smart-01d3c450-48ca-4a60-91f9-8ebdd59de2b7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106695098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.4106695098
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3058164831
Short name T206
Test name
Test status
Simulation time 183662570327 ps
CPU time 101.03 seconds
Started Apr 04 01:18:41 PM PDT 24
Finished Apr 04 01:20:23 PM PDT 24
Peak memory 202256 kb
Host smart-9d62e83f-43e4-4167-a376-a7c61c47e434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058164831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3058164831
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.3453172447
Short name T267
Test name
Test status
Simulation time 328358611923 ps
CPU time 754.07 seconds
Started Apr 04 01:18:41 PM PDT 24
Finished Apr 04 01:31:16 PM PDT 24
Peak memory 202204 kb
Host smart-e2bec475-b35f-4db3-aaa8-9d0b2b5698e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453172447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.3453172447
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.54674333
Short name T640
Test name
Test status
Simulation time 167512572255 ps
CPU time 112.31 seconds
Started Apr 04 01:18:41 PM PDT 24
Finished Apr 04 01:20:34 PM PDT 24
Peak memory 202168 kb
Host smart-544b32d9-4ea7-4371-ba95-8b9bbeb47fdf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=54674333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt
_fixed.54674333
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.710201558
Short name T725
Test name
Test status
Simulation time 164433403756 ps
CPU time 197.88 seconds
Started Apr 04 01:18:30 PM PDT 24
Finished Apr 04 01:21:48 PM PDT 24
Peak memory 202180 kb
Host smart-1e7e37c1-af7f-4b97-9b90-b1de7eadcfb7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=710201558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixe
d.710201558
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.604776489
Short name T284
Test name
Test status
Simulation time 703506450421 ps
CPU time 406 seconds
Started Apr 04 01:18:42 PM PDT 24
Finished Apr 04 01:25:28 PM PDT 24
Peak memory 202348 kb
Host smart-2307ab21-e8c9-4044-8e79-0b7b4a58ff2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604776489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_
wakeup.604776489
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.364717595
Short name T537
Test name
Test status
Simulation time 604242138414 ps
CPU time 206.31 seconds
Started Apr 04 01:18:42 PM PDT 24
Finished Apr 04 01:22:09 PM PDT 24
Peak memory 202300 kb
Host smart-cb0a8b5c-011e-4e45-a975-8b8b97719cf3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364717595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
adc_ctrl_filters_wakeup_fixed.364717595
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2090416851
Short name T334
Test name
Test status
Simulation time 108340450213 ps
CPU time 531.04 seconds
Started Apr 04 01:18:53 PM PDT 24
Finished Apr 04 01:27:45 PM PDT 24
Peak memory 202544 kb
Host smart-cce9bcaf-5d50-4df0-99a0-e7486ffd1237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090416851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2090416851
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2390719435
Short name T183
Test name
Test status
Simulation time 39351603652 ps
CPU time 45.5 seconds
Started Apr 04 01:18:52 PM PDT 24
Finished Apr 04 01:19:38 PM PDT 24
Peak memory 202072 kb
Host smart-f0245d3d-dafb-4c20-863f-04f2fba521ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390719435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2390719435
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.786668796
Short name T492
Test name
Test status
Simulation time 5004200920 ps
CPU time 6.51 seconds
Started Apr 04 01:18:42 PM PDT 24
Finished Apr 04 01:18:49 PM PDT 24
Peak memory 202080 kb
Host smart-7ecab7f9-1aff-45ba-9706-3cea4c7b2721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786668796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.786668796
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.952259182
Short name T184
Test name
Test status
Simulation time 5868034351 ps
CPU time 2.68 seconds
Started Apr 04 01:18:30 PM PDT 24
Finished Apr 04 01:18:33 PM PDT 24
Peak memory 202032 kb
Host smart-a30919ea-fb13-4e1c-a07a-242d9fa2b961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952259182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.952259182
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2373532677
Short name T509
Test name
Test status
Simulation time 302886663541 ps
CPU time 915.24 seconds
Started Apr 04 01:18:53 PM PDT 24
Finished Apr 04 01:34:09 PM PDT 24
Peak memory 211956 kb
Host smart-0bea45f3-6777-4d7f-868f-a19b17323965
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373532677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2373532677
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.2077755591
Short name T561
Test name
Test status
Simulation time 78547776138 ps
CPU time 50.12 seconds
Started Apr 04 01:18:52 PM PDT 24
Finished Apr 04 01:19:42 PM PDT 24
Peak memory 210548 kb
Host smart-73259c16-cc06-4981-a25b-788401bd6d57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077755591 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.2077755591
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.3229414885
Short name T441
Test name
Test status
Simulation time 396245798 ps
CPU time 1.44 seconds
Started Apr 04 01:19:12 PM PDT 24
Finished Apr 04 01:19:14 PM PDT 24
Peak memory 201940 kb
Host smart-4ee35265-6036-4e4e-a13c-a93214b67078
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229414885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3229414885
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3072082039
Short name T696
Test name
Test status
Simulation time 345940614975 ps
CPU time 265.72 seconds
Started Apr 04 01:19:03 PM PDT 24
Finished Apr 04 01:23:29 PM PDT 24
Peak memory 202228 kb
Host smart-54fa80d0-74e8-4e07-9f11-31309d375d7a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072082039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3072082039
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.3018879872
Short name T221
Test name
Test status
Simulation time 366038073216 ps
CPU time 421.32 seconds
Started Apr 04 01:19:04 PM PDT 24
Finished Apr 04 01:26:05 PM PDT 24
Peak memory 202172 kb
Host smart-b1164e94-1d61-4445-8a06-f5f0d54b2652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018879872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3018879872
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.3106658321
Short name T718
Test name
Test status
Simulation time 169995875080 ps
CPU time 362.73 seconds
Started Apr 04 01:18:52 PM PDT 24
Finished Apr 04 01:24:56 PM PDT 24
Peak memory 202252 kb
Host smart-85543c30-0200-4304-9400-aed66faf5958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106658321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.3106658321
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3873168393
Short name T532
Test name
Test status
Simulation time 159304556981 ps
CPU time 381.88 seconds
Started Apr 04 01:18:53 PM PDT 24
Finished Apr 04 01:25:16 PM PDT 24
Peak memory 202048 kb
Host smart-895f81dd-b6ac-452a-8a3d-392a399874c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873168393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3873168393
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1889193438
Short name T778
Test name
Test status
Simulation time 490401636338 ps
CPU time 330.74 seconds
Started Apr 04 01:18:52 PM PDT 24
Finished Apr 04 01:24:23 PM PDT 24
Peak memory 202216 kb
Host smart-b023935d-62d2-46af-a8fd-0e2cbb058441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889193438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1889193438
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.919218053
Short name T776
Test name
Test status
Simulation time 163291541859 ps
CPU time 369.1 seconds
Started Apr 04 01:18:53 PM PDT 24
Finished Apr 04 01:25:03 PM PDT 24
Peak memory 202076 kb
Host smart-f3018df1-820f-47d0-81fc-703d34f02e2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=919218053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fixe
d.919218053
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1055601204
Short name T477
Test name
Test status
Simulation time 611091957285 ps
CPU time 429.63 seconds
Started Apr 04 01:19:04 PM PDT 24
Finished Apr 04 01:26:14 PM PDT 24
Peak memory 202320 kb
Host smart-91ef71bc-1bc1-4077-a40a-ca3d49f87bab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055601204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1055601204
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1972574679
Short name T724
Test name
Test status
Simulation time 137718363541 ps
CPU time 762.45 seconds
Started Apr 04 01:19:13 PM PDT 24
Finished Apr 04 01:31:56 PM PDT 24
Peak memory 202524 kb
Host smart-b299b43d-1697-439c-a3c2-f5b194b14450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972574679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1972574679
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.205246792
Short name T623
Test name
Test status
Simulation time 26592053133 ps
CPU time 14.85 seconds
Started Apr 04 01:19:04 PM PDT 24
Finished Apr 04 01:19:18 PM PDT 24
Peak memory 202048 kb
Host smart-88e7997a-e6ea-40b7-b59c-ac0cbd9e4bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205246792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.205246792
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3787914970
Short name T410
Test name
Test status
Simulation time 3843900193 ps
CPU time 2.72 seconds
Started Apr 04 01:19:04 PM PDT 24
Finished Apr 04 01:19:07 PM PDT 24
Peak memory 202104 kb
Host smart-7a0b1ac4-e40f-4af6-8802-4ee061a77323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787914970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3787914970
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.978736186
Short name T420
Test name
Test status
Simulation time 5877034143 ps
CPU time 6.36 seconds
Started Apr 04 01:18:55 PM PDT 24
Finished Apr 04 01:19:02 PM PDT 24
Peak memory 202012 kb
Host smart-9065f792-0b58-488e-a97b-a5d588ae08fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978736186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.978736186
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.2774646826
Short name T233
Test name
Test status
Simulation time 334938855530 ps
CPU time 749.4 seconds
Started Apr 04 01:19:12 PM PDT 24
Finished Apr 04 01:31:42 PM PDT 24
Peak memory 202336 kb
Host smart-9aeddb6e-231d-4f3d-bdd8-eebbc1f54435
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774646826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.2774646826
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.598960775
Short name T643
Test name
Test status
Simulation time 55274201998 ps
CPU time 142.62 seconds
Started Apr 04 01:19:12 PM PDT 24
Finished Apr 04 01:21:35 PM PDT 24
Peak memory 210920 kb
Host smart-05ba13c4-13f3-4a6a-aa33-2bdf1d8b5c2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598960775 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.598960775
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.2311866409
Short name T32
Test name
Test status
Simulation time 490851187 ps
CPU time 0.77 seconds
Started Apr 04 01:19:22 PM PDT 24
Finished Apr 04 01:19:23 PM PDT 24
Peak memory 201900 kb
Host smart-13177993-f650-40ba-b4dc-33e81117cf4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311866409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2311866409
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3182858007
Short name T287
Test name
Test status
Simulation time 529588712046 ps
CPU time 436.97 seconds
Started Apr 04 01:19:22 PM PDT 24
Finished Apr 04 01:26:39 PM PDT 24
Peak memory 202272 kb
Host smart-cfb51d5e-be05-4765-ab3b-1880cd52b167
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182858007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3182858007
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.2586544585
Short name T325
Test name
Test status
Simulation time 163732749716 ps
CPU time 39.14 seconds
Started Apr 04 01:19:23 PM PDT 24
Finished Apr 04 01:20:02 PM PDT 24
Peak memory 202156 kb
Host smart-55043bcd-441e-44c4-a7bc-5f25c0658cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586544585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.2586544585
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.3104236922
Short name T201
Test name
Test status
Simulation time 172768283211 ps
CPU time 108.42 seconds
Started Apr 04 01:19:11 PM PDT 24
Finished Apr 04 01:21:00 PM PDT 24
Peak memory 202244 kb
Host smart-21d23eb0-2bbb-42d6-844a-143dd29b945a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104236922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3104236922
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.209851024
Short name T430
Test name
Test status
Simulation time 491139781632 ps
CPU time 257.24 seconds
Started Apr 04 01:19:11 PM PDT 24
Finished Apr 04 01:23:29 PM PDT 24
Peak memory 202160 kb
Host smart-5d19e584-b100-411a-81fa-086beed38edc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=209851024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrup
t_fixed.209851024
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.2799194774
Short name T497
Test name
Test status
Simulation time 492946353816 ps
CPU time 1128.5 seconds
Started Apr 04 01:19:12 PM PDT 24
Finished Apr 04 01:38:01 PM PDT 24
Peak memory 202336 kb
Host smart-b539fd43-d886-432d-9fe8-f3be41f41589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799194774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.2799194774
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.127567779
Short name T647
Test name
Test status
Simulation time 334865346870 ps
CPU time 196.61 seconds
Started Apr 04 01:19:11 PM PDT 24
Finished Apr 04 01:22:28 PM PDT 24
Peak memory 202188 kb
Host smart-2c70157d-2110-43d6-a514-598f8d24adb5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=127567779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe
d.127567779
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2873471608
Short name T171
Test name
Test status
Simulation time 565447997119 ps
CPU time 276.22 seconds
Started Apr 04 01:19:13 PM PDT 24
Finished Apr 04 01:23:50 PM PDT 24
Peak memory 202232 kb
Host smart-fc1e741f-ff44-4bed-8d09-ae0c0faf46c1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873471608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2873471608
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.266428576
Short name T471
Test name
Test status
Simulation time 202087502588 ps
CPU time 129.35 seconds
Started Apr 04 01:19:12 PM PDT 24
Finished Apr 04 01:21:22 PM PDT 24
Peak memory 202168 kb
Host smart-4a4c5bdd-620b-4aa8-b7e6-24480a12a15a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266428576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.266428576
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.3521661863
Short name T49
Test name
Test status
Simulation time 98390913994 ps
CPU time 536.69 seconds
Started Apr 04 01:19:21 PM PDT 24
Finished Apr 04 01:28:18 PM PDT 24
Peak memory 202568 kb
Host smart-754eef90-2a11-4674-8c9c-df07bd4539cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521661863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.3521661863
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3461266904
Short name T693
Test name
Test status
Simulation time 29411264161 ps
CPU time 6.88 seconds
Started Apr 04 01:19:22 PM PDT 24
Finished Apr 04 01:19:29 PM PDT 24
Peak memory 202020 kb
Host smart-59293452-6e10-48b2-97cd-c26566ba2b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461266904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3461266904
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3080100912
Short name T501
Test name
Test status
Simulation time 3300305900 ps
CPU time 1.86 seconds
Started Apr 04 01:19:20 PM PDT 24
Finished Apr 04 01:19:22 PM PDT 24
Peak memory 202072 kb
Host smart-c4b7f4c8-6ce8-4496-b6e2-1b9f4a6c6dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080100912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3080100912
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.555242046
Short name T463
Test name
Test status
Simulation time 5978375359 ps
CPU time 2.18 seconds
Started Apr 04 01:19:12 PM PDT 24
Finished Apr 04 01:19:15 PM PDT 24
Peak memory 202072 kb
Host smart-478e2be3-f665-4ebf-8f6f-239514421ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555242046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.555242046
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1636720831
Short name T757
Test name
Test status
Simulation time 371858541535 ps
CPU time 758.7 seconds
Started Apr 04 01:19:23 PM PDT 24
Finished Apr 04 01:32:02 PM PDT 24
Peak memory 213172 kb
Host smart-214b0e14-3afe-4331-b6d5-ce6bdc51bfc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636720831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1636720831
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3649135605
Short name T320
Test name
Test status
Simulation time 69837580182 ps
CPU time 146.96 seconds
Started Apr 04 01:19:22 PM PDT 24
Finished Apr 04 01:21:49 PM PDT 24
Peak memory 210948 kb
Host smart-e5340ea6-b09d-40c7-93a0-5a9e7520fdb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649135605 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3649135605
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1219530792
Short name T413
Test name
Test status
Simulation time 401668512 ps
CPU time 0.83 seconds
Started Apr 04 01:19:44 PM PDT 24
Finished Apr 04 01:19:45 PM PDT 24
Peak memory 201956 kb
Host smart-18f527a4-651a-4151-9e51-bc54df8d442f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219530792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1219530792
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.283151093
Short name T609
Test name
Test status
Simulation time 487073413933 ps
CPU time 570.43 seconds
Started Apr 04 01:19:32 PM PDT 24
Finished Apr 04 01:29:02 PM PDT 24
Peak memory 202348 kb
Host smart-6f531d37-01be-4d51-91e9-4fe6a88b2813
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283151093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gati
ng.283151093
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.750342196
Short name T129
Test name
Test status
Simulation time 323343396659 ps
CPU time 692.51 seconds
Started Apr 04 01:19:35 PM PDT 24
Finished Apr 04 01:31:08 PM PDT 24
Peak memory 202184 kb
Host smart-58d43ad0-ba4c-4339-bf48-2b16505518d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750342196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.750342196
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2838508737
Short name T660
Test name
Test status
Simulation time 484889167260 ps
CPU time 122.06 seconds
Started Apr 04 01:19:21 PM PDT 24
Finished Apr 04 01:21:23 PM PDT 24
Peak memory 202168 kb
Host smart-fb294a67-3a78-41f2-9640-c9d620287786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838508737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2838508737
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.269076883
Short name T535
Test name
Test status
Simulation time 330641689657 ps
CPU time 721.53 seconds
Started Apr 04 01:19:23 PM PDT 24
Finished Apr 04 01:31:25 PM PDT 24
Peak memory 202132 kb
Host smart-751327ce-eef0-4fa7-bd73-539940cc114e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=269076883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.269076883
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.2921142538
Short name T263
Test name
Test status
Simulation time 488040189211 ps
CPU time 1192.96 seconds
Started Apr 04 01:19:21 PM PDT 24
Finished Apr 04 01:39:15 PM PDT 24
Peak memory 202216 kb
Host smart-c504830b-f309-487f-9c79-cc12531086cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921142538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2921142538
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1095600380
Short name T636
Test name
Test status
Simulation time 161773044543 ps
CPU time 37.61 seconds
Started Apr 04 01:19:22 PM PDT 24
Finished Apr 04 01:20:00 PM PDT 24
Peak memory 202192 kb
Host smart-dca5728f-2909-4a71-b4fb-9a60e7e54a08
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095600380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1095600380
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3468746334
Short name T731
Test name
Test status
Simulation time 542744058995 ps
CPU time 334.23 seconds
Started Apr 04 01:19:33 PM PDT 24
Finished Apr 04 01:25:08 PM PDT 24
Peak memory 202156 kb
Host smart-4737e0b9-7dc1-483c-b557-f0eebc8ee374
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468746334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3468746334
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.747462930
Short name T466
Test name
Test status
Simulation time 200106660221 ps
CPU time 488.23 seconds
Started Apr 04 01:19:32 PM PDT 24
Finished Apr 04 01:27:40 PM PDT 24
Peak memory 202236 kb
Host smart-f29b52c0-6509-4dd9-a373-e69b62a21ac8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747462930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
adc_ctrl_filters_wakeup_fixed.747462930
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.276310226
Short name T347
Test name
Test status
Simulation time 134120797730 ps
CPU time 404.61 seconds
Started Apr 04 01:19:36 PM PDT 24
Finished Apr 04 01:26:20 PM PDT 24
Peak memory 202572 kb
Host smart-a68f3462-2417-4596-baf9-778e22d6865f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276310226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.276310226
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.308119326
Short name T540
Test name
Test status
Simulation time 41544563317 ps
CPU time 5.57 seconds
Started Apr 04 01:19:32 PM PDT 24
Finished Apr 04 01:19:38 PM PDT 24
Peak memory 202056 kb
Host smart-4c67c62d-fda4-4c75-a5ec-9f5a4d9b87d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308119326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.308119326
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3971771103
Short name T9
Test name
Test status
Simulation time 2766477955 ps
CPU time 4.11 seconds
Started Apr 04 01:19:35 PM PDT 24
Finished Apr 04 01:19:40 PM PDT 24
Peak memory 201988 kb
Host smart-bbfe7e17-08b8-4931-ac1e-4f55185e3552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971771103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3971771103
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2217598763
Short name T406
Test name
Test status
Simulation time 5939344921 ps
CPU time 4.25 seconds
Started Apr 04 01:19:23 PM PDT 24
Finished Apr 04 01:19:28 PM PDT 24
Peak memory 202100 kb
Host smart-7667d4f7-ff73-484d-9ab0-f634a0ecf499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217598763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2217598763
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.707595291
Short name T321
Test name
Test status
Simulation time 432519072032 ps
CPU time 508.72 seconds
Started Apr 04 01:19:42 PM PDT 24
Finished Apr 04 01:28:11 PM PDT 24
Peak memory 202228 kb
Host smart-f3a75238-9ff0-4f47-b384-4ad25000e962
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707595291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.
707595291
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1881312704
Short name T514
Test name
Test status
Simulation time 9569009157 ps
CPU time 11.95 seconds
Started Apr 04 01:19:32 PM PDT 24
Finished Apr 04 01:19:44 PM PDT 24
Peak memory 202412 kb
Host smart-6d10d65f-9466-437c-b272-1b1cd800ef76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881312704 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1881312704
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.1643392058
Short name T624
Test name
Test status
Simulation time 286432778 ps
CPU time 0.99 seconds
Started Apr 04 01:20:07 PM PDT 24
Finished Apr 04 01:20:08 PM PDT 24
Peak memory 201980 kb
Host smart-ad5c2596-0ac7-4787-8308-5f0a647869d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643392058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1643392058
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2455124930
Short name T522
Test name
Test status
Simulation time 190309123199 ps
CPU time 431.25 seconds
Started Apr 04 01:19:58 PM PDT 24
Finished Apr 04 01:27:09 PM PDT 24
Peak memory 202368 kb
Host smart-059a838c-6a2b-4d8a-bb36-bfef1db004bf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455124930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2455124930
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2796512711
Short name T208
Test name
Test status
Simulation time 347506460394 ps
CPU time 804.12 seconds
Started Apr 04 01:19:58 PM PDT 24
Finished Apr 04 01:33:23 PM PDT 24
Peak memory 202304 kb
Host smart-fe30c099-2cf4-4518-bdfe-fccdd261306a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796512711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2796512711
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3814139038
Short name T176
Test name
Test status
Simulation time 336700159420 ps
CPU time 50.45 seconds
Started Apr 04 01:19:43 PM PDT 24
Finished Apr 04 01:20:33 PM PDT 24
Peak memory 202344 kb
Host smart-53f55eac-b7ae-4df1-a2a6-01a63724d76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814139038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3814139038
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2056455403
Short name T91
Test name
Test status
Simulation time 502250890897 ps
CPU time 125.6 seconds
Started Apr 04 01:19:44 PM PDT 24
Finished Apr 04 01:21:49 PM PDT 24
Peak memory 202276 kb
Host smart-0a610a7e-3b8e-443d-aeb3-c5345c4ae41b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056455403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2056455403
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.3800197889
Short name T228
Test name
Test status
Simulation time 170499055001 ps
CPU time 74.31 seconds
Started Apr 04 01:19:43 PM PDT 24
Finished Apr 04 01:20:58 PM PDT 24
Peak memory 202416 kb
Host smart-6452259c-e2d8-459c-9b31-aecc77fa53f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800197889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3800197889
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3175030948
Short name T538
Test name
Test status
Simulation time 503960167494 ps
CPU time 605.85 seconds
Started Apr 04 01:19:42 PM PDT 24
Finished Apr 04 01:29:48 PM PDT 24
Peak memory 202264 kb
Host smart-1dc68114-e653-4f43-8d91-e2700fc08571
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175030948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3175030948
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.2504217015
Short name T172
Test name
Test status
Simulation time 544962551569 ps
CPU time 333.84 seconds
Started Apr 04 01:19:50 PM PDT 24
Finished Apr 04 01:25:24 PM PDT 24
Peak memory 202292 kb
Host smart-0a630e20-aa52-4459-bfe3-16043ec725cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504217015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.2504217015
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2015386327
Short name T499
Test name
Test status
Simulation time 205657516149 ps
CPU time 45.58 seconds
Started Apr 04 01:19:42 PM PDT 24
Finished Apr 04 01:20:28 PM PDT 24
Peak memory 202196 kb
Host smart-1ee7d2cc-c4ce-4ba2-a831-3a614b35a5d9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015386327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2015386327
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1358354409
Short name T737
Test name
Test status
Simulation time 116214286540 ps
CPU time 441.74 seconds
Started Apr 04 01:20:00 PM PDT 24
Finished Apr 04 01:27:23 PM PDT 24
Peak memory 202560 kb
Host smart-380199d8-1dae-45a5-8385-6443a327e8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358354409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1358354409
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.3625373082
Short name T383
Test name
Test status
Simulation time 38067535698 ps
CPU time 15.19 seconds
Started Apr 04 01:19:58 PM PDT 24
Finished Apr 04 01:20:13 PM PDT 24
Peak memory 202120 kb
Host smart-047bcccd-9035-47d5-8663-c6f318fa89b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625373082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.3625373082
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.487250297
Short name T431
Test name
Test status
Simulation time 5160439160 ps
CPU time 7.44 seconds
Started Apr 04 01:19:59 PM PDT 24
Finished Apr 04 01:20:06 PM PDT 24
Peak memory 202028 kb
Host smart-413530e2-90f9-4222-8409-9849f3e04f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487250297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.487250297
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.4113527693
Short name T754
Test name
Test status
Simulation time 5736844516 ps
CPU time 7.53 seconds
Started Apr 04 01:19:43 PM PDT 24
Finished Apr 04 01:19:50 PM PDT 24
Peak memory 202012 kb
Host smart-e9782711-5341-42ca-b147-dcaa1990a79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113527693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.4113527693
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.4206914105
Short name T214
Test name
Test status
Simulation time 347802356810 ps
CPU time 767.08 seconds
Started Apr 04 01:20:08 PM PDT 24
Finished Apr 04 01:32:56 PM PDT 24
Peak memory 202284 kb
Host smart-b4a8bd49-d579-449d-b5d7-75fa60dcd6bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206914105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.4206914105
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.1191201782
Short name T510
Test name
Test status
Simulation time 432254263 ps
CPU time 0.79 seconds
Started Apr 04 01:20:17 PM PDT 24
Finished Apr 04 01:20:18 PM PDT 24
Peak memory 201980 kb
Host smart-7ab0679c-0e5d-4272-a99f-786e5fe255d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191201782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.1191201782
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1578901928
Short name T296
Test name
Test status
Simulation time 174477122283 ps
CPU time 409.39 seconds
Started Apr 04 01:20:09 PM PDT 24
Finished Apr 04 01:26:59 PM PDT 24
Peak memory 202252 kb
Host smart-34c084c6-eb58-402e-b1b3-08efa6a342b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578901928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1578901928
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.2755600144
Short name T265
Test name
Test status
Simulation time 348138747579 ps
CPU time 201.14 seconds
Started Apr 04 01:20:10 PM PDT 24
Finished Apr 04 01:23:31 PM PDT 24
Peak memory 202296 kb
Host smart-a09115b5-4e38-444f-bfc8-7010fbc665ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755600144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2755600144
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1151593173
Short name T662
Test name
Test status
Simulation time 338890881716 ps
CPU time 217.35 seconds
Started Apr 04 01:20:10 PM PDT 24
Finished Apr 04 01:23:47 PM PDT 24
Peak memory 202220 kb
Host smart-482f8726-7113-4092-8dbd-672a481f61f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151593173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1151593173
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.3365838824
Short name T602
Test name
Test status
Simulation time 158722447321 ps
CPU time 190.38 seconds
Started Apr 04 01:20:09 PM PDT 24
Finished Apr 04 01:23:20 PM PDT 24
Peak memory 202260 kb
Host smart-9305af1a-e681-4bcb-9f10-7a0ffaa08f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365838824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.3365838824
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1206444453
Short name T417
Test name
Test status
Simulation time 333973576751 ps
CPU time 214.48 seconds
Started Apr 04 01:20:08 PM PDT 24
Finished Apr 04 01:23:43 PM PDT 24
Peak memory 202232 kb
Host smart-629c6c65-e7b9-457a-8506-49ae3b9729c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206444453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1206444453
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.607920846
Short name T314
Test name
Test status
Simulation time 179600407924 ps
CPU time 228.87 seconds
Started Apr 04 01:20:08 PM PDT 24
Finished Apr 04 01:23:57 PM PDT 24
Peak memory 202256 kb
Host smart-2808f99c-972f-43eb-b959-f16b3074907a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607920846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_
wakeup.607920846
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3876056495
Short name T354
Test name
Test status
Simulation time 412218674270 ps
CPU time 1002.24 seconds
Started Apr 04 01:20:06 PM PDT 24
Finished Apr 04 01:36:49 PM PDT 24
Peak memory 202248 kb
Host smart-5da5c53f-fc95-40e1-a9a0-7a8517b5036a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876056495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3876056495
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.4186129745
Short name T468
Test name
Test status
Simulation time 102961592499 ps
CPU time 402.94 seconds
Started Apr 04 01:20:09 PM PDT 24
Finished Apr 04 01:26:53 PM PDT 24
Peak memory 202624 kb
Host smart-15d76737-700b-4da4-aa27-545f540d88a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186129745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.4186129745
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1462638099
Short name T578
Test name
Test status
Simulation time 36886023696 ps
CPU time 90.64 seconds
Started Apr 04 01:20:11 PM PDT 24
Finished Apr 04 01:21:42 PM PDT 24
Peak memory 202044 kb
Host smart-f021257a-244a-482f-a738-684b7590531b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462638099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1462638099
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1814852058
Short name T356
Test name
Test status
Simulation time 3819664040 ps
CPU time 9.87 seconds
Started Apr 04 01:20:08 PM PDT 24
Finished Apr 04 01:20:18 PM PDT 24
Peak memory 202028 kb
Host smart-17038f0f-df5a-4604-a0b7-fda7887cf7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814852058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1814852058
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2950434870
Short name T773
Test name
Test status
Simulation time 6066453376 ps
CPU time 15.74 seconds
Started Apr 04 01:20:08 PM PDT 24
Finished Apr 04 01:20:24 PM PDT 24
Peak memory 202020 kb
Host smart-0ae8f69b-b36b-47b3-9f8f-c8c52645140e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950434870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2950434870
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.4125122199
Short name T257
Test name
Test status
Simulation time 707738383795 ps
CPU time 831.1 seconds
Started Apr 04 01:20:17 PM PDT 24
Finished Apr 04 01:34:08 PM PDT 24
Peak memory 202256 kb
Host smart-2d787d75-1320-4e4f-b507-7ef3e04e9dfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125122199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.4125122199
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2803792737
Short name T323
Test name
Test status
Simulation time 447573831310 ps
CPU time 598.69 seconds
Started Apr 04 01:20:11 PM PDT 24
Finished Apr 04 01:30:10 PM PDT 24
Peak memory 217068 kb
Host smart-9c7a3323-4d83-451e-834c-7ae78484c589
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803792737 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2803792737
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3173951523
Short name T594
Test name
Test status
Simulation time 551274914 ps
CPU time 0.76 seconds
Started Apr 04 01:20:25 PM PDT 24
Finished Apr 04 01:20:26 PM PDT 24
Peak memory 201960 kb
Host smart-5315ca5a-b8b1-492a-b686-4ca9b49392d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173951523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3173951523
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.3594814604
Short name T774
Test name
Test status
Simulation time 332023653395 ps
CPU time 324.5 seconds
Started Apr 04 01:20:17 PM PDT 24
Finished Apr 04 01:25:41 PM PDT 24
Peak memory 202248 kb
Host smart-2a677eb0-b28c-40c7-9e56-70591a9a5966
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594814604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.3594814604
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1547135480
Short name T123
Test name
Test status
Simulation time 159410757890 ps
CPU time 38.99 seconds
Started Apr 04 01:20:16 PM PDT 24
Finished Apr 04 01:20:56 PM PDT 24
Peak memory 202272 kb
Host smart-70006e84-c6e7-481c-860b-2653ee797f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547135480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1547135480
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.4114942331
Short name T709
Test name
Test status
Simulation time 163555515610 ps
CPU time 168.45 seconds
Started Apr 04 01:20:17 PM PDT 24
Finished Apr 04 01:23:05 PM PDT 24
Peak memory 202248 kb
Host smart-45446203-200e-4a22-a747-8b817aa72dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114942331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.4114942331
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2451049732
Short name T363
Test name
Test status
Simulation time 490478963116 ps
CPU time 442.75 seconds
Started Apr 04 01:20:18 PM PDT 24
Finished Apr 04 01:27:41 PM PDT 24
Peak memory 202236 kb
Host smart-67eb26b3-fc98-4e44-a81d-bf6a2ae5e23d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451049732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2451049732
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.865368040
Short name T668
Test name
Test status
Simulation time 486727005195 ps
CPU time 926.66 seconds
Started Apr 04 01:20:18 PM PDT 24
Finished Apr 04 01:35:45 PM PDT 24
Peak memory 202196 kb
Host smart-6de75df0-b6c5-4ab8-8b09-aab3a84e1e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865368040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.865368040
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3352946780
Short name T387
Test name
Test status
Simulation time 324640581606 ps
CPU time 188.1 seconds
Started Apr 04 01:20:16 PM PDT 24
Finished Apr 04 01:23:25 PM PDT 24
Peak memory 202204 kb
Host smart-9b639de2-4b0a-4288-a2ab-4866b79c854b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352946780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3352946780
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.3878557994
Short name T730
Test name
Test status
Simulation time 180346173046 ps
CPU time 211.08 seconds
Started Apr 04 01:20:17 PM PDT 24
Finished Apr 04 01:23:48 PM PDT 24
Peak memory 202272 kb
Host smart-d65e74d9-7b5a-43d2-a9ca-87b81fb995e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878557994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.3878557994
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3273163061
Short name T384
Test name
Test status
Simulation time 199092444451 ps
CPU time 220.45 seconds
Started Apr 04 01:20:18 PM PDT 24
Finished Apr 04 01:23:58 PM PDT 24
Peak memory 202196 kb
Host smart-3cd185c6-0003-4aee-a994-af7274a0649a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273163061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3273163061
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3823358207
Short name T350
Test name
Test status
Simulation time 111645226988 ps
CPU time 380.85 seconds
Started Apr 04 01:20:26 PM PDT 24
Finished Apr 04 01:26:48 PM PDT 24
Peak memory 202548 kb
Host smart-e7b02a06-8018-491c-95bd-d0a71dda6e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823358207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3823358207
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2585023418
Short name T705
Test name
Test status
Simulation time 31716493467 ps
CPU time 19.72 seconds
Started Apr 04 01:20:25 PM PDT 24
Finished Apr 04 01:20:45 PM PDT 24
Peak memory 202060 kb
Host smart-4577d6d6-cbef-4a20-93b9-a4b7ccaf5928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585023418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2585023418
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.777107423
Short name T358
Test name
Test status
Simulation time 3712051350 ps
CPU time 2.79 seconds
Started Apr 04 01:20:26 PM PDT 24
Finished Apr 04 01:20:29 PM PDT 24
Peak memory 202032 kb
Host smart-f3716d46-6f55-45a2-bc0e-e13bb2eb6fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777107423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.777107423
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.962525091
Short name T637
Test name
Test status
Simulation time 6053155700 ps
CPU time 4.88 seconds
Started Apr 04 01:20:17 PM PDT 24
Finished Apr 04 01:20:22 PM PDT 24
Peak memory 202028 kb
Host smart-94f5e8ec-71d4-4751-a7b3-4ce59e2b3d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962525091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.962525091
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1973315843
Short name T155
Test name
Test status
Simulation time 457966184150 ps
CPU time 473.29 seconds
Started Apr 04 01:20:24 PM PDT 24
Finished Apr 04 01:28:18 PM PDT 24
Peak memory 210776 kb
Host smart-3d1dad0b-9e81-4cc8-8752-7995438419d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973315843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1973315843
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.4080294134
Short name T23
Test name
Test status
Simulation time 49785609018 ps
CPU time 31.27 seconds
Started Apr 04 01:20:27 PM PDT 24
Finished Apr 04 01:20:58 PM PDT 24
Peak memory 210612 kb
Host smart-28a36514-5300-4f54-be41-89199b602740
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080294134 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.4080294134
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.144392063
Short name T434
Test name
Test status
Simulation time 532806117 ps
CPU time 1.24 seconds
Started Apr 04 01:20:41 PM PDT 24
Finished Apr 04 01:20:43 PM PDT 24
Peak memory 201872 kb
Host smart-aa60e663-e0d5-4d33-abf4-661c6136fa3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144392063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.144392063
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1422179733
Short name T255
Test name
Test status
Simulation time 168599957788 ps
CPU time 184.98 seconds
Started Apr 04 01:20:35 PM PDT 24
Finished Apr 04 01:23:41 PM PDT 24
Peak memory 202180 kb
Host smart-400f7a08-4405-4861-bb98-d9a58a562c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422179733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1422179733
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2310456787
Short name T720
Test name
Test status
Simulation time 168813466473 ps
CPU time 379.18 seconds
Started Apr 04 01:20:26 PM PDT 24
Finished Apr 04 01:26:45 PM PDT 24
Peak memory 202172 kb
Host smart-8357f477-7c5b-4e74-a905-09fecdff048a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310456787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2310456787
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.854234392
Short name T524
Test name
Test status
Simulation time 330309212131 ps
CPU time 199.91 seconds
Started Apr 04 01:20:24 PM PDT 24
Finished Apr 04 01:23:44 PM PDT 24
Peak memory 202332 kb
Host smart-f167e748-51e8-48b0-b2f0-003a1fb066a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=854234392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrup
t_fixed.854234392
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.3651243345
Short name T710
Test name
Test status
Simulation time 490849976603 ps
CPU time 80.43 seconds
Started Apr 04 01:20:26 PM PDT 24
Finished Apr 04 01:21:47 PM PDT 24
Peak memory 202316 kb
Host smart-c0fd2278-9994-40c8-a6ab-b33aad2c811d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651243345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3651243345
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.278967438
Short name T90
Test name
Test status
Simulation time 325962210958 ps
CPU time 196.59 seconds
Started Apr 04 01:20:26 PM PDT 24
Finished Apr 04 01:23:43 PM PDT 24
Peak memory 202168 kb
Host smart-ecd460e7-b0fe-4fe0-b5c7-a8b12a03ee12
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=278967438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixe
d.278967438
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.1801613802
Short name T248
Test name
Test status
Simulation time 589755401620 ps
CPU time 278.62 seconds
Started Apr 04 01:20:25 PM PDT 24
Finished Apr 04 01:25:04 PM PDT 24
Peak memory 202104 kb
Host smart-f67eb865-06a6-448c-94f7-f9d688daecc1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801613802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.1801613802
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.2448991620
Short name T167
Test name
Test status
Simulation time 197001070172 ps
CPU time 132.48 seconds
Started Apr 04 01:20:27 PM PDT 24
Finished Apr 04 01:22:40 PM PDT 24
Peak memory 202172 kb
Host smart-718fb628-04c4-4546-a94a-0b1d7137b62a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448991620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.2448991620
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.843475626
Short name T351
Test name
Test status
Simulation time 61014146664 ps
CPU time 338.17 seconds
Started Apr 04 01:20:33 PM PDT 24
Finished Apr 04 01:26:12 PM PDT 24
Peak memory 202656 kb
Host smart-3ffb27ac-3bcf-41dd-b416-caa86fee52f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843475626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.843475626
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.4043076706
Short name T480
Test name
Test status
Simulation time 27433686482 ps
CPU time 31.74 seconds
Started Apr 04 01:20:34 PM PDT 24
Finished Apr 04 01:21:06 PM PDT 24
Peak memory 202064 kb
Host smart-b0f5b5d7-0b38-44e0-b763-e3f64aa6e72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043076706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.4043076706
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.3025992734
Short name T401
Test name
Test status
Simulation time 2828961109 ps
CPU time 7.34 seconds
Started Apr 04 01:20:32 PM PDT 24
Finished Apr 04 01:20:40 PM PDT 24
Peak memory 202020 kb
Host smart-bb12710f-8d31-4c71-a5c9-df6dae0771d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025992734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.3025992734
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.4208527918
Short name T670
Test name
Test status
Simulation time 5979801039 ps
CPU time 13.24 seconds
Started Apr 04 01:20:27 PM PDT 24
Finished Apr 04 01:20:40 PM PDT 24
Peak memory 202068 kb
Host smart-2bbc2034-9374-4ffc-90a5-525912838dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208527918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.4208527918
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1532676370
Short name T318
Test name
Test status
Simulation time 226535380833 ps
CPU time 527.32 seconds
Started Apr 04 01:20:31 PM PDT 24
Finished Apr 04 01:29:19 PM PDT 24
Peak memory 202264 kb
Host smart-7a13456d-9c1f-41f2-85c9-c5fa6e0eeaab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532676370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1532676370
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.2892078631
Short name T759
Test name
Test status
Simulation time 69482779621 ps
CPU time 113.78 seconds
Started Apr 04 01:20:34 PM PDT 24
Finished Apr 04 01:22:28 PM PDT 24
Peak memory 210896 kb
Host smart-ba10f995-b85f-4112-a084-cd661ef52a9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892078631 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.2892078631
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.237417420
Short name T388
Test name
Test status
Simulation time 320950923 ps
CPU time 0.97 seconds
Started Apr 04 01:07:43 PM PDT 24
Finished Apr 04 01:07:44 PM PDT 24
Peak memory 201940 kb
Host smart-e71ab14f-787a-408b-9a28-a13c5a09eebd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237417420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.237417420
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1021730676
Short name T246
Test name
Test status
Simulation time 521251915494 ps
CPU time 406.25 seconds
Started Apr 04 01:07:29 PM PDT 24
Finished Apr 04 01:14:19 PM PDT 24
Peak memory 202228 kb
Host smart-8c89885e-548d-4ec4-9196-c1a5b3da7070
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021730676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1021730676
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.3887843120
Short name T220
Test name
Test status
Simulation time 527623114046 ps
CPU time 334.36 seconds
Started Apr 04 01:07:41 PM PDT 24
Finished Apr 04 01:13:16 PM PDT 24
Peak memory 202152 kb
Host smart-29897ada-8361-4572-940f-2c022f3cffe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887843120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3887843120
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.490839384
Short name T494
Test name
Test status
Simulation time 161795887279 ps
CPU time 342.87 seconds
Started Apr 04 01:07:15 PM PDT 24
Finished Apr 04 01:12:58 PM PDT 24
Peak memory 202296 kb
Host smart-5c90354d-28f2-4c6c-b81b-28c713522dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490839384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.490839384
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.456433645
Short name T560
Test name
Test status
Simulation time 503435827837 ps
CPU time 326.56 seconds
Started Apr 04 01:07:30 PM PDT 24
Finished Apr 04 01:12:59 PM PDT 24
Peak memory 202292 kb
Host smart-4aaaac75-af22-48dc-9478-d080e6961a80
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=456433645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt
_fixed.456433645
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.6199070
Short name T291
Test name
Test status
Simulation time 331324948670 ps
CPU time 742.39 seconds
Started Apr 04 01:07:11 PM PDT 24
Finished Apr 04 01:19:34 PM PDT 24
Peak memory 202292 kb
Host smart-2b614132-50e6-4c69-bb13-22a2c3c7f65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6199070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.6199070
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.884558646
Short name T719
Test name
Test status
Simulation time 165476733550 ps
CPU time 44.37 seconds
Started Apr 04 01:07:13 PM PDT 24
Finished Apr 04 01:07:59 PM PDT 24
Peak memory 202312 kb
Host smart-3fc9d387-1e8d-4845-bb71-fbcbb3678c27
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=884558646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.884558646
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3622449188
Short name T324
Test name
Test status
Simulation time 551525133142 ps
CPU time 1259.86 seconds
Started Apr 04 01:07:31 PM PDT 24
Finished Apr 04 01:28:33 PM PDT 24
Peak memory 202400 kb
Host smart-09a4d005-ded5-4b3a-80d0-8f0035e4fcec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622449188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3622449188
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.229170698
Short name T577
Test name
Test status
Simulation time 389242753418 ps
CPU time 905.44 seconds
Started Apr 04 01:07:29 PM PDT 24
Finished Apr 04 01:22:38 PM PDT 24
Peak memory 202260 kb
Host smart-8e44ae86-0567-46ba-b2a1-55fcb3e9cd47
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229170698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.a
dc_ctrl_filters_wakeup_fixed.229170698
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3746244647
Short name T344
Test name
Test status
Simulation time 86436627981 ps
CPU time 452.27 seconds
Started Apr 04 01:07:45 PM PDT 24
Finished Apr 04 01:15:17 PM PDT 24
Peak memory 202636 kb
Host smart-b91b1a4b-50ad-4fff-a65d-08a6d0091142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746244647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3746244647
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.4221785757
Short name T437
Test name
Test status
Simulation time 38245637348 ps
CPU time 84.06 seconds
Started Apr 04 01:07:43 PM PDT 24
Finished Apr 04 01:09:07 PM PDT 24
Peak memory 202072 kb
Host smart-a0fb64b2-722b-450d-830b-64e2b7c3a141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221785757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.4221785757
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.4167178655
Short name T485
Test name
Test status
Simulation time 3803028966 ps
CPU time 5.01 seconds
Started Apr 04 01:07:44 PM PDT 24
Finished Apr 04 01:07:49 PM PDT 24
Peak memory 201996 kb
Host smart-e979cedd-3b9d-4f36-a621-56df5f1b6301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167178655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.4167178655
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2634933772
Short name T73
Test name
Test status
Simulation time 8350033436 ps
CPU time 2.92 seconds
Started Apr 04 01:07:43 PM PDT 24
Finished Apr 04 01:07:46 PM PDT 24
Peak memory 218884 kb
Host smart-442defd9-ce09-4373-b788-9622ba9dea40
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634933772 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2634933772
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.1886812191
Short name T2
Test name
Test status
Simulation time 5839995310 ps
CPU time 15.44 seconds
Started Apr 04 01:07:13 PM PDT 24
Finished Apr 04 01:07:30 PM PDT 24
Peak memory 201996 kb
Host smart-5cffec4a-4b5d-4473-9d7c-b0551ca855e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886812191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1886812191
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.48566456
Short name T308
Test name
Test status
Simulation time 35596432841 ps
CPU time 49.4 seconds
Started Apr 04 01:07:43 PM PDT 24
Finished Apr 04 01:08:32 PM PDT 24
Peak memory 210632 kb
Host smart-1d06eac0-8513-497a-af98-1224fe2374d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48566456 -assert nopos
tproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.48566456
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2468227073
Short name T31
Test name
Test status
Simulation time 460883025 ps
CPU time 1.56 seconds
Started Apr 04 01:21:03 PM PDT 24
Finished Apr 04 01:21:04 PM PDT 24
Peak memory 201988 kb
Host smart-ea83414d-145a-4e85-b75e-192a727dbf18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468227073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2468227073
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.2966161278
Short name T198
Test name
Test status
Simulation time 164206766488 ps
CPU time 101.98 seconds
Started Apr 04 01:20:56 PM PDT 24
Finished Apr 04 01:22:38 PM PDT 24
Peak memory 202220 kb
Host smart-25753391-b1ff-4ea6-a6d0-a15ba2c72bce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966161278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.2966161278
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.313599661
Short name T43
Test name
Test status
Simulation time 157665375910 ps
CPU time 368.69 seconds
Started Apr 04 01:20:54 PM PDT 24
Finished Apr 04 01:27:03 PM PDT 24
Peak memory 202316 kb
Host smart-f0d0f70b-1526-4890-b7c6-134a3130d4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313599661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.313599661
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1515673371
Short name T750
Test name
Test status
Simulation time 490211367916 ps
CPU time 316.14 seconds
Started Apr 04 01:20:40 PM PDT 24
Finished Apr 04 01:25:57 PM PDT 24
Peak memory 202212 kb
Host smart-01592caa-cbbf-4ded-b308-f2f26d5fd986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515673371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1515673371
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2184002028
Short name T150
Test name
Test status
Simulation time 167591751799 ps
CPU time 39.47 seconds
Started Apr 04 01:20:43 PM PDT 24
Finished Apr 04 01:21:23 PM PDT 24
Peak memory 202152 kb
Host smart-2ce1c3ab-200e-4547-b543-97f70d82b8f4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184002028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2184002028
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.516647516
Short name T133
Test name
Test status
Simulation time 328278007218 ps
CPU time 732.45 seconds
Started Apr 04 01:20:42 PM PDT 24
Finished Apr 04 01:32:55 PM PDT 24
Peak memory 202248 kb
Host smart-1725cf10-3d36-42ce-902a-9c7019767eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516647516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.516647516
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.1567878164
Short name T769
Test name
Test status
Simulation time 499384500466 ps
CPU time 105.16 seconds
Started Apr 04 01:20:43 PM PDT 24
Finished Apr 04 01:22:28 PM PDT 24
Peak memory 202228 kb
Host smart-86e22306-904b-4551-b665-a3b11e615515
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567878164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.1567878164
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.3988714332
Short name T305
Test name
Test status
Simulation time 167506864372 ps
CPU time 139.35 seconds
Started Apr 04 01:20:44 PM PDT 24
Finished Apr 04 01:23:04 PM PDT 24
Peak memory 202184 kb
Host smart-5e40118a-775f-4b63-8b91-7ad24b2e5ca2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988714332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.3988714332
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2940511700
Short name T452
Test name
Test status
Simulation time 593067834202 ps
CPU time 611.29 seconds
Started Apr 04 01:20:55 PM PDT 24
Finished Apr 04 01:31:06 PM PDT 24
Peak memory 202232 kb
Host smart-9983066c-d91a-4753-b099-b0b7fe60bfb1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940511700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2940511700
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.1562827146
Short name T487
Test name
Test status
Simulation time 126263929301 ps
CPU time 517.5 seconds
Started Apr 04 01:20:55 PM PDT 24
Finished Apr 04 01:29:33 PM PDT 24
Peak memory 202652 kb
Host smart-98fb1e1c-1c9f-44cb-8d13-725275ce0bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562827146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1562827146
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1769611681
Short name T169
Test name
Test status
Simulation time 30577921894 ps
CPU time 62.99 seconds
Started Apr 04 01:20:54 PM PDT 24
Finished Apr 04 01:21:57 PM PDT 24
Peak memory 202040 kb
Host smart-45137d9d-6910-45ac-bf8c-de93460bc856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769611681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1769611681
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3674407132
Short name T393
Test name
Test status
Simulation time 4724255842 ps
CPU time 3.43 seconds
Started Apr 04 01:20:54 PM PDT 24
Finished Apr 04 01:20:57 PM PDT 24
Peak memory 202072 kb
Host smart-8f8531a9-662a-42b2-96c3-99311b81f93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674407132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3674407132
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.2632428919
Short name T571
Test name
Test status
Simulation time 5826327152 ps
CPU time 15.34 seconds
Started Apr 04 01:20:42 PM PDT 24
Finished Apr 04 01:20:58 PM PDT 24
Peak memory 202016 kb
Host smart-05d3dae0-9980-4b09-aa79-876def5be195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632428919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.2632428919
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.4243184630
Short name T301
Test name
Test status
Simulation time 234655471372 ps
CPU time 149.26 seconds
Started Apr 04 01:21:05 PM PDT 24
Finished Apr 04 01:23:34 PM PDT 24
Peak memory 202244 kb
Host smart-d33eb297-8764-41df-8e95-075699b786d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243184630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.4243184630
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.648905103
Short name T292
Test name
Test status
Simulation time 42663356088 ps
CPU time 98.19 seconds
Started Apr 04 01:20:59 PM PDT 24
Finished Apr 04 01:22:37 PM PDT 24
Peak memory 210880 kb
Host smart-d565e7f8-531a-4ec3-8ae4-3ea42688a8c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648905103 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.648905103
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.4203186166
Short name T403
Test name
Test status
Simulation time 399153893 ps
CPU time 0.82 seconds
Started Apr 04 01:21:15 PM PDT 24
Finished Apr 04 01:21:16 PM PDT 24
Peak memory 201908 kb
Host smart-a4eabbab-ed00-4c76-8bdf-c7d3f52adeac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203186166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.4203186166
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.450369792
Short name T205
Test name
Test status
Simulation time 397233383177 ps
CPU time 952.82 seconds
Started Apr 04 01:21:06 PM PDT 24
Finished Apr 04 01:36:59 PM PDT 24
Peak memory 202264 kb
Host smart-0084ff3c-9292-47a7-9c74-4f0d3a4e2c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450369792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.450369792
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1611821698
Short name T722
Test name
Test status
Simulation time 159687292000 ps
CPU time 34.05 seconds
Started Apr 04 01:21:03 PM PDT 24
Finished Apr 04 01:21:38 PM PDT 24
Peak memory 202164 kb
Host smart-1db59978-4082-40a9-93da-e6ee8301e10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611821698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1611821698
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.2494514137
Short name T777
Test name
Test status
Simulation time 329817467189 ps
CPU time 169.06 seconds
Started Apr 04 01:21:03 PM PDT 24
Finished Apr 04 01:23:52 PM PDT 24
Peak memory 202232 kb
Host smart-077e02e3-683c-4a81-ba12-e97f81c26ec6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494514137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.2494514137
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.3623183882
Short name T655
Test name
Test status
Simulation time 493916127366 ps
CPU time 599.31 seconds
Started Apr 04 01:21:05 PM PDT 24
Finished Apr 04 01:31:04 PM PDT 24
Peak memory 202320 kb
Host smart-747b671b-b271-4d60-a6d9-baec3aca5d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623183882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.3623183882
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2042574644
Short name T525
Test name
Test status
Simulation time 490786675367 ps
CPU time 455.54 seconds
Started Apr 04 01:21:05 PM PDT 24
Finished Apr 04 01:28:40 PM PDT 24
Peak memory 202116 kb
Host smart-c583e661-3501-4b9b-b298-68f8738c26d3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042574644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2042574644
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.1276604411
Short name T569
Test name
Test status
Simulation time 192148229492 ps
CPU time 84.4 seconds
Started Apr 04 01:21:04 PM PDT 24
Finished Apr 04 01:22:29 PM PDT 24
Peak memory 202180 kb
Host smart-0bdfb876-178f-488a-a982-3e8b1188cacc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276604411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.1276604411
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.648765668
Short name T619
Test name
Test status
Simulation time 202863048567 ps
CPU time 443.09 seconds
Started Apr 04 01:21:04 PM PDT 24
Finished Apr 04 01:28:27 PM PDT 24
Peak memory 202320 kb
Host smart-2837c03f-9d7b-4454-994b-676394fb9bab
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648765668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
adc_ctrl_filters_wakeup_fixed.648765668
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3598024393
Short name T708
Test name
Test status
Simulation time 109267290667 ps
CPU time 464.1 seconds
Started Apr 04 01:21:15 PM PDT 24
Finished Apr 04 01:28:59 PM PDT 24
Peak memory 202612 kb
Host smart-faa50ef3-d56e-478f-bac1-a04bc5578de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598024393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3598024393
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.151314751
Short name T93
Test name
Test status
Simulation time 41404659650 ps
CPU time 92.72 seconds
Started Apr 04 01:21:14 PM PDT 24
Finished Apr 04 01:22:47 PM PDT 24
Peak memory 202080 kb
Host smart-8b8b2388-7d69-4b85-9f90-bf73d711906b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151314751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.151314751
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.743399049
Short name T767
Test name
Test status
Simulation time 4665607839 ps
CPU time 11.65 seconds
Started Apr 04 01:21:05 PM PDT 24
Finished Apr 04 01:21:17 PM PDT 24
Peak memory 202016 kb
Host smart-1119961c-486c-4fe7-834b-92ab191df9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743399049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.743399049
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1289625332
Short name T679
Test name
Test status
Simulation time 5895531212 ps
CPU time 2.97 seconds
Started Apr 04 01:21:04 PM PDT 24
Finished Apr 04 01:21:08 PM PDT 24
Peak memory 202076 kb
Host smart-81ae4451-8bfd-49a5-84a0-fc60c19d00c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289625332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1289625332
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.3212416870
Short name T595
Test name
Test status
Simulation time 1311654309 ps
CPU time 3.47 seconds
Started Apr 04 01:21:14 PM PDT 24
Finished Apr 04 01:21:17 PM PDT 24
Peak memory 201968 kb
Host smart-bc583490-6ff9-493b-937b-12e9f08c3e9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212416870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.3212416870
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2673213292
Short name T789
Test name
Test status
Simulation time 14952283252 ps
CPU time 33.63 seconds
Started Apr 04 01:21:13 PM PDT 24
Finished Apr 04 01:21:47 PM PDT 24
Peak memory 202376 kb
Host smart-aa01e1c1-00db-472f-affc-33d169c03f11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673213292 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2673213292
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.3790775380
Short name T400
Test name
Test status
Simulation time 331215206 ps
CPU time 1 seconds
Started Apr 04 01:21:25 PM PDT 24
Finished Apr 04 01:21:26 PM PDT 24
Peak memory 201920 kb
Host smart-33dee971-6a26-47a4-bbc0-48fa050d7ff5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790775380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3790775380
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.476926829
Short name T137
Test name
Test status
Simulation time 325813315607 ps
CPU time 245.79 seconds
Started Apr 04 01:21:25 PM PDT 24
Finished Apr 04 01:25:31 PM PDT 24
Peak memory 202252 kb
Host smart-642abf09-4942-4484-9684-5195df01cceb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476926829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gati
ng.476926829
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.2636001461
Short name T231
Test name
Test status
Simulation time 163384368959 ps
CPU time 404.04 seconds
Started Apr 04 01:21:15 PM PDT 24
Finished Apr 04 01:27:59 PM PDT 24
Peak memory 202272 kb
Host smart-8a574dd8-3924-4644-905b-8ef1680d77d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636001461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2636001461
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1028452200
Short name T82
Test name
Test status
Simulation time 327445780937 ps
CPU time 212.11 seconds
Started Apr 04 01:21:14 PM PDT 24
Finished Apr 04 01:24:46 PM PDT 24
Peak memory 202228 kb
Host smart-8ea92f83-4009-4125-b260-47df69217e6d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028452200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1028452200
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.2268315167
Short name T178
Test name
Test status
Simulation time 163850627804 ps
CPU time 199.71 seconds
Started Apr 04 01:21:14 PM PDT 24
Finished Apr 04 01:24:33 PM PDT 24
Peak memory 202284 kb
Host smart-5858e276-2894-4471-be55-c1ef486f15f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268315167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2268315167
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.1325985499
Short name T771
Test name
Test status
Simulation time 497447755395 ps
CPU time 1090.69 seconds
Started Apr 04 01:21:15 PM PDT 24
Finished Apr 04 01:39:26 PM PDT 24
Peak memory 202264 kb
Host smart-71923587-e7bb-460e-9b07-a8d59ed31030
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325985499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.1325985499
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.934727516
Short name T770
Test name
Test status
Simulation time 369511764969 ps
CPU time 69.93 seconds
Started Apr 04 01:21:14 PM PDT 24
Finished Apr 04 01:22:24 PM PDT 24
Peak memory 202284 kb
Host smart-37e2fe6a-35be-421c-bf8a-b86674d6bc33
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934727516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.934727516
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.872559708
Short name T714
Test name
Test status
Simulation time 607062704362 ps
CPU time 366.88 seconds
Started Apr 04 01:21:24 PM PDT 24
Finished Apr 04 01:27:31 PM PDT 24
Peak memory 202236 kb
Host smart-96b93ba1-be03-497c-83ef-79d93f9d83d4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872559708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
adc_ctrl_filters_wakeup_fixed.872559708
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2286460972
Short name T490
Test name
Test status
Simulation time 118527075520 ps
CPU time 436.69 seconds
Started Apr 04 01:21:24 PM PDT 24
Finished Apr 04 01:28:41 PM PDT 24
Peak memory 202568 kb
Host smart-a9b72a6a-0819-49a0-a748-877dab25431f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286460972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2286460972
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.1782810946
Short name T780
Test name
Test status
Simulation time 22873808910 ps
CPU time 52.72 seconds
Started Apr 04 01:21:22 PM PDT 24
Finished Apr 04 01:22:15 PM PDT 24
Peak memory 202060 kb
Host smart-bd8e7b7e-918a-4053-b7d8-82f089763d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782810946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.1782810946
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3660537310
Short name T706
Test name
Test status
Simulation time 4297940598 ps
CPU time 2.97 seconds
Started Apr 04 01:21:23 PM PDT 24
Finished Apr 04 01:21:26 PM PDT 24
Peak memory 201988 kb
Host smart-96d2e611-c12a-4561-b60b-9299f3cde71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660537310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3660537310
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2810781190
Short name T635
Test name
Test status
Simulation time 6053987102 ps
CPU time 1.69 seconds
Started Apr 04 01:21:15 PM PDT 24
Finished Apr 04 01:21:17 PM PDT 24
Peak memory 202068 kb
Host smart-738f2b36-7244-4626-9cf5-1fa88e45a2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810781190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2810781190
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1683037294
Short name T229
Test name
Test status
Simulation time 162672072796 ps
CPU time 386.99 seconds
Started Apr 04 01:21:24 PM PDT 24
Finished Apr 04 01:27:51 PM PDT 24
Peak memory 202088 kb
Host smart-da01cf7a-e986-4511-9e12-bace0fc1cf4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683037294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1683037294
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.3204854124
Short name T13
Test name
Test status
Simulation time 126626274260 ps
CPU time 154.13 seconds
Started Apr 04 01:21:25 PM PDT 24
Finished Apr 04 01:23:59 PM PDT 24
Peak memory 218164 kb
Host smart-957559df-2c8f-4f7c-92e3-6b833979e496
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204854124 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.3204854124
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2275776395
Short name T574
Test name
Test status
Simulation time 593541780 ps
CPU time 0.79 seconds
Started Apr 04 01:21:42 PM PDT 24
Finished Apr 04 01:21:43 PM PDT 24
Peak memory 202044 kb
Host smart-b2f93721-3329-421b-9cdc-882a1afb81af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275776395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2275776395
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.275332996
Short name T326
Test name
Test status
Simulation time 337192068576 ps
CPU time 756.52 seconds
Started Apr 04 01:21:32 PM PDT 24
Finished Apr 04 01:34:09 PM PDT 24
Peak memory 202176 kb
Host smart-46b8fb27-bb79-4c8e-9f22-198f69a56740
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275332996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gati
ng.275332996
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1012436133
Short name T632
Test name
Test status
Simulation time 331194177317 ps
CPU time 369.93 seconds
Started Apr 04 01:21:32 PM PDT 24
Finished Apr 04 01:27:42 PM PDT 24
Peak memory 202264 kb
Host smart-cef58232-d7e8-47e7-bc66-d3749e0b8de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012436133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1012436133
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2147204757
Short name T290
Test name
Test status
Simulation time 161299471314 ps
CPU time 170.56 seconds
Started Apr 04 01:21:32 PM PDT 24
Finished Apr 04 01:24:23 PM PDT 24
Peak memory 202204 kb
Host smart-7ff1bc66-db71-4d5f-afa7-8118f16cde45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147204757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2147204757
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1240133288
Short name T712
Test name
Test status
Simulation time 324233371913 ps
CPU time 760.06 seconds
Started Apr 04 01:21:31 PM PDT 24
Finished Apr 04 01:34:12 PM PDT 24
Peak memory 202204 kb
Host smart-d39dc152-e5bc-40d9-a302-048de7d9debf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240133288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1240133288
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3436951593
Short name T187
Test name
Test status
Simulation time 487760322644 ps
CPU time 292.44 seconds
Started Apr 04 01:21:25 PM PDT 24
Finished Apr 04 01:26:17 PM PDT 24
Peak memory 202272 kb
Host smart-92217533-8413-40e3-9dd7-445adaadd172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436951593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3436951593
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2584168916
Short name T440
Test name
Test status
Simulation time 494470910817 ps
CPU time 1195.87 seconds
Started Apr 04 01:21:33 PM PDT 24
Finished Apr 04 01:41:29 PM PDT 24
Peak memory 202228 kb
Host smart-ba829ad5-3999-4713-8415-7206598635cf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584168916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2584168916
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.678958287
Short name T261
Test name
Test status
Simulation time 357631409311 ps
CPU time 181.48 seconds
Started Apr 04 01:21:31 PM PDT 24
Finished Apr 04 01:24:33 PM PDT 24
Peak memory 202336 kb
Host smart-3c6c7329-22a1-435a-9163-be1910894c6a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678958287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_
wakeup.678958287
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3832170293
Short name T721
Test name
Test status
Simulation time 201347644222 ps
CPU time 102.08 seconds
Started Apr 04 01:21:33 PM PDT 24
Finished Apr 04 01:23:15 PM PDT 24
Peak memory 202140 kb
Host smart-3e17b639-9329-4b84-a9e1-8a43b6fbc6df
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832170293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.3832170293
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3180494383
Short name T455
Test name
Test status
Simulation time 26331663870 ps
CPU time 16.84 seconds
Started Apr 04 01:21:42 PM PDT 24
Finished Apr 04 01:21:59 PM PDT 24
Peak memory 202080 kb
Host smart-bbf35c75-431c-41bd-aed3-5c9693921fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180494383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3180494383
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.2971414222
Short name T476
Test name
Test status
Simulation time 4983088749 ps
CPU time 3.17 seconds
Started Apr 04 01:21:40 PM PDT 24
Finished Apr 04 01:21:44 PM PDT 24
Peak memory 201988 kb
Host smart-0cd6148b-3b22-4e6d-bd07-d56df8b3fc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971414222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.2971414222
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1567040071
Short name T398
Test name
Test status
Simulation time 6171821200 ps
CPU time 11.27 seconds
Started Apr 04 01:21:22 PM PDT 24
Finished Apr 04 01:21:33 PM PDT 24
Peak memory 201992 kb
Host smart-09ea4750-d735-4253-a77c-49a4a4ea4622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567040071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1567040071
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1485332805
Short name T211
Test name
Test status
Simulation time 170073282039 ps
CPU time 33.57 seconds
Started Apr 04 01:21:39 PM PDT 24
Finished Apr 04 01:22:13 PM PDT 24
Peak memory 202356 kb
Host smart-f8efb482-b46b-465a-87c7-f0219f20fc6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485332805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1485332805
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.331183136
Short name T41
Test name
Test status
Simulation time 55716548670 ps
CPU time 82.06 seconds
Started Apr 04 01:21:41 PM PDT 24
Finished Apr 04 01:23:03 PM PDT 24
Peak memory 213008 kb
Host smart-3166bef4-90b8-4699-9cbb-50466b59b341
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331183136 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.331183136
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3880741611
Short name T584
Test name
Test status
Simulation time 439810298 ps
CPU time 1.1 seconds
Started Apr 04 01:22:08 PM PDT 24
Finished Apr 04 01:22:10 PM PDT 24
Peak memory 201952 kb
Host smart-3966376b-e93a-4727-9412-a4bd2e6702a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880741611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3880741611
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.2003318372
Short name T526
Test name
Test status
Simulation time 373472033841 ps
CPU time 850.91 seconds
Started Apr 04 01:21:52 PM PDT 24
Finished Apr 04 01:36:03 PM PDT 24
Peak memory 202260 kb
Host smart-e6ae801d-742c-4aa8-a2fe-07712df0ead3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003318372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.2003318372
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.601155384
Short name T316
Test name
Test status
Simulation time 322337750656 ps
CPU time 745.33 seconds
Started Apr 04 01:21:43 PM PDT 24
Finished Apr 04 01:34:09 PM PDT 24
Peak memory 202200 kb
Host smart-083fa2a3-d492-4cca-8d17-53b59b3eeb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601155384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.601155384
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1369252194
Short name T456
Test name
Test status
Simulation time 167395301007 ps
CPU time 390.62 seconds
Started Apr 04 01:21:41 PM PDT 24
Finished Apr 04 01:28:12 PM PDT 24
Peak memory 202188 kb
Host smart-deab8fe3-4f75-4cfb-a3b9-7b14d08908b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369252194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1369252194
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.712840889
Short name T80
Test name
Test status
Simulation time 335694863428 ps
CPU time 387.77 seconds
Started Apr 04 01:21:40 PM PDT 24
Finished Apr 04 01:28:09 PM PDT 24
Peak memory 202256 kb
Host smart-ff45ee3d-2d58-416e-83fc-37a369287b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712840889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.712840889
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2281590676
Short name T473
Test name
Test status
Simulation time 490804644347 ps
CPU time 532.21 seconds
Started Apr 04 01:21:41 PM PDT 24
Finished Apr 04 01:30:34 PM PDT 24
Peak memory 202224 kb
Host smart-2d5c35cf-a814-4048-bd6a-f4c03807e44a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281590676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2281590676
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.3772579641
Short name T217
Test name
Test status
Simulation time 373272137116 ps
CPU time 835.74 seconds
Started Apr 04 01:21:40 PM PDT 24
Finished Apr 04 01:35:37 PM PDT 24
Peak memory 202196 kb
Host smart-dc69eeca-8a34-4c57-91b3-832a2c4c3b6f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772579641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.3772579641
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.964374503
Short name T723
Test name
Test status
Simulation time 201905535979 ps
CPU time 225.23 seconds
Started Apr 04 01:21:53 PM PDT 24
Finished Apr 04 01:25:39 PM PDT 24
Peak memory 202220 kb
Host smart-cf68370e-39db-4497-8f68-4b41ef0e1b1c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964374503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
adc_ctrl_filters_wakeup_fixed.964374503
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.475355624
Short name T654
Test name
Test status
Simulation time 137726568860 ps
CPU time 444.61 seconds
Started Apr 04 01:21:52 PM PDT 24
Finished Apr 04 01:29:17 PM PDT 24
Peak memory 202624 kb
Host smart-631b6485-b240-4901-b5da-56f99944cf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475355624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.475355624
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.3236081326
Short name T547
Test name
Test status
Simulation time 43749171100 ps
CPU time 15.99 seconds
Started Apr 04 01:21:52 PM PDT 24
Finished Apr 04 01:22:09 PM PDT 24
Peak memory 202092 kb
Host smart-3338c00b-51fc-49a4-ae43-413331904750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236081326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3236081326
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.1253320192
Short name T559
Test name
Test status
Simulation time 3262496101 ps
CPU time 7.48 seconds
Started Apr 04 01:21:54 PM PDT 24
Finished Apr 04 01:22:02 PM PDT 24
Peak memory 202020 kb
Host smart-3cda9f2d-a996-4dfe-afb7-6debd60f5a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253320192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.1253320192
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1710978496
Short name T371
Test name
Test status
Simulation time 5694111113 ps
CPU time 15.05 seconds
Started Apr 04 01:21:40 PM PDT 24
Finished Apr 04 01:21:56 PM PDT 24
Peak memory 202072 kb
Host smart-aee8e6a4-a063-4948-80b9-2fd6bbe36afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710978496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1710978496
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.1952479755
Short name T680
Test name
Test status
Simulation time 506827730299 ps
CPU time 288.03 seconds
Started Apr 04 01:22:07 PM PDT 24
Finished Apr 04 01:26:55 PM PDT 24
Peak memory 202276 kb
Host smart-5caff028-522c-4bf1-a095-2e982e087761
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952479755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.1952479755
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.1509554671
Short name T346
Test name
Test status
Simulation time 105515652323 ps
CPU time 391.01 seconds
Started Apr 04 01:22:07 PM PDT 24
Finished Apr 04 01:28:38 PM PDT 24
Peak memory 210888 kb
Host smart-44249d30-d52e-4956-b6f9-bdf0a85c551a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509554671 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.1509554671
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2484876047
Short name T454
Test name
Test status
Simulation time 405761762 ps
CPU time 1.48 seconds
Started Apr 04 01:22:20 PM PDT 24
Finished Apr 04 01:22:21 PM PDT 24
Peak memory 202048 kb
Host smart-3895fef3-80e6-466f-a183-263add9b8a4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484876047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2484876047
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.3790453737
Short name T94
Test name
Test status
Simulation time 528360470897 ps
CPU time 1176.94 seconds
Started Apr 04 01:22:07 PM PDT 24
Finished Apr 04 01:41:44 PM PDT 24
Peak memory 202220 kb
Host smart-b82c3cb0-85af-4221-9274-04f3cd84a80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790453737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.3790453737
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1411354176
Short name T515
Test name
Test status
Simulation time 164793256462 ps
CPU time 111.48 seconds
Started Apr 04 01:22:08 PM PDT 24
Finished Apr 04 01:24:01 PM PDT 24
Peak memory 202176 kb
Host smart-cfcfcebd-4997-43cb-bc69-4a9915675d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411354176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1411354176
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.864640885
Short name T427
Test name
Test status
Simulation time 322644458336 ps
CPU time 375.28 seconds
Started Apr 04 01:22:05 PM PDT 24
Finished Apr 04 01:28:21 PM PDT 24
Peak memory 202312 kb
Host smart-3fff1160-a678-4689-9e4b-df1086f2621c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=864640885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrup
t_fixed.864640885
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3249286067
Short name T784
Test name
Test status
Simulation time 490902616528 ps
CPU time 291.64 seconds
Started Apr 04 01:22:07 PM PDT 24
Finished Apr 04 01:26:59 PM PDT 24
Peak memory 202240 kb
Host smart-72f7bf8c-f35e-4312-9cc9-0f6e2449e053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249286067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3249286067
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.953854527
Short name T370
Test name
Test status
Simulation time 327458627064 ps
CPU time 385.25 seconds
Started Apr 04 01:22:05 PM PDT 24
Finished Apr 04 01:28:31 PM PDT 24
Peak memory 202148 kb
Host smart-5b5cd196-1ee4-47e7-8dd8-9eda814b3e19
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=953854527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixe
d.953854527
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.1108047271
Short name T677
Test name
Test status
Simulation time 427291679173 ps
CPU time 985.27 seconds
Started Apr 04 01:22:07 PM PDT 24
Finished Apr 04 01:38:32 PM PDT 24
Peak memory 202184 kb
Host smart-da44ef6a-601d-467c-9b8f-0a6dc3d47bba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108047271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.1108047271
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.4126381946
Short name T382
Test name
Test status
Simulation time 621517203770 ps
CPU time 191.64 seconds
Started Apr 04 01:22:08 PM PDT 24
Finished Apr 04 01:25:20 PM PDT 24
Peak memory 202160 kb
Host smart-79f2e952-a146-438c-8439-2dcbbbdd8c36
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126381946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.4126381946
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2541789742
Short name T651
Test name
Test status
Simulation time 69332139092 ps
CPU time 247.67 seconds
Started Apr 04 01:22:21 PM PDT 24
Finished Apr 04 01:26:29 PM PDT 24
Peak memory 202548 kb
Host smart-606661f6-4095-41ec-a96d-a3cc835d95c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541789742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2541789742
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.3429799298
Short name T48
Test name
Test status
Simulation time 40152907855 ps
CPU time 21.99 seconds
Started Apr 04 01:22:08 PM PDT 24
Finished Apr 04 01:22:30 PM PDT 24
Peak memory 202080 kb
Host smart-9a263b74-35cb-4b90-ab5e-b255a89616e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429799298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.3429799298
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.910838481
Short name T791
Test name
Test status
Simulation time 5442782708 ps
CPU time 13.05 seconds
Started Apr 04 01:22:07 PM PDT 24
Finished Apr 04 01:22:20 PM PDT 24
Peak memory 202052 kb
Host smart-aa997e40-0dd4-4d74-a7a9-3678eac7a633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910838481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.910838481
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3664319376
Short name T681
Test name
Test status
Simulation time 6009511818 ps
CPU time 1.86 seconds
Started Apr 04 01:22:07 PM PDT 24
Finished Apr 04 01:22:10 PM PDT 24
Peak memory 202028 kb
Host smart-e627658a-8855-4bfc-8f30-4198ce18d5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664319376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3664319376
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1652371510
Short name T223
Test name
Test status
Simulation time 423978690673 ps
CPU time 1019.45 seconds
Started Apr 04 01:22:20 PM PDT 24
Finished Apr 04 01:39:20 PM PDT 24
Peak memory 210788 kb
Host smart-1df7ce0c-6215-48fb-8c3e-2ce05896713f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652371510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1652371510
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3518606705
Short name T715
Test name
Test status
Simulation time 38648631204 ps
CPU time 49.93 seconds
Started Apr 04 01:22:20 PM PDT 24
Finished Apr 04 01:23:10 PM PDT 24
Peak memory 210588 kb
Host smart-ae99e56c-d829-457c-9ed1-9cc36210a3b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518606705 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.3518606705
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2837237399
Short name T631
Test name
Test status
Simulation time 422221021 ps
CPU time 0.86 seconds
Started Apr 04 01:22:31 PM PDT 24
Finished Apr 04 01:22:32 PM PDT 24
Peak memory 202016 kb
Host smart-3221c494-eaeb-4115-ae05-e5cc59277f64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837237399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2837237399
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.661943165
Short name T166
Test name
Test status
Simulation time 496229845151 ps
CPU time 212.82 seconds
Started Apr 04 01:22:21 PM PDT 24
Finished Apr 04 01:25:54 PM PDT 24
Peak memory 202328 kb
Host smart-0d262ec2-f02c-4790-b050-62daa4e60841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661943165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.661943165
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3568486312
Short name T127
Test name
Test status
Simulation time 327958200415 ps
CPU time 52.84 seconds
Started Apr 04 01:22:19 PM PDT 24
Finished Apr 04 01:23:12 PM PDT 24
Peak memory 202140 kb
Host smart-fe4d943f-bb69-4fe2-946f-87a61909baae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568486312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3568486312
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2869671961
Short name T743
Test name
Test status
Simulation time 486744374072 ps
CPU time 1068.72 seconds
Started Apr 04 01:22:19 PM PDT 24
Finished Apr 04 01:40:08 PM PDT 24
Peak memory 202160 kb
Host smart-a5fb261b-442e-4183-9f8b-0d11753a0a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869671961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2869671961
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2241138410
Short name T131
Test name
Test status
Simulation time 496497243752 ps
CPU time 143.86 seconds
Started Apr 04 01:22:21 PM PDT 24
Finished Apr 04 01:24:45 PM PDT 24
Peak memory 202220 kb
Host smart-809c19b0-49eb-4360-b93e-c242b4f27c70
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241138410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2241138410
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3462756574
Short name T612
Test name
Test status
Simulation time 187143552974 ps
CPU time 452.9 seconds
Started Apr 04 01:22:20 PM PDT 24
Finished Apr 04 01:29:53 PM PDT 24
Peak memory 202264 kb
Host smart-7f05c6f1-b6ed-4602-a57c-889753af9a42
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462756574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.3462756574
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3249820465
Short name T534
Test name
Test status
Simulation time 398590456608 ps
CPU time 234.32 seconds
Started Apr 04 01:22:21 PM PDT 24
Finished Apr 04 01:26:16 PM PDT 24
Peak memory 202140 kb
Host smart-704ceb79-ac23-4604-9183-4b0d11173348
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249820465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.3249820465
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.4227585345
Short name T657
Test name
Test status
Simulation time 86384638342 ps
CPU time 338.21 seconds
Started Apr 04 01:22:32 PM PDT 24
Finished Apr 04 01:28:10 PM PDT 24
Peak memory 202552 kb
Host smart-ad6617b2-17eb-4439-a47a-fcbe3a2235ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227585345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.4227585345
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2795455634
Short name T745
Test name
Test status
Simulation time 37452954743 ps
CPU time 9.32 seconds
Started Apr 04 01:22:30 PM PDT 24
Finished Apr 04 01:22:40 PM PDT 24
Peak memory 201948 kb
Host smart-368770cd-c368-4250-a9cd-586e9fcb5ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795455634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2795455634
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2958410427
Short name T570
Test name
Test status
Simulation time 4423338384 ps
CPU time 5.49 seconds
Started Apr 04 01:22:21 PM PDT 24
Finished Apr 04 01:22:26 PM PDT 24
Peak memory 202068 kb
Host smart-f46989fe-b90a-4f95-9478-7d4e1f8eb486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958410427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2958410427
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.1693141664
Short name T567
Test name
Test status
Simulation time 5768479269 ps
CPU time 15.6 seconds
Started Apr 04 01:22:20 PM PDT 24
Finished Apr 04 01:22:35 PM PDT 24
Peak memory 201960 kb
Host smart-ae29d504-f97e-4719-845b-c93c2cb41695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693141664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.1693141664
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2330952302
Short name T658
Test name
Test status
Simulation time 531149579 ps
CPU time 0.68 seconds
Started Apr 04 01:22:55 PM PDT 24
Finished Apr 04 01:22:56 PM PDT 24
Peak memory 201976 kb
Host smart-0abee014-8cb7-496b-8405-5d3fcbd1c99a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330952302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2330952302
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3993963896
Short name T209
Test name
Test status
Simulation time 176871259671 ps
CPU time 390.74 seconds
Started Apr 04 01:22:41 PM PDT 24
Finished Apr 04 01:29:12 PM PDT 24
Peak memory 202352 kb
Host smart-c4e6abd9-6941-4023-9ddc-f3db75b76982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993963896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3993963896
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.4088849901
Short name T552
Test name
Test status
Simulation time 487180950990 ps
CPU time 323.49 seconds
Started Apr 04 01:22:31 PM PDT 24
Finished Apr 04 01:27:54 PM PDT 24
Peak memory 202228 kb
Host smart-6c38dc00-8cab-4fae-80ed-9dff1fd3e3fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088849901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.4088849901
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.3155801651
Short name T738
Test name
Test status
Simulation time 163125395425 ps
CPU time 117.83 seconds
Started Apr 04 01:22:30 PM PDT 24
Finished Apr 04 01:24:28 PM PDT 24
Peak memory 202212 kb
Host smart-74f7d792-a652-4e75-80c8-df6120b217a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155801651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.3155801651
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.37721528
Short name T428
Test name
Test status
Simulation time 490724989768 ps
CPU time 1028.67 seconds
Started Apr 04 01:22:30 PM PDT 24
Finished Apr 04 01:39:39 PM PDT 24
Peak memory 202168 kb
Host smart-431000c6-c827-4b5a-ad84-9a564938368b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=37721528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixed
.37721528
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2911641754
Short name T256
Test name
Test status
Simulation time 170999002905 ps
CPU time 204.96 seconds
Started Apr 04 01:22:31 PM PDT 24
Finished Apr 04 01:25:56 PM PDT 24
Peak memory 202184 kb
Host smart-fb777d50-3ba5-494f-b05a-90a03d594a50
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911641754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2911641754
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2240192971
Short name T589
Test name
Test status
Simulation time 395479801728 ps
CPU time 856.99 seconds
Started Apr 04 01:22:31 PM PDT 24
Finished Apr 04 01:36:49 PM PDT 24
Peak memory 202220 kb
Host smart-d13d4fdf-a5ec-4255-b35e-ac5f6693fa55
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240192971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2240192971
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1066651351
Short name T337
Test name
Test status
Simulation time 97952691604 ps
CPU time 368.94 seconds
Started Apr 04 01:22:42 PM PDT 24
Finished Apr 04 01:28:52 PM PDT 24
Peak memory 202580 kb
Host smart-153a51d0-7db4-438e-9d4a-4a6127344bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066651351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1066651351
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.4137560677
Short name T379
Test name
Test status
Simulation time 28396028420 ps
CPU time 16.41 seconds
Started Apr 04 01:22:40 PM PDT 24
Finished Apr 04 01:22:56 PM PDT 24
Peak memory 202108 kb
Host smart-69fa8fca-8824-43fe-9a50-437383212a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137560677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.4137560677
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3530915241
Short name T433
Test name
Test status
Simulation time 3607026498 ps
CPU time 8.36 seconds
Started Apr 04 01:22:43 PM PDT 24
Finished Apr 04 01:22:51 PM PDT 24
Peak memory 202052 kb
Host smart-16ca9c15-48ab-482d-93c3-85c710ce8b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530915241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3530915241
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.1618749039
Short name T448
Test name
Test status
Simulation time 5951180340 ps
CPU time 5.74 seconds
Started Apr 04 01:22:32 PM PDT 24
Finished Apr 04 01:22:37 PM PDT 24
Peak memory 202036 kb
Host smart-ee4ee8b8-22a9-4797-bf01-f69f43990892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618749039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.1618749039
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.1856771733
Short name T639
Test name
Test status
Simulation time 58898654608 ps
CPU time 66.26 seconds
Started Apr 04 01:22:43 PM PDT 24
Finished Apr 04 01:23:49 PM PDT 24
Peak memory 210524 kb
Host smart-9c70af51-3e79-4d13-ad81-cd081d276e10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856771733 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.1856771733
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.2031203405
Short name T375
Test name
Test status
Simulation time 533646113 ps
CPU time 1.2 seconds
Started Apr 04 01:23:08 PM PDT 24
Finished Apr 04 01:23:10 PM PDT 24
Peak memory 201956 kb
Host smart-f2ca0ece-1588-492c-a1cf-39f0eb59e314
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031203405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.2031203405
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.555647330
Short name T245
Test name
Test status
Simulation time 230583002727 ps
CPU time 65.34 seconds
Started Apr 04 01:22:53 PM PDT 24
Finished Apr 04 01:23:59 PM PDT 24
Peak memory 202252 kb
Host smart-f69a1d58-e593-4f29-adcf-863d5f46b09d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555647330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gati
ng.555647330
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1963262375
Short name T702
Test name
Test status
Simulation time 173983637235 ps
CPU time 223.95 seconds
Started Apr 04 01:22:57 PM PDT 24
Finished Apr 04 01:26:41 PM PDT 24
Peak memory 202236 kb
Host smart-1207d042-982b-4596-8a57-a62d544a405b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963262375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1963262375
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.1491520677
Short name T278
Test name
Test status
Simulation time 491606370852 ps
CPU time 559.26 seconds
Started Apr 04 01:22:52 PM PDT 24
Finished Apr 04 01:32:12 PM PDT 24
Peak memory 202356 kb
Host smart-202b3d69-9719-4ae1-9997-812d80dd9359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491520677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.1491520677
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.801388238
Short name T3
Test name
Test status
Simulation time 484343103060 ps
CPU time 412.6 seconds
Started Apr 04 01:22:53 PM PDT 24
Finished Apr 04 01:29:46 PM PDT 24
Peak memory 202152 kb
Host smart-185da23a-b455-49bd-b760-75caa7768e24
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=801388238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.801388238
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.453722808
Short name T164
Test name
Test status
Simulation time 328227291245 ps
CPU time 102.51 seconds
Started Apr 04 01:22:53 PM PDT 24
Finished Apr 04 01:24:36 PM PDT 24
Peak memory 202160 kb
Host smart-609c7ac6-a7fb-4e33-98d9-6f95db124c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453722808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.453722808
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.3835587756
Short name T592
Test name
Test status
Simulation time 497028096454 ps
CPU time 568.88 seconds
Started Apr 04 01:22:57 PM PDT 24
Finished Apr 04 01:32:26 PM PDT 24
Peak memory 202292 kb
Host smart-674a2596-030f-4317-8eba-f55e1e3588ec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835587756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.3835587756
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2993519498
Short name T621
Test name
Test status
Simulation time 209845520820 ps
CPU time 522.34 seconds
Started Apr 04 01:22:56 PM PDT 24
Finished Apr 04 01:31:38 PM PDT 24
Peak memory 202216 kb
Host smart-4c419d88-aff2-4859-92b2-737ae859331b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993519498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2993519498
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2951547209
Short name T6
Test name
Test status
Simulation time 209392114665 ps
CPU time 198.56 seconds
Started Apr 04 01:22:54 PM PDT 24
Finished Apr 04 01:26:12 PM PDT 24
Peak memory 202228 kb
Host smart-7578c1b8-f19d-4a50-822a-f456c3b819b2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951547209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2951547209
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3857211658
Short name T335
Test name
Test status
Simulation time 101726737117 ps
CPU time 542.85 seconds
Started Apr 04 01:23:03 PM PDT 24
Finished Apr 04 01:32:06 PM PDT 24
Peak memory 202624 kb
Host smart-6fdc24a0-c46d-4604-90cd-8c0f03a7c376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857211658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3857211658
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3976509211
Short name T408
Test name
Test status
Simulation time 30200733417 ps
CPU time 68.7 seconds
Started Apr 04 01:23:06 PM PDT 24
Finished Apr 04 01:24:15 PM PDT 24
Peak memory 202156 kb
Host smart-8630b394-1f3c-411b-9b18-a43305f27ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976509211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3976509211
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.2959917836
Short name T404
Test name
Test status
Simulation time 3096091392 ps
CPU time 6.48 seconds
Started Apr 04 01:22:54 PM PDT 24
Finished Apr 04 01:23:01 PM PDT 24
Peak memory 202020 kb
Host smart-cce16cb0-c6fa-4c88-b311-a3f9dbbf3334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959917836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.2959917836
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.1791018260
Short name T751
Test name
Test status
Simulation time 5721526912 ps
CPU time 10.33 seconds
Started Apr 04 01:22:53 PM PDT 24
Finished Apr 04 01:23:04 PM PDT 24
Peak memory 202072 kb
Host smart-fa4b41cd-b185-463f-a1c2-db5142c4bb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791018260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.1791018260
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2236408916
Short name T689
Test name
Test status
Simulation time 165751634052 ps
CPU time 508.82 seconds
Started Apr 04 01:23:03 PM PDT 24
Finished Apr 04 01:31:32 PM PDT 24
Peak memory 210936 kb
Host smart-48c8271c-7675-4954-9adb-a327e3193b23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236408916 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.2236408916
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.523013956
Short name T395
Test name
Test status
Simulation time 454313612 ps
CPU time 1.57 seconds
Started Apr 04 01:23:23 PM PDT 24
Finished Apr 04 01:23:24 PM PDT 24
Peak memory 201976 kb
Host smart-e883424e-c8f7-428b-b4f0-c6c4adf2c6c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523013956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.523013956
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.65589591
Short name T328
Test name
Test status
Simulation time 167165746509 ps
CPU time 94.57 seconds
Started Apr 04 01:23:15 PM PDT 24
Finished Apr 04 01:24:50 PM PDT 24
Peak memory 202452 kb
Host smart-a0b08dc7-3f0b-458a-8d21-86eeb3ba1ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65589591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.65589591
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2068209871
Short name T77
Test name
Test status
Simulation time 163632526510 ps
CPU time 56.8 seconds
Started Apr 04 01:23:13 PM PDT 24
Finished Apr 04 01:24:09 PM PDT 24
Peak memory 202304 kb
Host smart-6f2f0ffe-3e40-48e1-a970-7e856ee37ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068209871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2068209871
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.2408882498
Short name T372
Test name
Test status
Simulation time 161191371583 ps
CPU time 146.82 seconds
Started Apr 04 01:23:13 PM PDT 24
Finished Apr 04 01:25:40 PM PDT 24
Peak memory 202164 kb
Host smart-70ba2717-34fb-419f-945c-c828c4e4c330
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408882498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.2408882498
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.365230053
Short name T274
Test name
Test status
Simulation time 165944681388 ps
CPU time 104.47 seconds
Started Apr 04 01:23:08 PM PDT 24
Finished Apr 04 01:24:53 PM PDT 24
Peak memory 202232 kb
Host smart-bb99e527-2e0e-4a01-a037-ad3e868f16a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365230053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.365230053
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2090441608
Short name T445
Test name
Test status
Simulation time 161292238490 ps
CPU time 343.25 seconds
Started Apr 04 01:23:08 PM PDT 24
Finished Apr 04 01:28:52 PM PDT 24
Peak memory 202208 kb
Host smart-2e573ca0-ceb7-4647-8c72-4cbea2c13a2b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090441608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.2090441608
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.240489457
Short name T457
Test name
Test status
Simulation time 179595858273 ps
CPU time 399.76 seconds
Started Apr 04 01:23:15 PM PDT 24
Finished Apr 04 01:29:55 PM PDT 24
Peak memory 202536 kb
Host smart-d67f9595-41ee-4d51-b88a-9062c1085b29
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240489457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_
wakeup.240489457
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1880308042
Short name T148
Test name
Test status
Simulation time 192276874492 ps
CPU time 118.3 seconds
Started Apr 04 01:23:13 PM PDT 24
Finished Apr 04 01:25:12 PM PDT 24
Peak memory 202152 kb
Host smart-faf4cd06-d28c-4de6-ae28-83d6c394ee86
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880308042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1880308042
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.3519057723
Short name T627
Test name
Test status
Simulation time 67119840320 ps
CPU time 366.13 seconds
Started Apr 04 01:23:12 PM PDT 24
Finished Apr 04 01:29:18 PM PDT 24
Peak memory 202600 kb
Host smart-c2d756e2-d8e1-4ae9-80b1-70b3d1e7f633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519057723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.3519057723
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.2336236108
Short name T92
Test name
Test status
Simulation time 31056824647 ps
CPU time 74.23 seconds
Started Apr 04 01:23:13 PM PDT 24
Finished Apr 04 01:24:28 PM PDT 24
Peak memory 202120 kb
Host smart-7b3950d5-fabb-489c-a30b-f20d79308c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336236108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.2336236108
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.3767258333
Short name T438
Test name
Test status
Simulation time 4370935799 ps
CPU time 7.74 seconds
Started Apr 04 01:23:15 PM PDT 24
Finished Apr 04 01:23:23 PM PDT 24
Peak memory 202068 kb
Host smart-0026f146-c8b3-46c7-b5f0-1f095d8c3a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767258333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3767258333
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2099959653
Short name T377
Test name
Test status
Simulation time 6035647351 ps
CPU time 1.97 seconds
Started Apr 04 01:23:03 PM PDT 24
Finished Apr 04 01:23:05 PM PDT 24
Peak memory 202060 kb
Host smart-c392b43b-5826-4634-8065-51e9bccdaebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099959653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2099959653
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.562126234
Short name T399
Test name
Test status
Simulation time 466739777 ps
CPU time 0.72 seconds
Started Apr 04 01:08:02 PM PDT 24
Finished Apr 04 01:08:03 PM PDT 24
Peak memory 201964 kb
Host smart-887f63c8-5fef-435e-aa36-04f88587039c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562126234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.562126234
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.4083021260
Short name T215
Test name
Test status
Simulation time 166227204200 ps
CPU time 109.74 seconds
Started Apr 04 01:08:01 PM PDT 24
Finished Apr 04 01:09:51 PM PDT 24
Peak memory 202216 kb
Host smart-3a69bcde-9ff0-4709-b074-b7767d217cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083021260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.4083021260
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1917365924
Short name T474
Test name
Test status
Simulation time 165080054097 ps
CPU time 194.63 seconds
Started Apr 04 01:07:53 PM PDT 24
Finished Apr 04 01:11:08 PM PDT 24
Peak memory 202148 kb
Host smart-2c7ed979-3650-4334-b908-e32b74a3b913
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917365924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1917365924
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.740396794
Short name T424
Test name
Test status
Simulation time 161983206891 ps
CPU time 173.07 seconds
Started Apr 04 01:07:53 PM PDT 24
Finished Apr 04 01:10:46 PM PDT 24
Peak memory 202152 kb
Host smart-4ff41349-40ad-49f2-95e7-91a610bc3f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740396794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.740396794
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.975425804
Short name T790
Test name
Test status
Simulation time 494632645907 ps
CPU time 289.8 seconds
Started Apr 04 01:07:51 PM PDT 24
Finished Apr 04 01:12:41 PM PDT 24
Peak memory 202240 kb
Host smart-26c6a847-086c-4b83-bad3-fafcc95d6423
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=975425804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.975425804
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3388696070
Short name T556
Test name
Test status
Simulation time 382864390964 ps
CPU time 469.12 seconds
Started Apr 04 01:07:54 PM PDT 24
Finished Apr 04 01:15:44 PM PDT 24
Peak memory 202296 kb
Host smart-dc6aef98-ab71-421b-97e1-35d1fe93bd2f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388696070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3388696070
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.980023560
Short name T27
Test name
Test status
Simulation time 595384921899 ps
CPU time 1489.16 seconds
Started Apr 04 01:07:54 PM PDT 24
Finished Apr 04 01:32:43 PM PDT 24
Peak memory 202248 kb
Host smart-948af88e-6e6d-4f6f-b570-ee746f185f47
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980023560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.a
dc_ctrl_filters_wakeup_fixed.980023560
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1432419451
Short name T348
Test name
Test status
Simulation time 121135157961 ps
CPU time 423.08 seconds
Started Apr 04 01:08:04 PM PDT 24
Finished Apr 04 01:15:08 PM PDT 24
Peak memory 202564 kb
Host smart-ef6304e1-419f-47b7-942f-a7a446f43218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432419451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1432419451
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1466144670
Short name T24
Test name
Test status
Simulation time 33658861834 ps
CPU time 14.42 seconds
Started Apr 04 01:08:03 PM PDT 24
Finished Apr 04 01:08:18 PM PDT 24
Peak memory 202036 kb
Host smart-d8655f34-dced-434b-99a6-8805e8a013ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466144670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1466144670
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.2120409950
Short name T508
Test name
Test status
Simulation time 4063320239 ps
CPU time 5.64 seconds
Started Apr 04 01:08:02 PM PDT 24
Finished Apr 04 01:08:08 PM PDT 24
Peak memory 202008 kb
Host smart-32a54e2c-f9bf-4a88-adf9-7dc1cf70e941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120409950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.2120409950
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.2157884929
Short name T385
Test name
Test status
Simulation time 6148012365 ps
CPU time 14.41 seconds
Started Apr 04 01:07:51 PM PDT 24
Finished Apr 04 01:08:06 PM PDT 24
Peak memory 202064 kb
Host smart-95f025a2-47a6-4668-8da4-40d078bca069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157884929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.2157884929
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2624876895
Short name T601
Test name
Test status
Simulation time 134292988104 ps
CPU time 457.38 seconds
Started Apr 04 01:08:01 PM PDT 24
Finished Apr 04 01:15:39 PM PDT 24
Peak memory 218808 kb
Host smart-1b2a785d-103f-4bf1-9cba-091a9d4757f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624876895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2624876895
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.3273800385
Short name T83
Test name
Test status
Simulation time 435746735 ps
CPU time 1.12 seconds
Started Apr 04 01:08:23 PM PDT 24
Finished Apr 04 01:08:24 PM PDT 24
Peak memory 201968 kb
Host smart-8844e414-551f-442a-a81d-fc60131b21cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273800385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3273800385
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1669380720
Short name T329
Test name
Test status
Simulation time 165149037107 ps
CPU time 200.46 seconds
Started Apr 04 01:08:11 PM PDT 24
Finished Apr 04 01:11:31 PM PDT 24
Peak memory 202244 kb
Host smart-8bf42be0-3cb1-4cc1-bbe4-05fdf00c8386
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669380720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1669380720
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.2065448142
Short name T568
Test name
Test status
Simulation time 262675578736 ps
CPU time 307.35 seconds
Started Apr 04 01:08:21 PM PDT 24
Finished Apr 04 01:13:29 PM PDT 24
Peak memory 202256 kb
Host smart-bb9f8c29-990a-4896-b64c-66582773e94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065448142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.2065448142
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.4192134463
Short name T392
Test name
Test status
Simulation time 327459374173 ps
CPU time 183.77 seconds
Started Apr 04 01:08:11 PM PDT 24
Finished Apr 04 01:11:15 PM PDT 24
Peak memory 202252 kb
Host smart-93e78db9-47ac-4188-b0f9-7caf608bfdf4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192134463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.4192134463
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1087487981
Short name T322
Test name
Test status
Simulation time 487121386200 ps
CPU time 284.09 seconds
Started Apr 04 01:08:01 PM PDT 24
Finished Apr 04 01:12:45 PM PDT 24
Peak memory 202196 kb
Host smart-a39f31d8-7aa8-4e42-8194-2eca97dce934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087487981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1087487981
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.1945126785
Short name T149
Test name
Test status
Simulation time 158414209887 ps
CPU time 41.06 seconds
Started Apr 04 01:08:12 PM PDT 24
Finished Apr 04 01:08:53 PM PDT 24
Peak memory 202256 kb
Host smart-276af2bc-e727-446e-b67d-81d863a43044
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945126785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.1945126785
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.2196278953
Short name T527
Test name
Test status
Simulation time 194474952444 ps
CPU time 61.54 seconds
Started Apr 04 01:08:12 PM PDT 24
Finished Apr 04 01:09:14 PM PDT 24
Peak memory 202204 kb
Host smart-80de8d20-b9ba-4124-90bc-36fc34542ca9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196278953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.2196278953
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.712889603
Short name T336
Test name
Test status
Simulation time 80275797684 ps
CPU time 342.79 seconds
Started Apr 04 01:08:23 PM PDT 24
Finished Apr 04 01:14:06 PM PDT 24
Peak memory 202572 kb
Host smart-4901439f-4ebf-4e72-add4-38c100dbc281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712889603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.712889603
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1247648566
Short name T489
Test name
Test status
Simulation time 46325033971 ps
CPU time 22.13 seconds
Started Apr 04 01:08:23 PM PDT 24
Finished Apr 04 01:08:45 PM PDT 24
Peak memory 202076 kb
Host smart-17917943-2e12-4dec-91af-659842ffe15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247648566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1247648566
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1252061473
Short name T661
Test name
Test status
Simulation time 4802424302 ps
CPU time 3.69 seconds
Started Apr 04 01:08:22 PM PDT 24
Finished Apr 04 01:08:26 PM PDT 24
Peak memory 202024 kb
Host smart-da0cfa5c-6988-4a6e-b410-374a48c4a485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252061473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1252061473
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3383540987
Short name T158
Test name
Test status
Simulation time 6120062380 ps
CPU time 4.33 seconds
Started Apr 04 01:08:02 PM PDT 24
Finished Apr 04 01:08:06 PM PDT 24
Peak memory 201964 kb
Host smart-782e31b5-88e7-46f3-8dea-48182e62fbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383540987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3383540987
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.439791267
Short name T698
Test name
Test status
Simulation time 576466946753 ps
CPU time 978.77 seconds
Started Apr 04 01:08:21 PM PDT 24
Finished Apr 04 01:24:41 PM PDT 24
Peak memory 210812 kb
Host smart-0caab128-1152-4e70-b2d2-c288a84a62dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439791267 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.439791267
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.1841937681
Short name T550
Test name
Test status
Simulation time 524857698 ps
CPU time 1.73 seconds
Started Apr 04 01:08:54 PM PDT 24
Finished Apr 04 01:08:56 PM PDT 24
Peak memory 201836 kb
Host smart-6311b703-2d3c-4447-8de1-c4fbda383355
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841937681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.1841937681
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1106531462
Short name T236
Test name
Test status
Simulation time 486955594096 ps
CPU time 816.72 seconds
Started Apr 04 01:08:40 PM PDT 24
Finished Apr 04 01:22:18 PM PDT 24
Peak memory 202340 kb
Host smart-e07afabf-8431-4778-a197-4d118f9d4513
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106531462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1106531462
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.26701460
Short name T241
Test name
Test status
Simulation time 487377534483 ps
CPU time 533.15 seconds
Started Apr 04 01:08:31 PM PDT 24
Finished Apr 04 01:17:25 PM PDT 24
Peak memory 202288 kb
Host smart-180af64b-861c-45fd-ae34-1689b957a99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26701460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.26701460
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1500012120
Short name T181
Test name
Test status
Simulation time 489112057801 ps
CPU time 608.77 seconds
Started Apr 04 01:08:32 PM PDT 24
Finished Apr 04 01:18:41 PM PDT 24
Peak memory 202284 kb
Host smart-5220ad2b-d8f3-4ccb-ab4c-33428650a822
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500012120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.1500012120
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.2897802174
Short name T1
Test name
Test status
Simulation time 326833069871 ps
CPU time 188.44 seconds
Started Apr 04 01:08:31 PM PDT 24
Finished Apr 04 01:11:40 PM PDT 24
Peak memory 202268 kb
Host smart-68c2d756-4a59-42cb-aa4d-61e3a15b1b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897802174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.2897802174
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.298635037
Short name T507
Test name
Test status
Simulation time 489373559918 ps
CPU time 1152.58 seconds
Started Apr 04 01:08:31 PM PDT 24
Finished Apr 04 01:27:44 PM PDT 24
Peak memory 202228 kb
Host smart-c4555a61-adc2-41b3-9cd7-ee7b8d2b92cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=298635037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.298635037
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2059279254
Short name T764
Test name
Test status
Simulation time 186355964160 ps
CPU time 87.73 seconds
Started Apr 04 01:08:31 PM PDT 24
Finished Apr 04 01:09:59 PM PDT 24
Peak memory 202352 kb
Host smart-30a8c4fb-9201-4ea1-a33b-bcca386bf420
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059279254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2059279254
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.4206308876
Short name T353
Test name
Test status
Simulation time 392755496321 ps
CPU time 327.63 seconds
Started Apr 04 01:08:42 PM PDT 24
Finished Apr 04 01:14:10 PM PDT 24
Peak memory 202292 kb
Host smart-d4ee1f4f-5553-4631-9c8d-1c134d0cbbdc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206308876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.4206308876
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.4274857769
Short name T425
Test name
Test status
Simulation time 105830084932 ps
CPU time 395.19 seconds
Started Apr 04 01:08:42 PM PDT 24
Finished Apr 04 01:15:17 PM PDT 24
Peak memory 202536 kb
Host smart-a040f9d6-7a19-45e6-b3fb-5ebf6d03f80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274857769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.4274857769
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.3401028113
Short name T469
Test name
Test status
Simulation time 31933608487 ps
CPU time 31.06 seconds
Started Apr 04 01:08:41 PM PDT 24
Finished Apr 04 01:09:12 PM PDT 24
Peak memory 201988 kb
Host smart-8beab019-fe90-4031-b7a1-6b7ce0584592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401028113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.3401028113
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3305510547
Short name T459
Test name
Test status
Simulation time 3576703520 ps
CPU time 4.63 seconds
Started Apr 04 01:08:41 PM PDT 24
Finished Apr 04 01:08:46 PM PDT 24
Peak memory 202016 kb
Host smart-073cc05b-e80c-4541-9266-dd7c3db7f98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305510547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3305510547
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3160796376
Short name T512
Test name
Test status
Simulation time 6136168847 ps
CPU time 5.14 seconds
Started Apr 04 01:08:31 PM PDT 24
Finished Apr 04 01:08:36 PM PDT 24
Peak memory 201964 kb
Host smart-89e44fe5-34ac-4acb-aef1-4c5ce5359b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160796376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3160796376
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.4142111939
Short name T645
Test name
Test status
Simulation time 380559729715 ps
CPU time 204.11 seconds
Started Apr 04 01:08:54 PM PDT 24
Finished Apr 04 01:12:19 PM PDT 24
Peak memory 202260 kb
Host smart-5d9a930f-f1c2-4514-956c-f9affe2290f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142111939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
4142111939
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2364330861
Short name T38
Test name
Test status
Simulation time 28485178934 ps
CPU time 67.21 seconds
Started Apr 04 01:08:40 PM PDT 24
Finished Apr 04 01:09:48 PM PDT 24
Peak memory 218748 kb
Host smart-0111812b-76f3-4a52-93c7-c24a8bdefd08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364330861 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2364330861
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.4057064204
Short name T381
Test name
Test status
Simulation time 483452824 ps
CPU time 1.21 seconds
Started Apr 04 01:09:13 PM PDT 24
Finished Apr 04 01:09:14 PM PDT 24
Peak memory 201888 kb
Host smart-368aae99-3cb9-42e9-a4f6-6738bdfc42b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057064204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.4057064204
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1417092367
Short name T152
Test name
Test status
Simulation time 328684949218 ps
CPU time 144.47 seconds
Started Apr 04 01:09:03 PM PDT 24
Finished Apr 04 01:11:28 PM PDT 24
Peak memory 202228 kb
Host smart-0bbc22e6-07d7-44da-9be5-d5f096b6944b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417092367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1417092367
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2181864165
Short name T141
Test name
Test status
Simulation time 494317848760 ps
CPU time 294.4 seconds
Started Apr 04 01:08:49 PM PDT 24
Finished Apr 04 01:13:44 PM PDT 24
Peak memory 202248 kb
Host smart-296ad558-6757-420a-8081-49c1effb3ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181864165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2181864165
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2297666972
Short name T695
Test name
Test status
Simulation time 168258011472 ps
CPU time 53.68 seconds
Started Apr 04 01:08:54 PM PDT 24
Finished Apr 04 01:09:48 PM PDT 24
Peak memory 202044 kb
Host smart-8f17a239-a485-4d9f-a30b-9530127ec9bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297666972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2297666972
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.317488470
Short name T210
Test name
Test status
Simulation time 494151847248 ps
CPU time 246.3 seconds
Started Apr 04 01:08:51 PM PDT 24
Finished Apr 04 01:12:58 PM PDT 24
Peak memory 202172 kb
Host smart-5a134e01-3be7-4052-8fcf-0db2bbc30fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317488470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.317488470
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2426284474
Short name T366
Test name
Test status
Simulation time 325369474119 ps
CPU time 338.76 seconds
Started Apr 04 01:08:51 PM PDT 24
Finished Apr 04 01:14:30 PM PDT 24
Peak memory 202268 kb
Host smart-03fcbeea-dd7d-4bc3-ad55-53726eabe684
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426284474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2426284474
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2650081799
Short name T608
Test name
Test status
Simulation time 495400239526 ps
CPU time 1114.77 seconds
Started Apr 04 01:09:07 PM PDT 24
Finished Apr 04 01:27:42 PM PDT 24
Peak memory 202368 kb
Host smart-2dae4163-e5d4-4e8f-b781-b425e800adb2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650081799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2650081799
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.2783621573
Short name T610
Test name
Test status
Simulation time 417141833405 ps
CPU time 130.66 seconds
Started Apr 04 01:09:04 PM PDT 24
Finished Apr 04 01:11:15 PM PDT 24
Peak memory 202316 kb
Host smart-da1e55bc-880a-4a5a-a8b4-44d6b02ea351
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783621573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.2783621573
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.3346913069
Short name T407
Test name
Test status
Simulation time 93948017810 ps
CPU time 377.18 seconds
Started Apr 04 01:09:16 PM PDT 24
Finished Apr 04 01:15:33 PM PDT 24
Peak memory 202624 kb
Host smart-a6cb594e-e787-4f29-bd08-bf36c3452e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346913069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.3346913069
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.351590285
Short name T558
Test name
Test status
Simulation time 34959169904 ps
CPU time 39.89 seconds
Started Apr 04 01:09:04 PM PDT 24
Finished Apr 04 01:09:45 PM PDT 24
Peak memory 202020 kb
Host smart-d869d219-fb28-4ad2-9dd2-b3e4880b6191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351590285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.351590285
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.3090804754
Short name T652
Test name
Test status
Simulation time 3640105566 ps
CPU time 2.95 seconds
Started Apr 04 01:09:05 PM PDT 24
Finished Apr 04 01:09:08 PM PDT 24
Peak memory 202052 kb
Host smart-591ad108-bf5b-4e10-bea9-517062d53295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090804754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.3090804754
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.204200830
Short name T369
Test name
Test status
Simulation time 6136699954 ps
CPU time 15.83 seconds
Started Apr 04 01:08:54 PM PDT 24
Finished Apr 04 01:09:10 PM PDT 24
Peak memory 201992 kb
Host smart-273530e2-8d29-4c6a-9a46-6da09ff957c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204200830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.204200830
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1846119700
Short name T422
Test name
Test status
Simulation time 180071012006 ps
CPU time 225.94 seconds
Started Apr 04 01:09:18 PM PDT 24
Finished Apr 04 01:13:04 PM PDT 24
Peak memory 202288 kb
Host smart-8b515ca8-16ab-4dfb-b31d-b5e072dc316e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846119700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1846119700
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1806808953
Short name T275
Test name
Test status
Simulation time 106491004427 ps
CPU time 87.32 seconds
Started Apr 04 01:09:14 PM PDT 24
Finished Apr 04 01:10:41 PM PDT 24
Peak memory 210608 kb
Host smart-08016e38-3016-4470-a22a-efd461f8e2c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806808953 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1806808953
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.888087997
Short name T71
Test name
Test status
Simulation time 421047422 ps
CPU time 1 seconds
Started Apr 04 01:09:49 PM PDT 24
Finished Apr 04 01:09:50 PM PDT 24
Peak memory 201960 kb
Host smart-cb9d6fa2-8710-484f-baa7-fb5376ea5bb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888087997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.888087997
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.302593999
Short name T528
Test name
Test status
Simulation time 594769798919 ps
CPU time 342.74 seconds
Started Apr 04 01:09:42 PM PDT 24
Finished Apr 04 01:15:24 PM PDT 24
Peak memory 202372 kb
Host smart-98e397f9-d31a-479c-bd94-e287b4994b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302593999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.302593999
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2847016230
Short name T188
Test name
Test status
Simulation time 493556135157 ps
CPU time 314.21 seconds
Started Apr 04 01:09:29 PM PDT 24
Finished Apr 04 01:14:43 PM PDT 24
Peak memory 202196 kb
Host smart-d99f4540-8429-4ffe-a257-6a2cd23b1bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847016230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2847016230
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.126216709
Short name T97
Test name
Test status
Simulation time 330282829095 ps
CPU time 217.65 seconds
Started Apr 04 01:09:29 PM PDT 24
Finished Apr 04 01:13:07 PM PDT 24
Peak memory 202156 kb
Host smart-735e8ee1-b122-4b38-a4d9-8f203611175c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=126216709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.126216709
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2650132087
Short name T736
Test name
Test status
Simulation time 495979386085 ps
CPU time 604 seconds
Started Apr 04 01:09:14 PM PDT 24
Finished Apr 04 01:19:19 PM PDT 24
Peak memory 202196 kb
Host smart-fbba34a2-8719-4c4a-9f6e-55ba34ae3538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650132087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2650132087
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.504275858
Short name T733
Test name
Test status
Simulation time 169372046197 ps
CPU time 111.06 seconds
Started Apr 04 01:09:29 PM PDT 24
Finished Apr 04 01:11:20 PM PDT 24
Peak memory 202224 kb
Host smart-67cf90b6-de0a-4303-8edd-ec059198fea8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=504275858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.504275858
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.284851285
Short name T557
Test name
Test status
Simulation time 364845545392 ps
CPU time 865.5 seconds
Started Apr 04 01:09:28 PM PDT 24
Finished Apr 04 01:23:53 PM PDT 24
Peak memory 202112 kb
Host smart-250110ff-d0d7-4947-94ef-a9b34a2913de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284851285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_w
akeup.284851285
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.424729738
Short name T483
Test name
Test status
Simulation time 595508718467 ps
CPU time 1274.89 seconds
Started Apr 04 01:09:29 PM PDT 24
Finished Apr 04 01:30:44 PM PDT 24
Peak memory 202264 kb
Host smart-5fab7fa8-8609-44ae-9df0-afc35ab48f12
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424729738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.a
dc_ctrl_filters_wakeup_fixed.424729738
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.157433680
Short name T464
Test name
Test status
Simulation time 110711424495 ps
CPU time 537.62 seconds
Started Apr 04 01:09:42 PM PDT 24
Finished Apr 04 01:18:40 PM PDT 24
Peak memory 202668 kb
Host smart-9530600f-5306-4bfa-8dff-17fc88ad3506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157433680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.157433680
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3058480816
Short name T782
Test name
Test status
Simulation time 39122203665 ps
CPU time 46.39 seconds
Started Apr 04 01:09:39 PM PDT 24
Finished Apr 04 01:10:25 PM PDT 24
Peak memory 202092 kb
Host smart-6f09b7e1-848e-4231-a196-358ef8c608d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058480816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3058480816
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1411120419
Short name T600
Test name
Test status
Simulation time 4020204271 ps
CPU time 9.73 seconds
Started Apr 04 01:09:41 PM PDT 24
Finished Apr 04 01:09:51 PM PDT 24
Peak memory 201988 kb
Host smart-54596efd-bd74-4155-b4ca-9e6bd2befb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411120419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1411120419
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3801221924
Short name T498
Test name
Test status
Simulation time 5945128385 ps
CPU time 7.85 seconds
Started Apr 04 01:09:14 PM PDT 24
Finished Apr 04 01:09:22 PM PDT 24
Peak memory 202092 kb
Host smart-0d202fb6-e6c6-4eab-a9c9-333384f8b86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801221924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3801221924
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.630474281
Short name T34
Test name
Test status
Simulation time 169351011242 ps
CPU time 124.69 seconds
Started Apr 04 01:09:51 PM PDT 24
Finished Apr 04 01:11:56 PM PDT 24
Peak memory 202236 kb
Host smart-a8542b7e-ba03-497f-b793-f760954c32dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630474281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.630474281
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2309330202
Short name T40
Test name
Test status
Simulation time 73651134648 ps
CPU time 149.79 seconds
Started Apr 04 01:09:41 PM PDT 24
Finished Apr 04 01:12:11 PM PDT 24
Peak memory 210504 kb
Host smart-8a1001b9-fd40-4fc2-9283-b11566776b2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309330202 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2309330202
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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