Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6828	1			T8	111		T25	33		T37	9
testmodes[AdcCtrlTestmodeNormal]	5574	1			T2	1		T3	1		T4	1
testmodes[AdcCtrlTestmodeLowpower]	5586	1			T1	3		T3	1		T5	2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3663	1			T8	51		T25	9		T37	5
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1686	1			T8	25		T25	12		T37	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1372	1			T8	35		T25	12		T11	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1736	1			T8	27		T25	13		T37	3
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2100	1			T7	2		T8	31		T10	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1401	1			T3	1		T5	1		T8	35
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1314	1			T8	33		T25	11		T11	4
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1454	1			T8	37		T22	1		T25	11
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2564	1			T1	2		T5	1		T6	2