Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26057

1

T1

26

T2

8

T3

40

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22068

1

T1

1

T2

8

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3989

1

T1

25

T3

20

T5

50

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20111

1

T1

1

T3

20

T5

1

auto[1]

5946

1

T1

25

T2

8

T3

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22024

1

T1

26

T2

1

T3

22

auto[1]

4033

1

T2

7

T3

18

T5

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	84	1			T7	11		T221	26		T153	1
values[0]	30	1			T198	16		T132	1		T222	3
values[1]	711	1			T5	27		T8	3		T10	1
values[2]	3059	1			T1	17		T2	8		T3	20
values[3]	534	1			T20	4		T89	4		T121	24
values[4]	867	1			T1	8		T7	1		T136	20
values[5]	473	1			T3	20		T36	11		T121	22
values[6]	724	1			T5	1		T7	1		T20	17
values[7]	667	1			T5	23		T8	8		T90	1
values[8]	644	1			T10	1		T120	10		T137	6
values[9]	1231	1			T1	1		T8	27		T11	7
minimum	17033	1			T8	297		T25	107		T37	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1028	1			T1	17		T5	27		T8	3
values[1]	2948	1			T2	8		T3	20		T4	1
values[2]	659	1			T1	8		T89	4		T136	20
values[3]	657	1			T3	20		T7	1		T121	22
values[4]	445	1			T26	1		T36	11		T39	19
values[5]	689	1			T5	24		T20	17		T22	13
values[6]	829	1			T7	1		T8	8		T22	25
values[7]	682	1			T223	28		T128	8		T138	1
values[8]	831	1			T1	1		T7	11		T10	1
values[9]	256	1			T8	27		T224	24		T122	9
minimum	17033	1			T8	297		T25	107		T37	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

4036

1

T1

23

T3

20

T5

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T8	1		T10	1		T36	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T1	17		T5	14		T22	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1519	1			T2	1		T4	1		T6	39
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T3	12		T8	15		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T89	1		T207	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T1	8		T136	10		T121	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T3	10		T7	1		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T121	9		T143	6		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T26	1		T127	10		T31	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T36	11		T39	11		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T5	1		T47	5		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T5	12		T20	9		T22	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T7	1		T8	4		T22	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T120	1		T209	3		T225	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T124	2		T221	1		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T223	14		T128	4		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T1	1		T227	1		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T7	1		T10	1		T11	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T224	12		T228	13		T134	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T8	6		T122	1		T33	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16899	1			T8	296		T25	107		T37	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T8	2		T152	10		T177	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T5	13		T22	17		T120	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	897	1			T2	7		T9	10		T23	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T3	8		T8	2		T137	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T89	3		T142	1		T12	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T136	10		T121	12		T123	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	10		T122	13		T28	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T121	13		T143	8		T28	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T31	1		T144	10		T152	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T39	8		T137	1		T229	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T151	7		T34	1		T15	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	11		T20	8		T22	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T8	4		T22	10		T32	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T120	9		T209	5		T186	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T230	7		T231	6		T66	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T223	14		T128	4		T34	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T120	6		T207	10		T122	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	10		T11	3		T221	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T224	12		T228	10		T134	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T8	21		T122	8		T33	21
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	1		T58	1		T31	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T7	1		T221	13		T153	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T232	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T198	1		T132	1		T222	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T8	1		T10	1		T36	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T5	14		T120	1		T121	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1503	1			T2	1		T4	1		T6	39
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T1	17		T3	12		T8	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T20	4		T89	1		T207	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T121	12		T32	8		T143	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T7	1		T12	8		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T1	8		T136	10		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T3	10		T127	10		T31	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T36	11		T121	9		T39	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T5	1		T7	1		T22	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T20	9		T22	6		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T8	4		T185	12		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T5	12		T90	1		T223	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T137	6		T124	2		T233	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T10	1		T120	1		T128	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	365	1			T1	1		T227	1		T120	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T8	6		T11	4		T227	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16899	1			T8	296		T25	107		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T7	10		T221	13		T18	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T198	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	2		T223	3		T152	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	13		T120	10		T121	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	928	1			T2	7		T9	10		T23	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T3	8		T8	2		T22	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T89	3		T142	1		T226	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T121	12		T32	7		T143	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	8		T122	13		T152	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T136	10		T123	8		T32	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T3	10		T31	1		T144	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T121	13		T39	8		T234	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T22	10		T151	7		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T20	8		T22	7		T137	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T8	4		T32	4		T35	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T5	11		T223	14		T209	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T233	6		T235	2		T231	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T120	9		T128	4		T186	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T120	6		T207	10		T224	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T8	21		T11	3		T122	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	1		T58	1		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T8	3		T10	1		T36	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	355	1			T1	1		T5	14		T22	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1218	1			T2	8		T4	1		T6	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T3	9		T8	3		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T89	4		T207	1		T142	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T1	1		T136	11		T121	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T3	11		T7	1		T122	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T121	14		T143	9		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T26	1		T127	1		T31	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T36	1		T39	9		T137	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	1		T47	1		T151	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T5	12		T20	9		T22	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T7	1		T8	7		T22	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T120	10		T209	6		T225	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T124	2		T221	1		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T223	15		T128	5		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	1		T227	1		T120	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T7	11		T10	1		T11	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T224	13		T228	11		T134	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T8	24		T122	9		T33	27
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17033	1			T8	297		T25	107		T37	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T36	14		T152	5		T177	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T1	16		T5	13		T22	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1198	1			T6	36		T20	3		T21	40
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T3	11		T8	14		T137	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T12	3		T152	10		T149	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	7		T136	9		T121	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T3	9		T19	3		T236	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T121	8		T143	5		T237	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T127	9		T144	9		T152	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T36	10		T39	10		T229	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T47	4		T34	1		T15	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	11		T20	8		T22	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T8	1		T22	14		T137	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T209	2		T186	15		T144	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T145	11		T238	2		T230	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T223	13		T128	3		T239	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T127	10		T240	7		T35	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	2		T36	7		T241	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T224	11		T228	12		T134	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T8	3		T33	4		T187	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T7	11		T221	14		T153	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T232	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T198	16		T132	1		T222	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T8	3		T10	1		T36	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T5	14		T120	11		T121	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1249	1			T2	8		T4	1		T6	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T1	1		T3	9		T8	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T20	1		T89	4		T207	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T121	13		T32	11		T143	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T7	1		T12	13		T122	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T1	1		T136	11		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T3	11		T127	1		T31	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T36	1		T121	14		T39	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	1		T7	1		T22	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T20	9		T22	8		T137	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T8	7		T185	1		T130	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	12		T90	1		T223	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T137	1		T124	2		T233	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T10	1		T120	10		T128	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T1	1		T227	1		T120	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	362	1			T8	24		T11	5		T227	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17033	1			T8	297		T25	107		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T221	12		T242	16		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T222	2		T243	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T36	14		T152	5		T244	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T5	13		T121	11		T142	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1182	1			T6	36		T21	40		T245	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T1	16		T3	11		T8	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T20	3		T246	9		T236	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T121	11		T32	4		T143	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T12	3		T152	10		T149	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T1	7		T136	9		T123	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T3	9		T127	9		T144	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T36	10		T121	8		T39	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T22	14		T47	4		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T20	8		T22	5		T223	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T8	1		T185	11		T32	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T5	11		T223	13		T127	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T137	5		T233	1		T238	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T128	3		T186	15		T144	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T224	11		T127	10		T240	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T8	3		T11	2		T36	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

auto[0]

4036

1

T1

23

T3

20

T5

24

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26057

1

T1

26

T2

8

T3

40

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22441

1

T2

8

T3

40

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3616

1

T1

26

T5

23

T7

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20110

1

T1

1

T3

20

T5

24

auto[1]

5947

1

T1

25

T2

8

T3

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22024

1

T1

26

T2

1

T3

22

auto[1]

4033

1

T2

7

T3

18

T5

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	14	1			T234	13		T226	1		-	-
values[0]	49	1			T36	11		T198	16		T164	3
values[1]	689	1			T22	31		T89	4		T47	5
values[2]	701	1			T3	20		T20	4		T22	38
values[3]	688	1			T5	27		T7	1		T8	27
values[4]	633	1			T5	1		T120	10		T121	24
values[5]	3066	1			T2	8		T4	1		T6	39
values[6]	709	1			T1	8		T5	23		T8	17
values[7]	490	1			T7	1		T10	1		T36	8
values[8]	718	1			T1	17		T8	3		T26	1
values[9]	1267	1			T1	1		T3	20		T7	11
minimum	17033	1			T8	297		T25	107		T37	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	915	1			T22	31		T89	4		T36	11
values[1]	720	1			T3	20		T7	1		T10	1
values[2]	619	1			T5	27		T8	27		T20	17
values[3]	2893	1			T2	8		T4	1		T5	1
values[4]	798	1			T90	1		T227	1		T120	7
values[5]	663	1			T1	8		T5	23		T8	17
values[6]	579	1			T7	1		T10	1		T36	8
values[7]	865	1			T1	1		T8	11		T26	1
values[8]	826	1			T1	17		T3	20		T7	11
values[9]	141	1			T121	24		T247	1		T130	1
minimum	17038	1			T8	297		T25	107		T37	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

4036

1

T1

23

T3

20

T5

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T89	1		T137	6		T223	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T22	14		T36	11		T127	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T3	12		T20	4		T22	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T7	1		T10	1		T22	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T5	14		T8	6		T20	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T39	11		T122	1		T123	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1579	1			T2	1		T4	1		T5	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T120	1		T121	12		T248	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T90	1		T36	15		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T227	1		T120	1		T13	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T227	1		T223	12		T234	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T1	8		T5	12		T8	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T10	1		T137	6		T124	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	1		T36	8		T207	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T8	1		T26	1		T223	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T1	1		T8	4		T249	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T3	10		T142	1		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T1	17		T7	1		T120	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T121	12		T247	1		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T250	8		T236	4		T251	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16899	1			T8	296		T25	107		T37	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T47	5		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T89	3		T137	12		T223	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T22	17		T229	10		T35	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	8		T22	10		T136	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T22	7		T11	3		T122	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T5	13		T8	21		T20	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T39	8		T122	13		T123	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	929	1			T2	7		T9	10		T23	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T120	9		T121	12		T221	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T12	8		T237	2		T252	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T120	6		T13	3		T33	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T223	6		T233	17		T35	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T5	11		T8	2		T121	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T177	9		T252	10		T253	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T225	9		T229	6		T144	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T8	2		T223	14		T32	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T8	4		T144	9		T254	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T3	10		T142	1		T15	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	10		T120	10		T224	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T121	12		T234	12		T226	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T250	2		T236	3		T251	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	1		T58	1		T31	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T234	1		T226	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T198	1		T164	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T36	11		T255	9		T166	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T89	1		T137	6		T223	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T22	14		T47	5		T127	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T3	12		T20	4		T22	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T22	6		T11	4		T58	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T5	14		T8	6		T20	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	1		T10	1		T39	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	1		T127	10		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T120	1		T121	12		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1584	1			T2	1		T4	1		T6	39
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T227	1		T13	2		T33	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T90	1		T227	1		T36	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T1	8		T5	12		T8	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T10	1		T234	1		T256	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T7	1		T36	8		T121	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T8	1		T26	1		T137	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T1	17		T249	1		T144	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	343	1			T3	10		T121	12		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	396	1			T1	1		T7	1		T8	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16899	1			T8	296		T25	107		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T234	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T198	15		T164	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T255	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T89	3		T137	12		T223	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T22	17		T229	10		T35	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	8		T22	10		T136	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T22	7		T11	3		T122	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	13		T8	21		T20	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T39	8		T122	13		T233	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T257	1		T230	7		T217	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T120	9		T121	12		T230	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	934	1			T2	7		T9	10		T23	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T33	21		T221	13		T233	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T223	6		T233	17		T35	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T5	11		T8	2		T120	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T234	11		T253	10		T258	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T121	13		T225	9		T229	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T8	2		T223	14		T32	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T144	10		T254	13		T152	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T3	10		T121	12		T142	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T7	10		T8	4		T120	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	1		T58	1		T31	1