Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26057

1

T1

26

T2

8

T3

40

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22665

1

T1

25

T2

8

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3392

1

T1

1

T3

20

T5

50

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20203

1

T5

1

T7

2

T8

308

auto[1]

5854

1

T1

26

T2

8

T3

40

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22024

1

T1

26

T2

1

T3

22

auto[1]

4033

1

T2

7

T3

18

T5

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	7	1			T252	5		T328	1		T329	1
values[0]	69	1			T5	1		T144	1		T234	1
values[1]	660	1			T7	1		T20	17		T22	13
values[2]	549	1			T7	1		T89	4		T137	20
values[3]	891	1			T10	1		T22	25		T227	1
values[4]	561	1			T8	27		T36	11		T121	24
values[5]	2818	1			T1	17		T2	8		T3	20
values[6]	792	1			T1	1		T7	11		T8	25
values[7]	673	1			T1	8		T10	1		T11	7
values[8]	621	1			T3	20		T5	23		T207	12
values[9]	1383	1			T5	27		T8	3		T20	4
minimum	17033	1			T8	297		T25	107		T37	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	808	1			T5	1		T7	1		T20	17
values[1]	592	1			T7	1		T10	1		T22	25
values[2]	845	1			T8	27		T227	1		T36	11
values[3]	2798	1			T1	17		T2	8		T4	1
values[4]	673	1			T36	15		T161	1		T58	1
values[5]	695	1			T1	1		T3	20		T7	11
values[6]	650	1			T1	8		T3	20		T10	1
values[7]	727	1			T5	23		T36	8		T207	1
values[8]	841	1			T5	27		T8	3		T20	4
values[9]	353	1			T47	5		T125	7		T133	28
minimum	17075	1			T8	297		T25	107		T37	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

4036

1

T1

23

T3

20

T5

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T5	1		T7	1		T89	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T20	9		T22	6		T123	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T10	1		T137	6		T127	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T7	1		T22	15		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T8	6		T36	11		T128	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T227	1		T39	11		T249	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1520	1			T1	17		T2	1		T4	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T136	10		T121	12		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T36	15		T161	1		T12	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T58	1		T225	2		T241	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	12		T8	15		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	1		T7	1		T8	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T1	8		T10	1		T11	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	10		T120	1		T207	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T161	1		T30	2		T13	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T5	12		T36	8		T207	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T8	1		T20	4		T26	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T5	14		T120	1		T122	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T47	5		T125	1		T133	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T147	1		T231	1		T178	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16906	1			T8	296		T25	107		T37	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T229	1		T28	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T89	3		T121	25		T223	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T20	8		T22	7		T123	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T137	12		T209	5		T217	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T22	10		T137	1		T122	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T8	21		T128	4		T198	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T39	8		T234	11		T257	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	887	1			T2	7		T9	10		T22	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T136	10		T121	12		T142	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T12	8		T31	1		T229	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T225	9		T152	10		T276	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T3	8		T8	2		T120	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T7	10		T8	4		T123	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	3		T224	12		T223	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T3	10		T120	9		T207	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T33	21		T253	10		T330	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T5	11		T32	4		T34	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T8	2		T142	1		T151	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T5	13		T120	6		T122	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T125	6		T133	15		T231	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T147	7		T231	9		T66	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T8	1		T58	1		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T229	10		T28	12		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T252	1		T329	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T328	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T5	1		T234	1		T260	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T144	1		T182	12		T331	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	1		T121	21		T124	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T20	9		T22	6		T123	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T89	1		T137	6		T223	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T7	1		T137	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T10	1		T142	11		T127	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T22	15		T227	1		T136	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T8	6		T36	11		T128	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T121	12		T39	11		T223	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1593	1			T1	17		T2	1		T3	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T142	1		T58	1		T124	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T8	15		T224	12		T185	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T1	1		T7	1		T8	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T1	8		T10	1		T11	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T120	1		T15	2		T230	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T161	1		T30	2		T13	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T3	10		T5	12		T207	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T8	1		T20	4		T26	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	441	1			T5	14		T120	1		T36	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16899	1			T8	296		T25	107		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T252	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T332	1		T318	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T182	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T121	25		T192	10		T134	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T20	8		T22	7		T123	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T89	3		T137	12		T223	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T137	1		T34	10		T235	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T142	7		T198	15		T221	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T22	10		T136	10		T122	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	21		T128	4		T32	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T121	12		T39	8		T223	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	928	1			T2	7		T3	8		T9	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T142	1		T225	9		T152	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	2		T224	12		T240	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T7	10		T8	4		T123	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	3		T120	10		T223	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T120	9		T230	10		T333	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T33	21		T144	10		T152	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T3	10		T5	11		T207	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T8	2		T142	1		T151	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T5	13		T120	6		T122	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	1		T58	1		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T5	1		T7	1		T89	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T20	9		T22	8		T123	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T10	1		T137	13		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	1		T22	11		T137	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T8	24		T36	1		T128	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T227	1		T39	9		T249	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1195	1			T1	1		T2	8		T4	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T136	11		T121	13		T142	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T36	1		T161	1		T12	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T58	1		T225	11		T241	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T3	9		T8	3		T120	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T1	1		T7	11		T8	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T1	1		T10	1		T11	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T3	11		T120	10		T207	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T161	1		T30	2		T13	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T5	12		T36	1		T207	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T8	3		T20	1		T26	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T5	14		T120	7		T122	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T47	1		T125	7		T133	23
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T147	8		T231	10		T178	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17045	1			T8	297		T25	107		T37	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T229	11		T28	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T121	19		T223	13		T230	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T20	8		T22	5		T123	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T137	5		T127	9		T209	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T22	14		T186	15		T238	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T8	3		T36	10		T128	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T39	10		T257	1		T217	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1212	1			T1	16		T6	36		T21	40
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T136	9		T121	11		T223	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T36	14		T12	3		T229	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T241	4		T291	12		T152	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	11		T8	14		T127	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T8	1		T137	5		T123	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	7		T11	2		T224	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	9		T146	14		T230	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T33	4		T253	8		T263	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	11		T36	7		T127	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T20	3		T143	5		T145	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T5	13		T144	7		T271	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T47	4		T133	5		T253	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T66	17		T163	8		T29	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T302	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T252	5		T329	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T328	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T5	1		T234	1		T260	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T144	1		T182	14		T331	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	1		T121	27		T124	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T20	9		T22	8		T123	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T89	4		T137	13		T223	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T7	1		T137	2		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T10	1		T142	8		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T22	11		T227	1		T136	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T8	24		T36	1		T128	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T121	13		T39	9		T223	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1251	1			T1	1		T2	8		T3	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T142	2		T58	1		T124	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T8	3		T224	13		T185	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T1	1		T7	11		T8	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T1	1		T10	1		T11	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T120	10		T15	2		T230	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T161	1		T30	2		T13	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T3	11		T5	12		T207	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T8	3		T20	1		T26	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	441	1			T5	14		T120	7		T36	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17033	1			T8	297		T25	107		T37	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T260	12		T318	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T182	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T121	19		T134	2		T261	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T20	8		T22	5		T123	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T137	5		T223	13		T209	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T238	2		T235	2		T237	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T142	10		T127	9		T221	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T22	14		T136	9		T186	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T8	3		T36	10		T128	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T121	11		T39	10		T223	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1270	1			T1	16		T3	11		T6	36
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T241	4		T291	12		T152	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T8	14		T224	11		T185	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T8	1		T137	5		T123	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	7		T11	2		T127	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T230	10		T246	9		T334	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T33	4		T144	9		T152	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T3	9		T5	11		T127	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T20	3		T47	4		T143	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	353	1			T5	13		T36	7		T144	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

auto[0]

4036

1

T1

23

T3

20

T5

24