Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26057

1

T1

26

T2

8

T3

40

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22348

1

T2

8

T3

40

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3709

1

T1

26

T5

23

T7

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20077

1

T1

1

T3

20

T5

24

auto[1]

5980

1

T1

25

T2

8

T3

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22024

1

T1

26

T2

1

T3

22

auto[1]

4033

1

T2

7

T3

18

T5

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	178	1			T130	1		T131	1		T226	1
values[0]	15	1			T36	11		T223	4		-	-
values[1]	785	1			T22	31		T89	4		T47	5
values[2]	708	1			T3	20		T10	1		T20	4
values[3]	606	1			T5	27		T7	1		T8	27
values[4]	623	1			T5	1		T120	10		T121	24
values[5]	3085	1			T2	8		T4	1		T6	39
values[6]	687	1			T1	8		T5	23		T8	17
values[7]	500	1			T7	1		T10	1		T36	8
values[8]	752	1			T1	17		T8	3		T26	1
values[9]	1085	1			T1	1		T3	20		T7	11
minimum	17033	1			T8	297		T25	107		T37	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	799	1			T22	56		T89	4		T47	5
values[1]	651	1			T3	20		T8	27		T10	1
values[2]	591	1			T5	27		T7	1		T20	17
values[3]	2834	1			T2	8		T4	1		T5	1
values[4]	870	1			T90	1		T227	1		T120	7
values[5]	673	1			T1	8		T5	23		T8	17
values[6]	524	1			T7	1		T10	1		T36	8
values[7]	815	1			T1	17		T8	11		T26	1
values[8]	919	1			T1	1		T3	20		T7	11
values[9]	127	1			T121	24		T130	1		T131	1
minimum	17254	1			T8	297		T25	107		T37	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

4036

1

T1

23

T3

20

T5

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T22	15		T47	5		T137	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T22	14		T89	1		T127	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T3	12		T8	6		T20	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T10	1		T22	6		T11	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	14		T20	9		T192	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T7	1		T39	11		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1551	1			T2	1		T4	1		T5	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T120	1		T121	12		T248	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T90	1		T36	15		T12	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T227	1		T120	1		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T227	1		T223	12		T234	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	8		T5	12		T8	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T10	1		T124	1		T248	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	1		T36	8		T207	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T8	1		T26	1		T137	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T1	17		T8	4		T223	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T3	10		T142	1		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T1	1		T7	1		T120	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T121	12		T130	1		T226	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T131	1		T236	4		T260	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16929	1			T8	296		T25	107		T37	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T36	11		T269	13		T16	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T22	10		T137	12		T128	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T22	17		T89	3		T229	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	8		T8	21		T136	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T22	7		T11	3		T123	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	13		T20	8		T192	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T39	8		T122	13		T134	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	916	1			T2	7		T9	10		T23	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T120	9		T121	12		T221	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	8		T252	4		T285	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T120	6		T13	3		T33	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T223	6		T35	3		T288	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T5	11		T8	2		T121	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T177	9		T252	10		T253	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T225	9		T229	6		T144	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T8	2		T32	5		T234	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T8	4		T223	14		T144	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T3	10		T142	1		T137	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	10		T120	10		T224	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T121	12		T226	7		T335	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T236	3		T336	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	1		T58	1		T223	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T16	3		T66	19		T255	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T130	1		T337	1		T235	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T131	1		T226	1		T250	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T223	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T36	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T47	5		T137	6		T128	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T22	14		T89	1		T127	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	12		T20	4		T22	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T10	1		T22	6		T123	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	14		T8	6		T20	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T7	1		T11	4		T39	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	1		T127	10		T125	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T120	1		T121	12		T145	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1585	1			T2	1		T4	1		T6	39
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T227	1		T161	1		T13	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T227	1		T36	15		T223	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	8		T5	12		T8	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T10	1		T124	1		T234	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	1		T36	8		T121	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T8	1		T26	1		T137	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T1	17		T223	14		T249	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T3	10		T121	12		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T1	1		T7	1		T8	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16899	1			T8	296		T25	107		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T235	10		T276	2		T335	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T250	2		T236	3		T262	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T223	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T137	12		T128	4		T122	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T22	17		T89	3		T229	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	8		T22	10		T136	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T22	7		T123	8		T186	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	13		T8	21		T20	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	3		T39	8		T122	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T125	6		T228	10		T257	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T120	9		T121	12		T230	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	974	1			T2	7		T9	10		T23	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T33	21		T221	13		T233	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T223	6		T35	3		T288	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T5	11		T8	2		T120	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T234	11		T253	10		T258	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T121	13		T225	9		T229	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T8	2		T32	5		T28	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T223	14		T144	19		T254	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T3	10		T121	12		T142	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T7	10		T8	4		T120	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	1		T58	1		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T22	11		T47	1		T137	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T22	18		T89	4		T127	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T3	9		T8	24		T20	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T10	1		T22	8		T11	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T5	14		T20	9		T192	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	1		T39	9		T122	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1239	1			T2	8		T4	1		T5	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T120	10		T121	13		T248	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T90	1		T36	1		T12	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T227	1		T120	7		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T227	1		T223	7		T234	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	1		T5	12		T8	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T10	1		T124	1		T248	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T7	1		T36	1		T207	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T8	3		T26	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T1	1		T8	7		T223	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T3	11		T142	2		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T1	1		T7	11		T120	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T121	13		T130	1		T226	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T131	1		T236	4		T260	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17082	1			T8	297		T25	107		T37	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T36	1		T269	1		T16	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T22	14		T47	4		T137	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T22	13		T127	15		T35	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	11		T8	3		T20	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T22	5		T11	2		T123	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T5	13		T20	8		T32	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T39	10		T134	2		T270	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1228	1			T6	36		T21	40		T245	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T121	11		T221	12		T145	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T36	14		T12	3		T146	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T33	4		T233	9		T237	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T223	11		T35	2		T146	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	7		T5	11		T8	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T177	9		T253	8		T258	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T36	7		T229	5		T144	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T137	5		T32	6		T238	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T1	16		T8	1		T223	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	9		T15	2		T133	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T224	11		T123	12		T32	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T121	11		T216	19		T259	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T236	3		T260	12		T336	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T280	9		T312	9		T165	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T36	10		T269	12		T66	17

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T130	1		T337	1		T235	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T131	1		T226	1		T250	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T223	4		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T36	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T47	1		T137	13		T128	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T22	18		T89	4		T127	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	9		T20	1		T22	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T10	1		T22	8		T123	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T5	14		T8	24		T20	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T7	1		T11	5		T39	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T5	1		T127	1		T125	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T120	10		T121	13		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1299	1			T2	8		T4	1		T6	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T227	1		T161	1		T13	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T227	1		T36	1		T223	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T1	1		T5	12		T8	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T10	1		T124	1		T234	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	1		T36	1		T121	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	3		T26	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T1	1		T223	15		T249	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T3	11		T121	13		T142	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T1	1		T7	11		T8	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17033	1			T8	297		T25	107		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T235	4		T149	12		T253	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T250	2		T222	7		T236	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T36	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T47	4		T137	5		T128	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T22	13		T127	15		T35	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	11		T20	3		T22	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T22	5		T123	9		T186	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T5	13		T8	3		T20	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T11	2		T39	10		T134	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T127	9		T228	12		T257	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T121	11		T145	11		T230	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1260	1			T6	36		T21	40		T245	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T33	4		T221	12		T233	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T36	14		T223	11		T35	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	7		T5	11		T8	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T253	8		T258	15		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T36	7		T121	8		T185	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T137	5		T32	6		T238	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T1	16		T223	13		T144	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	9		T121	11		T15	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T8	1		T224	11		T123	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

auto[0]

4036

1

T1

23

T3

20

T5

24