Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26057

1

T1

26

T2

8

T3

40

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22644

1

T1

8

T2

8

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3413

1

T1

18

T3

20

T5

50

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20248

1

T5

1

T7

2

T8

308

auto[1]

5809

1

T1

26

T2

8

T3

40

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22024

1

T1

26

T2

1

T3

22

auto[1]

4033

1

T2

7

T3

18

T5

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	387	1			T227	1		T47	5		T122	5
values[0]	32	1			T5	1		T144	1		T332	4
values[1]	733	1			T7	1		T20	17		T22	13
values[2]	508	1			T7	1		T10	1		T89	4
values[3]	838	1			T22	25		T227	1		T142	18
values[4]	622	1			T8	27		T36	11		T136	20
values[5]	2859	1			T1	17		T2	8		T4	1
values[6]	706	1			T1	1		T3	20		T7	11
values[7]	679	1			T1	8		T11	7		T120	21
values[8]	676	1			T3	20		T5	23		T10	1
values[9]	984	1			T5	27		T8	3		T20	4
minimum	17033	1			T8	297		T25	107		T37	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	691	1			T7	1		T89	4		T121	46
values[1]	514	1			T7	1		T10	1		T22	25
values[2]	901	1			T8	27		T227	1		T36	11
values[3]	2716	1			T1	17		T2	8		T4	1
values[4]	690	1			T1	1		T36	15		T161	1
values[5]	724	1			T3	20		T7	11		T8	25
values[6]	646	1			T1	8		T3	20		T10	1
values[7]	714	1			T5	23		T36	8		T207	12
values[8]	931	1			T5	27		T8	3		T20	4
values[9]	269	1			T47	5		T125	7		T231	17
minimum	17261	1			T5	1		T8	297		T20	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

4036

1

T1

23

T3

20

T5

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T7	1		T89	1		T121	21
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T229	1		T35	12		T254	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T10	1		T137	6		T127	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T7	1		T22	15		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T8	6		T36	11		T142	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T227	1		T39	11		T186	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1467	1			T2	1		T4	1		T6	39
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T1	17		T136	10		T121	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T36	15		T161	1		T12	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T1	1		T58	1		T225	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	12		T8	15		T120	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T7	1		T8	4		T90	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T1	8		T10	1		T11	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	10		T120	1		T146	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T161	1		T30	2		T13	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T5	12		T36	8		T207	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T8	1		T26	1		T227	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T5	14		T20	4		T120	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T47	5		T125	1		T231	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T231	1		T66	18		T163	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16959	1			T5	1		T8	296		T25	107
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T20	9		T22	6		T123	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T89	3		T121	25		T223	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T229	10		T35	11		T254	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T137	12		T209	5		T15	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T22	10		T137	1		T122	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T8	21		T142	7		T128	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T39	8		T186	9		T234	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	855	1			T2	7		T9	10		T22	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T136	10		T121	12		T142	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T12	8		T31	1		T229	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T225	9		T276	2		T164	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T3	8		T8	2		T120	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T7	10		T8	4		T123	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T11	3		T224	12		T223	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T3	10		T120	9		T230	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T33	21		T152	10		T253	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T5	11		T207	10		T32	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T8	2		T142	1		T151	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T5	13		T120	6		T122	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T125	6		T231	6		T71	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T231	9		T66	19		T163	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T8	1		T58	1		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T20	8		T22	7		T123	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T227	1		T47	5		T125	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T122	1		T146	7		T231	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T5	1		T332	3		T290	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T144	1		T182	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	1		T121	21		T124	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T20	9		T22	6		T123	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T10	1		T89	1		T137	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T7	1		T137	1		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T142	11		T127	10		T198	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T22	15		T227	1		T39	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T8	6		T36	11		T128	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T136	10		T121	12		T223	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1612	1			T2	1		T4	1		T6	39
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T1	17		T142	1		T58	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	12		T8	15		T185	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T1	1		T7	1		T8	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T1	8		T11	4		T120	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T120	1		T230	11		T246	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T10	1		T161	1		T30	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T3	10		T5	12		T36	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T8	1		T26	1		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T5	14		T20	4		T120	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16899	1			T8	296		T25	107		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T125	6		T143	8		T28	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T122	4		T231	9		T66	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T332	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T182	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T121	25		T192	10		T134	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T20	8		T22	7		T123	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T89	3		T137	12		T223	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T137	1		T226	7		T34	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T142	7		T198	15		T221	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T22	10		T39	8		T122	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T8	21		T128	4		T32	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T136	10		T121	12		T223	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	984	1			T2	7		T9	10		T22	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T142	1		T225	9		T276	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T3	8		T8	2		T240	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T7	10		T8	4		T123	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	3		T120	10		T224	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T120	9		T230	10		T333	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T13	3		T33	21		T144	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	10		T5	11		T207	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T8	2		T142	1		T151	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T5	13		T120	6		T122	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	1		T58	1		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T7	1		T89	4		T121	27
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T229	11		T35	16		T254	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T10	1		T137	13		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	1		T22	11		T137	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T8	24		T36	1		T142	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T227	1		T39	9		T186	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1160	1			T2	8		T4	1		T6	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T1	1		T136	11		T121	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T36	1		T161	1		T12	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T1	1		T58	1		T225	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T3	9		T8	3		T120	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T7	11		T8	7		T90	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T1	1		T10	1		T11	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T3	11		T120	10		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T161	1		T30	2		T13	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T5	12		T36	1		T207	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T8	3		T26	1		T227	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T5	14		T20	1		T120	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T47	1		T125	7		T231	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T231	10		T66	20		T163	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17094	1			T5	1		T8	297		T25	107
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T20	9		T22	8		T123	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T121	19		T223	13		T230	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T35	7		T16	1		T149	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T137	5		T127	9		T209	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T22	14		T238	2		T235	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T8	3		T36	10		T142	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T39	10		T186	15		T257	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1162	1			T6	36		T21	40		T22	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T1	16		T136	9		T121	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T36	14		T12	3		T229	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T241	4		T291	12		T274	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T3	11		T8	14		T127	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T8	1		T137	5		T123	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T1	7		T11	2		T224	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	9		T146	14		T230	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T33	4		T152	5		T253	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T5	11		T36	7		T127	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T143	5		T145	11		T133	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	13		T20	3		T144	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T47	4		T253	2		T258	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T66	17		T163	8		T29	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T260	12		T264	9		T318	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T20	8		T22	5		T123	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T227	1		T47	1		T125	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T122	5		T146	1		T231	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T5	1		T332	4		T290	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T144	1		T182	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T7	1		T121	27		T124	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T20	9		T22	8		T123	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T10	1		T89	4		T137	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	1		T137	2		T132	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T142	8		T127	1		T198	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T22	11		T227	1		T39	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T8	24		T36	1		T128	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T136	11		T121	13		T223	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1313	1			T2	8		T4	1		T6	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T1	1		T142	2		T58	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	9		T8	3		T185	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T1	1		T7	11		T8	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T1	1		T11	5		T120	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T120	10		T230	11		T246	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T10	1		T161	1		T30	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T3	11		T5	12		T36	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T8	3		T26	1		T142	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T5	14		T20	1		T120	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17033	1			T8	297		T25	107		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T47	4		T143	5		T66	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T146	6		T66	17		T338	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T182	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T121	19		T134	2		T261	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T20	8		T22	5		T123	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T137	5		T223	13		T209	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T238	2		T235	2		T237	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T142	10		T127	9		T221	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T22	14		T39	10		T186	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T8	3		T36	10		T128	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T136	9		T121	11		T223	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T6	36		T21	40		T22	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T1	16		T241	4		T291	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	11		T8	14		T185	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T8	1		T137	5		T123	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T1	7		T11	2		T224	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T230	10		T246	9		T334	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T33	4		T144	9		T152	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	9		T5	11		T36	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T145	11		T133	5		T237	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T5	13		T20	3		T144	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

auto[0]

4036

1

T1

23

T3

20

T5

24