Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26057

1

T1

26

T2

8

T3

40

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22106

1

T1

1

T2

8

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3951

1

T1

25

T3

20

T5

50

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20134

1

T1

1

T3

20

T5

1

auto[1]

5923

1

T1

25

T2

8

T3

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22024

1

T1

26

T2

1

T3

22

auto[1]

4033

1

T2

7

T3

18

T5

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	252	1			T11	7		T227	1		T224	24
values[0]	39	1			T132	1		T222	3		T326	7
values[1]	714	1			T5	27		T8	3		T10	1
values[2]	3053	1			T1	17		T2	8		T3	20
values[3]	542	1			T1	8		T20	4		T89	4
values[4]	793	1			T7	1		T136	20		T12	16
values[5]	504	1			T3	20		T36	11		T121	22
values[6]	679	1			T5	1		T20	17		T22	13
values[7]	751	1			T5	23		T7	1		T8	8
values[8]	670	1			T10	1		T137	6		T128	8
values[9]	1027	1			T1	1		T7	11		T8	27
minimum	17033	1			T8	297		T25	107		T37	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	837	1			T1	17		T8	3		T10	1
values[1]	2875	1			T2	8		T3	20		T4	1
values[2]	732	1			T1	8		T89	4		T136	20
values[3]	598	1			T3	20		T7	1		T121	22
values[4]	501	1			T26	1		T36	11		T39	19
values[5]	655	1			T5	1		T20	17		T22	38
values[6]	845	1			T5	23		T7	1		T8	8
values[7]	690	1			T10	1		T128	8		T124	1
values[8]	838	1			T1	1		T7	11		T11	7
values[9]	204	1			T8	27		T224	24		T122	9
minimum	17282	1			T5	27		T8	297		T25	107

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

4036

1

T1

23

T3

20

T5

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T8	1		T10	1		T36	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T1	17		T22	14		T120	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1531	1			T2	1		T4	1		T6	39
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T3	12		T8	15		T137	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T89	1		T142	1		T12	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T1	8		T136	10		T121	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T3	10		T7	1		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T121	9		T143	6		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T26	1		T127	10		T31	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T36	11		T39	11		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	1		T22	15		T47	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T20	9		T22	6		T223	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T7	1		T8	4		T137	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T5	12		T90	1		T120	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T124	1		T221	1		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T10	1		T128	4		T186	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T1	1		T227	1		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T7	1		T11	4		T227	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T224	12		T228	13		T280	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T8	6		T122	1		T33	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16940	1			T8	296		T25	107		T37	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T5	14		T142	1		T230	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T8	2		T152	10		T177	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T22	17		T120	10		T121	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	902	1			T2	7		T9	10		T23	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T3	8		T8	2		T137	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T89	3		T142	1		T12	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T136	10		T121	12		T123	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T3	10		T122	13		T28	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T121	13		T143	8		T28	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T31	1		T144	10		T34	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T39	8		T137	1		T229	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T22	10		T151	7		T15	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T20	8		T22	7		T223	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T8	4		T32	4		T233	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	11		T120	9		T223	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T230	7		T235	2		T231	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T128	4		T186	9		T34	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T120	6		T207	10		T122	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T7	10		T11	3		T221	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T224	12		T228	10		T280	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T8	21		T122	8		T33	21
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T8	1		T58	1		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T5	13		T142	1		T230	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T224	12		T127	11		T228	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T11	4		T227	1		T122	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T339	9		T232	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T132	1		T222	3		T326	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T8	1		T10	1		T36	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T5	14		T120	1		T121	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1496	1			T2	1		T4	1		T6	39
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T1	17		T3	12		T8	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T20	4		T89	1		T207	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T1	8		T121	12		T32	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T7	1		T12	8		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T136	10		T138	1		T123	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T3	10		T127	10		T31	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T36	11		T121	9		T39	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T5	1		T26	1		T47	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T20	9		T22	6		T223	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T7	1		T8	4		T22	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	12		T90	1		T120	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T137	6		T124	2		T233	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T10	1		T128	4		T186	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T1	1		T227	1		T120	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T7	1		T8	6		T36	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16899	1			T8	296		T25	107		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T224	12		T228	10		T277	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T11	3		T122	8		T33	21
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T339	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T8	2		T152	10		T258	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T5	13		T120	10		T121	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	942	1			T2	7		T9	10		T23	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T3	8		T8	2		T22	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T89	3		T142	1		T226	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T121	12		T32	7		T143	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T12	8		T122	13		T252	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T136	10		T123	8		T32	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T3	10		T31	1		T144	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T121	13		T39	8		T137	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T151	7		T34	1		T15	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T20	8		T22	7		T223	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T8	4		T22	10		T32	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T5	11		T120	9		T223	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T233	6		T235	2		T231	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T128	4		T186	9		T144	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T120	6		T207	10		T122	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T7	10		T8	21		T221	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	1		T58	1		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T8	3		T10	1		T36	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T1	1		T22	18		T120	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1225	1			T2	8		T4	1		T6	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T3	9		T8	3		T137	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T89	4		T142	2		T12	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T1	1		T136	11		T121	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	11		T7	1		T122	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T121	14		T143	9		T134	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T26	1		T127	1		T31	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T36	1		T39	9		T137	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	1		T22	11		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T20	9		T22	8		T223	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T7	1		T8	7		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T5	12		T90	1		T120	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T124	1		T221	1		T226	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T10	1		T128	5		T186	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T1	1		T227	1		T120	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T7	11		T11	5		T227	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T224	13		T228	11		T280	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T8	24		T122	9		T33	27
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17084	1			T8	297		T25	107		T37	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T5	14		T142	2		T230	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T36	14		T152	5		T177	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T1	16		T22	13		T121	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1208	1			T6	36		T20	3		T21	40
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	11		T8	14		T137	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T12	3		T152	10		T149	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T1	7		T136	9		T121	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T3	9		T236	12		T275	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T121	8		T143	5		T278	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T127	9		T144	9		T34	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T36	10		T39	10		T229	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T22	14		T47	4		T15	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T20	8		T22	5		T223	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T8	1		T137	5		T185	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T5	11		T223	13		T209	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T145	11		T238	2		T230	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T128	3		T186	15		T270	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T127	10		T240	7		T35	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T11	2		T36	7		T241	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T224	11		T228	12		T280	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T8	3		T33	4		T187	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T272	5		T340	2		T339	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T5	13		T230	10		T305	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T224	13		T127	1		T228	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T11	5		T227	1		T122	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T339	10		T232	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T132	1		T222	1		T326	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T8	3		T10	1		T36	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T5	14		T120	11		T121	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T2	8		T4	1		T6	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T1	1		T3	9		T8	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T20	1		T89	4		T207	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	1		T121	13		T32	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T7	1		T12	13		T122	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T136	11		T138	1		T123	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T3	11		T127	1		T31	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T36	1		T121	14		T39	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	1		T26	1		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T20	9		T22	8		T223	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T7	1		T8	7		T22	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	12		T90	1		T120	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T137	1		T124	2		T233	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T10	1		T128	5		T186	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T1	1		T227	1		T120	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T7	11		T8	24		T36	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17033	1			T8	297		T25	107		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T224	11		T127	10		T228	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T11	2		T33	4		T291	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T339	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T222	2		T326	6		T243	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T36	14		T152	5		T244	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	13		T121	11		T142	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1172	1			T6	36		T21	40		T245	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T1	16		T3	11		T8	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T20	3		T152	10		T246	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T1	7		T121	11		T32	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T12	3		T149	12		T163	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T136	9		T123	9		T32	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T3	9		T127	9		T144	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T36	10		T121	8		T39	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T47	4		T34	1		T15	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T20	8		T22	5		T223	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	1		T22	14		T185	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T5	11		T223	13		T127	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T137	5		T233	1		T238	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T128	3		T186	15		T144	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T240	7		T145	11		T35	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T8	3		T36	7		T241	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

auto[0]

4036

1

T1

23

T3

20

T5

24