Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26057

1

T1

26

T2

8

T3

40

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22873

1

T1

18

T2

8

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3184

1

T1

8

T3

20

T5

24

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19986

1

T1

18

T3

40

T5

23

auto[1]

6071

1

T1

8

T2

8

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22024

1

T1

26

T2

1

T3

22

auto[1]

4033

1

T2

7

T3

18

T5

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	728	1			T1	1		T5	27		T8	7
values[0]	33	1			T164	3		T344	1		T275	11
values[1]	820	1			T7	1		T227	1		T120	7
values[2]	2889	1			T2	8		T3	20		T4	1
values[3]	909	1			T10	1		T22	13		T26	1
values[4]	560	1			T7	12		T36	15		T137	18
values[5]	707	1			T3	20		T22	31		T36	8
values[6]	676	1			T1	8		T5	24		T8	3
values[7]	660	1			T1	17		T8	27		T89	4
values[8]	492	1			T20	4		T90	1		T227	1
values[9]	1019	1			T8	25		T10	1		T22	25
minimum	16564	1			T8	290		T25	100		T37	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	723	1			T7	1		T20	17		T120	7
values[1]	2888	1			T2	8		T3	20		T4	1
values[2]	836	1			T10	1		T22	13		T142	2
values[3]	590	1			T7	12		T36	23		T161	1
values[4]	694	1			T3	20		T22	31		T121	24
values[5]	726	1			T1	8		T5	24		T8	3
values[6]	606	1			T1	17		T136	20		T247	1
values[7]	544	1			T8	44		T20	4		T90	1
values[8]	981	1			T1	1		T5	27		T8	8
values[9]	125	1			T207	11		T39	19		T185	12
minimum	17344	1			T8	297		T25	107		T37	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

4036

1

T1

23

T3

20

T5

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T7	1		T20	9		T161	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T120	1		T127	11		T123	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1604	1			T2	1		T3	10		T4	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T26	1		T207	1		T58	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T10	1		T22	6		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T142	1		T12	8		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T7	1		T36	8		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T7	1		T36	15		T223	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T22	14		T121	12		T123	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T3	12		T30	2		T122	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T8	1		T89	1		T11	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T1	8		T5	13		T142	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	17		T136	10		T144	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T247	1		T147	1		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T8	15		T121	12		T241	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T8	6		T20	4		T90	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T1	1		T5	14		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T8	4		T121	9		T224	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T207	1		T152	11		T261	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T39	11		T185	12		T171	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16968	1			T8	296		T25	107		T37	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T227	1		T36	11		T228	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T20	8		T223	14		T31	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T120	6		T123	2		T270	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	969	1			T2	7		T3	10		T9	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T234	11		T34	10		T35	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T22	7		T151	7		T32	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T142	1		T12	8		T122	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T137	12		T128	4		T186	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T7	10		T223	6		T198	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T22	17		T121	12		T123	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	8		T122	8		T254	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T8	2		T89	3		T11	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T5	11		T142	7		T225	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T136	10		T144	10		T221	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T28	7		T270	12		T253	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T8	2		T121	12		T234	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T8	21		T120	9		T223	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T5	13		T22	10		T209	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T8	4		T121	13		T224	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T207	10		T152	8		T261	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T39	8		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T8	1		T58	1		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T228	10		T345	9		T255	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	523	1			T1	1		T5	14		T8	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T39	11		T144	8		T221	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T164	1		T344	1		T275	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T303	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T7	1		T161	1		T137	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T227	1		T120	1		T36	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1587	1			T2	1		T3	10		T4	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T207	1		T58	1		T127	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T10	1		T22	6		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T26	1		T142	1		T12	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T7	1		T137	6		T128	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T7	1		T36	15		T223	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T22	14		T36	8		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T3	12		T30	2		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T8	1		T11	4		T121	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T1	8		T5	13		T142	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T1	17		T89	1		T47	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T8	6		T247	1		T254	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T136	10		T241	5		T234	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T20	4		T90	1		T227	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T8	15		T10	1		T22	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T8	4		T120	1		T121	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16430	1			T8	289		T25	100		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T5	13		T152	8		T261	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T39	8		T144	9		T233	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T164	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T303	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T223	14		T31	1		T229	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T120	6		T123	2		T228	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	960	1			T2	7		T3	10		T9	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T234	11		T34	10		T35	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T22	7		T151	7		T32	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T142	1		T12	8		T122	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T137	12		T128	4		T229	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T7	10		T223	6		T192	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T22	17		T186	9		T152	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	8		T254	13		T235	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T8	2		T11	3		T121	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T5	11		T142	7		T122	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T89	3		T144	10		T221	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T8	21		T254	10		T270	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T136	10		T234	12		T237	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T223	3		T125	6		T28	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T8	2		T22	10		T121	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T8	4		T120	9		T121	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	1		T58	1		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	1		T20	9		T161	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T120	7		T127	1		T123	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1298	1			T2	8		T3	11		T4	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T26	1		T207	1		T58	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T10	1		T22	8		T151	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T142	2		T12	13		T122	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T7	1		T36	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T7	11		T36	1		T223	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T22	18		T121	13		T123	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T3	9		T30	2		T122	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T8	3		T89	4		T11	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	1		T5	13		T142	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T1	1		T136	11		T144	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T247	1		T147	1		T28	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T8	3		T121	13		T241	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T8	24		T20	1		T90	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T1	1		T5	14		T10	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T8	7		T121	14		T224	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T207	11		T152	9		T261	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T39	9		T185	1		T171	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17131	1			T8	297		T25	107		T37	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T227	1		T36	1		T228	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T20	8		T137	5		T223	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T127	10		T123	12		T270	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T3	9		T6	36		T21	40
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T35	5		T346	13		T306	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T22	5		T32	6		T230	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T12	3		T240	7		T133	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T36	7		T137	5		T128	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T36	14		T223	11		T269	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T22	13		T121	11		T123	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T3	11		T271	6		T217	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T11	2		T47	4		T127	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T1	7		T5	11		T142	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	16		T136	9		T144	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T149	14		T270	11		T253	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T8	14		T121	11		T241	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T8	3		T20	3		T127	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T5	13		T22	14		T209	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T8	1		T121	8		T224	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T152	10		T261	1		T281	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T39	10		T185	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T154	11		T338	8		T275	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T36	10		T228	12		T345	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	549	1			T1	1		T5	14		T8	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T39	9		T144	10		T221	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T164	3		T344	1		T275	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T303	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T7	1		T161	1		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T227	1		T120	7		T36	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T2	8		T3	11		T4	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T207	1		T58	1		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	314	1			T10	1		T22	8		T151	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T26	1		T142	2		T12	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	1		T137	13		T128	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	11		T36	1		T223	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T22	18		T36	1		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T3	9		T30	2		T198	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T8	3		T11	5		T121	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T1	1		T5	13		T142	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	1		T89	4		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T8	24		T247	1		T254	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T136	11		T241	1		T234	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T20	1		T90	1		T227	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T8	3		T10	1		T22	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T8	7		T120	10		T121	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16564	1			T8	290		T25	100		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T5	13		T152	10		T261	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T39	10		T144	7		T233	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T275	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T303	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T137	5		T223	13		T233	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T36	10		T123	12		T228	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1262	1			T3	9		T6	36		T20	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T127	10		T35	5		T270	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T22	5		T32	6		T230	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T12	3		T240	7		T133	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T137	5		T128	3		T229	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T36	14		T223	11		T154	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T22	13		T36	7		T186	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T3	11		T271	6		T269	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T11	2		T121	11		T123	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T1	7		T5	11		T142	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	16		T47	4		T127	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T8	3		T270	11		T253	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T136	9		T241	4		T291	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T20	3		T149	14		T258	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T8	14		T22	14		T121	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T8	1		T121	8		T224	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

auto[0]

4036

1

T1

23

T3

20

T5

24