Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26057

1

T1

26

T2

8

T3

40

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22879

1

T1

26

T2

8

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3178

1

T3

20

T7

11

T20

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19969

1

T1

1

T3

40

T5

28

auto[1]

6088

1

T1

25

T2

8

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22024

1

T1

26

T2

1

T3

22

auto[1]

4033

1

T2

7

T3

18

T5

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	218	1			T22	13		T221	1		T254	14
values[0]	47	1			T39	19		T347	1		T267	26
values[1]	809	1			T5	23		T22	25		T58	1
values[2]	700	1			T1	18		T26	1		T89	4
values[3]	632	1			T5	1		T10	1		T22	31
values[4]	2932	1			T2	8		T4	1		T6	39
values[5]	671	1			T36	11		T137	6		T127	21
values[6]	690	1			T3	20		T20	4		T11	7
values[7]	629	1			T1	8		T8	8		T10	1
values[8]	812	1			T5	27		T7	2		T8	3
values[9]	884	1			T3	20		T8	17		T90	1
minimum	17033	1			T8	297		T25	107		T37	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	807	1			T1	1		T22	25		T26	1
values[1]	778	1			T1	17		T89	4		T120	7
values[2]	568	1			T5	1		T10	1		T22	31
values[3]	2816	1			T2	8		T4	1		T6	39
values[4]	752	1			T11	7		T36	11		T137	6
values[5]	717	1			T3	20		T8	8		T20	4
values[6]	650	1			T1	8		T7	1		T10	1
values[7]	734	1			T5	27		T7	1		T8	3
values[8]	813	1			T3	20		T8	17		T22	13
values[9]	150	1			T161	1		T155	5		T312	17
minimum	17272	1			T5	23		T8	297		T25	107

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

4036

1

T1

23

T3

20

T5

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	1		T223	1		T12	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T22	15		T26	1		T47	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T1	17		T120	1		T224	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T89	1		T142	1		T122	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T5	1		T10	1		T22	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T142	1		T225	1		T33	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1560	1			T2	1		T4	1		T6	39
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T7	1		T137	1		T13	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T128	4		T151	1		T225	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	4		T36	11		T137	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T8	4		T185	12		T186	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	12		T20	4		T121	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	8		T7	1		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T223	12		T124	1		T144	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T5	14		T7	1		T8	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T120	1		T36	8		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T3	10		T8	15		T121	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T22	6		T90	1		T227	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T161	1		T312	10		T316	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T155	3		T301	3		T348	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16968	1			T5	12		T8	296		T25	107
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T58	1		T30	2		T28	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T223	3		T12	8		T123	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T22	10		T144	10		T234	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T120	6		T224	12		T122	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T89	3		T142	1		T122	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T22	17		T120	10		T209	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T142	1		T33	21		T288	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	937	1			T2	7		T8	21		T9	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T7	10		T137	1		T13	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T128	4		T151	7		T225	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T11	3		T228	10		T257	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T8	4		T186	9		T229	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	8		T121	13		T142	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T230	7		T152	10		T235	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T223	6		T144	9		T253	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T5	13		T8	2		T234	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T120	9		T233	17		T231	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T3	10		T8	2		T121	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T22	7		T207	10		T192	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T312	7		T316	15		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T155	2		T301	2		T348	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	11		T8	1		T58	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T28	18		T278	14		T273	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T221	1		T254	1		T261	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T22	6		T29	1		T200	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T39	11		T347	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T267	14		T349	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T5	12		T223	1		T12	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T22	15		T58	1		T30	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T1	18		T120	1		T122	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T26	1		T89	1		T47	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	1		T10	1		T22	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T122	2		T225	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1626	1			T2	1		T4	1		T6	39
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T7	1		T142	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T127	11		T128	4		T125	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T36	11		T137	6		T127	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T185	12		T151	1		T186	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T3	12		T20	4		T11	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	8		T8	4		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T223	26		T124	1		T144	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T5	14		T7	2		T8	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T36	8		T130	1		T233	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T3	10		T8	15		T227	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T90	1		T227	1		T120	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16899	1			T8	296		T25	107		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T254	13		T66	8		T187	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T22	7		T29	6		T301	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T39	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T267	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	11		T223	3		T12	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T22	10		T144	10		T234	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T120	6		T122	4		T217	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T89	3		T142	1		T254	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T22	17		T224	12		T209	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T122	21		T33	21		T288	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	972	1			T2	7		T8	21		T9	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	10		T142	1		T137	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T128	4		T125	6		T225	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	3		T228	10		T34	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T151	7		T186	9		T229	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T3	8		T11	3		T121	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T8	4		T229	6		T221	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T223	20		T144	9		T253	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	13		T8	2		T152	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T233	17		T258	8		T286	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T3	10		T8	2		T121	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T120	9		T207	10		T192	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	1		T58	1		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	1		T223	4		T12	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T22	11		T26	1		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T1	1		T120	7		T224	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T89	4		T142	2		T122	23
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	1		T10	1		T22	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T142	2		T225	1		T33	27
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1258	1			T2	8		T4	1		T6	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	11		T137	2		T13	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T128	5		T151	8		T225	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T11	5		T36	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T8	7		T185	1		T186	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	9		T20	1		T121	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	1		T7	1		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T223	7		T124	1		T144	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T5	14		T7	1		T8	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T120	10		T36	1		T130	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T3	11		T8	3		T121	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T22	8		T90	1		T227	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T161	1		T312	8		T316	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T155	3		T301	3		T348	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17097	1			T5	12		T8	297		T25	107
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T58	1		T30	2		T28	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T12	3		T123	9		T145	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T22	14		T47	4		T144	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T1	16		T224	11		T271	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T163	10		T17	1		T201	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T22	13		T209	2		T123	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T33	4		T269	12		T288	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1239	1			T6	36		T8	3		T20	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T143	13		T34	1		T35	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T128	3		T146	6		T15	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	2		T36	10		T137	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T8	1		T185	11		T186	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T3	11		T20	3		T121	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T1	7		T36	14		T230	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T223	11		T144	7		T253	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T5	13		T146	14		T134	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T36	7		T233	10		T291	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	9		T8	14		T121	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T22	5		T32	6		T235	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T312	9		T316	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T155	2		T301	2		T348	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T5	11		T39	10		T233	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T278	11		T273	1		T263	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T221	1		T254	14		T261	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T22	8		T29	7		T200	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T39	9		T347	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T267	13		T349	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T5	12		T223	4		T12	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T22	11		T58	1		T30	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	2		T120	7		T122	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T26	1		T89	4		T47	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	1		T10	1		T22	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T122	23		T225	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T2	8		T4	1		T6	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	11		T142	2		T137	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T127	1		T128	5		T125	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T36	1		T137	1		T127	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T185	1		T151	8		T186	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	9		T20	1		T11	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	1		T8	7		T10	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T223	22		T124	1		T144	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	14		T7	2		T8	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T36	1		T130	1		T233	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T3	11		T8	3		T227	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T90	1		T227	1		T120	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17033	1			T8	297		T25	107		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T261	2		T66	8		T187	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T22	5		T200	17		T301	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T39	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T267	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	11		T12	3		T123	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T22	14		T144	9		T35	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T1	16		T271	6		T145	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T47	4		T163	10		T286	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T22	13		T224	11		T209	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T33	4		T288	9		T149	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1298	1			T6	36		T8	3		T20	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T143	13		T35	2		T230	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T127	10		T128	3		T152	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T36	10		T137	5		T127	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T185	11		T186	15		T240	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T3	11		T20	3		T11	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T1	7		T8	1		T229	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T223	24		T144	7		T253	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	13		T36	14		T146	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T36	7		T233	10		T291	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T3	9		T8	14		T121	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T32	6		T235	2		T305	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

auto[0]

4036

1

T1

23

T3

20

T5

24