Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T89	4		T137	13		T223	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T22	18		T36	1		T127	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	9		T20	1		T22	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T7	1		T10	1		T22	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	14		T8	24		T20	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T39	9		T122	14		T123	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1253	1			T2	8		T4	1		T5	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T120	10		T121	13		T248	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T90	1		T36	1		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T227	1		T120	7		T13	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T227	1		T223	7		T234	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T1	1		T5	12		T8	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T10	1		T137	1		T124	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T7	1		T36	1		T207	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T8	3		T26	1		T223	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T1	1		T8	7		T249	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	11		T142	2		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T1	1		T7	11		T120	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T121	13		T247	1		T130	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T250	8		T236	4		T251	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17033	1			T8	297		T25	107		T37	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T47	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T137	5		T128	3		T235	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T22	13		T36	10		T127	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	11		T20	3		T22	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T22	5		T11	2		T127	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T5	13		T8	3		T20	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T39	10		T123	9		T233	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1255	1			T6	36		T21	40		T245	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T121	11		T221	12		T145	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T36	14		T12	3		T146	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T33	4		T149	12		T239	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T223	11		T233	10		T35	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	7		T5	11		T8	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T137	5		T146	14		T177	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T36	7		T229	5		T144	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T223	13		T32	6		T238	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T8	1		T144	7		T152	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	9		T15	2		T133	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T1	16		T224	11		T123	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T121	11		T253	6		T259	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T250	2		T236	3		T260	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T47	4		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T234	13		T226	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T198	16		T164	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T36	1		T255	10		T166	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T89	4		T137	13		T223	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T22	18		T47	1		T127	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	9		T20	1		T22	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T22	8		T11	5		T58	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T5	14		T8	24		T20	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T7	1		T10	1		T39	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T5	1		T127	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T120	10		T121	13		T221	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T2	8		T4	1		T6	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T227	1		T13	2		T33	27
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T90	1		T227	1		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T1	1		T5	12		T8	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T10	1		T234	12		T256	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T7	1		T36	1		T121	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T8	3		T26	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T1	1		T249	1		T144	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T3	11		T121	13		T142	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T1	1		T7	11		T8	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17033	1			T8	297		T25	107		T37	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T36	10		T255	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T137	5		T128	3		T235	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T22	13		T47	4		T127	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T3	11		T20	3		T22	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T22	5		T11	2		T123	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T5	13		T8	3		T20	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T39	10		T233	1		T228	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T127	9		T257	1		T230	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T121	11		T145	11		T230	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1257	1			T6	36		T21	40		T245	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T33	4		T221	12		T233	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T36	14		T223	11		T233	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T1	7		T5	11		T8	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T253	8		T258	15		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T36	7		T121	8		T185	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T137	5		T223	13		T32	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T1	16		T144	9		T152	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T3	9		T121	11		T15	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T8	1		T224	11		T123	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

auto[0]

4036

1

T1

23

T3

20

T5

24