Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26057

1

T1

26

T2

8

T3

40

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22556

1

T1

9

T2

8

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3501

1

T1

17

T3

40

T5

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20054

1

T1

18

T5

1

T7

12

auto[1]

6003

1

T1

8

T2

8

T3

40

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22024

1

T1

26

T2

1

T3

22

auto[1]

4033

1

T2

7

T3

18

T5

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	23	1			T121	22		T198	1		-	-
values[0]	25	1			T261	7		T18	5		T262	4
values[1]	768	1			T3	20		T22	31		T227	1
values[2]	560	1			T7	11		T227	1		T127	17
values[3]	731	1			T1	1		T3	20		T7	2
values[4]	515	1			T1	8		T5	27		T120	11
values[5]	884	1			T22	13		T120	10		T36	11
values[6]	737	1			T5	23		T8	25		T10	1
values[7]	797	1			T1	17		T8	3		T20	17
values[8]	577	1			T5	1		T10	1		T36	15
values[9]	3407	1			T2	8		T4	1		T6	39
minimum	17033	1			T8	297		T25	107		T37	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	962	1			T3	20		T22	31		T227	1
values[1]	492	1			T1	1		T7	11		T227	1
values[2]	820	1			T1	8		T3	20		T5	27
values[3]	596	1			T22	13		T120	11		T47	5
values[4]	837	1			T5	23		T8	8		T120	10
values[5]	619	1			T8	17		T10	1		T11	7
values[6]	2954	1			T1	17		T2	8		T4	1
values[7]	710	1			T5	1		T10	1		T36	15
values[8]	871	1			T20	4		T22	25		T89	4
values[9]	156	1			T26	1		T121	22		T161	1
minimum	17040	1			T8	297		T25	107		T37	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

4036

1

T1

23

T3

20

T5

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T142	11		T31	3		T151	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T3	10		T22	14		T227	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T1	1		T247	1		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T7	1		T227	1		T249	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T1	8		T5	14		T7	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	12		T7	1		T8	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T120	1		T121	12		T12	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T22	6		T47	5		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T8	4		T36	19		T137	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T5	12		T120	1		T207	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T10	1		T120	1		T142	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T8	15		T11	4		T121	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1656	1			T2	1		T4	1		T6	39
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T1	17		T122	1		T192	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	1		T36	15		T186	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T10	1		T223	1		T198	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T20	4		T22	15		T224	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T89	1		T136	10		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T121	9		T198	1		T263	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T26	1		T161	1		T32	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16900	1			T8	296		T25	107		T37	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T264	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T142	7		T31	1		T151	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T3	10		T22	17		T143	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T221	13		T235	10		T28	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T7	10		T234	11		T257	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	13		T39	8		T123	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	8		T8	21		T123	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T120	10		T121	12		T12	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T22	7		T223	14		T13	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T8	4		T229	6		T28	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T5	11		T120	9		T207	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T120	6		T142	2		T128	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T8	2		T11	3		T121	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	963	1			T2	7		T8	2		T9	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T122	13		T192	10		T233	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T186	9		T32	4		T253	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T223	3		T198	15		T144	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T22	10		T224	12		T229	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T89	3		T136	10		T225	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T121	13		T263	4		T265	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T32	7		T266	13		T267	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	1		T58	1		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T264	5		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T121	9		T198	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T261	4		T18	4		T262	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T264	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T142	11		T151	1		T34	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	10		T22	14		T227	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T247	1		T31	3		T125	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T7	1		T227	1		T127	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	1		T7	1		T90	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T3	12		T7	1		T8	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T1	8		T5	14		T120	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T47	5		T161	1		T30	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T36	11		T58	1		T137	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T22	6		T120	1		T207	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T8	4		T10	1		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T5	12		T8	15		T121	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T8	1		T20	9		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T1	17		T11	4		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T5	1		T36	15		T241	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T10	1		T223	1		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1700	1			T2	1		T4	1		T6	39
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T26	1		T89	1		T136	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16899	1			T8	296		T25	107		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T121	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T261	3		T18	1		T262	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T264	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T142	7		T151	7		T34	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T3	10		T22	17		T144	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T31	1		T125	6		T221	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T7	10		T143	8		T257	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T39	8		T123	8		T32	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	8		T8	21		T123	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T5	13		T120	10		T121	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T13	3		T34	1		T35	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T229	6		T28	12		T237	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T22	7		T120	9		T207	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T8	4		T120	6		T142	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T5	11		T8	2		T121	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T8	2		T20	8		T142	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T11	3		T137	1		T233	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T32	4		T230	10		T268	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T223	3		T122	13		T192	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1033	1			T2	7		T9	10		T22	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T89	3		T136	10		T225	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	1		T58	1		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T142	8		T31	4		T151	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T3	11		T22	18		T227	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T1	1		T247	1		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T7	11		T227	1		T249	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T1	1		T5	14		T7	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	9		T7	1		T8	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T120	11		T121	13		T12	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T22	8		T47	1		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T8	7		T36	2		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T5	12		T120	10		T207	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T10	1		T120	7		T142	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T8	3		T11	5		T121	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T2	8		T4	1		T6	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T1	1		T122	14		T192	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T5	1		T36	1		T186	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T10	1		T223	4		T198	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T20	1		T22	11		T224	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T89	4		T136	11		T124	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T121	14		T198	1		T263	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T26	1		T161	1		T32	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17034	1			T8	297		T25	107		T37	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T264	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T142	10		T35	1		T230	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T3	9		T22	13		T127	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T221	12		T269	12		T270	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T145	11		T257	1		T239	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	7		T5	13		T39	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	11		T8	3		T123	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T121	11		T12	3		T271	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T22	5		T47	4		T223	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T8	1		T36	17		T137	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T5	11		T137	5		T223	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T128	3		T143	13		T152	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T8	14		T11	2		T121	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1316	1			T6	36		T20	8		T21	40
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T1	16		T233	9		T16	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T36	14		T186	15		T32	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T144	7		T233	11		T235	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T20	3		T22	14		T224	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T136	9		T15	2		T272	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T121	8		T263	3		T265	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T32	4		T266	15		T267	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T121	14		T198	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T261	6		T18	5		T262	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T264	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T142	8		T151	8		T34	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T3	11		T22	18		T227	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T247	1		T31	4		T125	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T7	11		T227	1		T127	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T1	1		T7	1		T90	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	9		T7	1		T8	24
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T1	1		T5	14		T120	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T47	1		T161	1		T30	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T36	1		T58	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T22	8		T120	10		T207	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T8	7		T10	1		T120	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T5	12		T8	3		T121	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T8	3		T20	9		T142	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T1	1		T11	5		T137	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T5	1		T36	1		T241	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T10	1		T223	4		T122	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T2	8		T4	1		T6	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	413	1			T26	1		T89	4		T136	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17033	1			T8	297		T25	107		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T121	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T261	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T142	10		T35	1		T253	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	9		T22	13		T144	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T221	12		T230	11		T269	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T127	15		T143	5		T257	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T39	10		T123	9		T32	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	11		T8	3		T123	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T1	7		T5	13		T121	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T47	4		T34	1		T35	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T36	10		T137	5		T229	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T22	5		T137	5		T223	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T8	1		T36	7		T128	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T5	11		T8	14		T121	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T20	8		T33	4		T152	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T1	16		T11	2		T233	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T36	14		T241	4		T32	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T144	7		T235	2		T217	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1353	1			T6	36		T20	3		T21	40
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T136	9		T32	4		T233	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

auto[0]

4036

1

T1

23

T3

20

T5

24