Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26057

1

T1

26

T2

8

T3

40

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22466

1

T1

1

T2

8

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3591

1

T1

25

T3

40

T5

51

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20274

1

T1

26

T3

40

T5

24

auto[1]

5783

1

T2

8

T4

1

T5

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22024

1

T1

26

T2

1

T3

22

auto[1]

4033

1

T2

7

T3

18

T5

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	261	1			T20	17		T58	1		T127	6
values[0]	1	1			T273	1		-	-		-	-
values[1]	881	1			T1	25		T8	8		T90	1
values[2]	754	1			T3	40		T5	27		T7	12
values[3]	680	1			T120	18		T130	1		T132	1
values[4]	751	1			T8	44		T20	4		T120	10
values[5]	850	1			T1	1		T89	4		T207	11
values[6]	741	1			T5	1		T36	11		T137	2
values[7]	732	1			T10	1		T161	1		T39	19
values[8]	2659	1			T2	8		T4	1		T6	39
values[9]	714	1			T5	23		T10	1		T22	13
minimum	17033	1			T8	297		T25	107		T37	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	804	1			T1	8		T3	20		T7	1
values[1]	661	1			T3	20		T5	27		T7	11
values[2]	702	1			T120	18		T224	24		T223	18
values[3]	728	1			T1	1		T8	44		T20	4
values[4]	873	1			T36	11		T142	2		T137	2
values[5]	704	1			T5	1		T223	4		T247	1
values[6]	2954	1			T2	8		T4	1		T6	39
values[7]	427	1			T10	1		T136	20		T30	2
values[8]	747	1			T5	23		T10	1		T20	17
values[9]	90	1			T127	11		T124	1		T241	5
minimum	17367	1			T1	17		T8	297		T25	107

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

4036

1

T1

23

T3

20

T5

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T22	15		T186	16		T230	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T1	8		T3	12		T7	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T122	1		T198	1		T256	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T3	10		T5	14		T7	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T120	1		T224	12		T223	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T120	1		T130	1		T144	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	1		T8	6		T20	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T8	15		T120	1		T207	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T12	8		T130	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T36	11		T142	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T247	1		T124	1		T274	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T5	1		T223	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1630	1			T2	1		T4	1		T6	39
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T161	2		T39	11		T137	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T30	2		T125	1		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T10	1		T136	10		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T20	9		T121	9		T127	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T5	12		T10	1		T22	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T34	2		T231	1		T275	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T127	11		T124	1		T241	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16998	1			T8	296		T25	107		T37	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T1	17		T227	1		T35	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T22	10		T186	9		T230	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	8		T8	4		T11	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T122	4		T198	15		T28	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	10		T5	13		T7	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T120	10		T224	12		T223	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T120	6		T144	10		T258	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T8	21		T89	3		T128	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T8	2		T120	9		T207	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T12	8		T240	7		T221	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T142	1		T137	1		T223	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T253	10		T276	8		T277	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T223	3		T261	3		T278	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	923	1			T2	7		T9	10		T23	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T39	8		T122	13		T151	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T125	6		T32	7		T35	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T136	10		T230	10		T279	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T20	8		T121	13		T229	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T5	11		T22	7		T142	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T34	1		T231	6		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T237	2		T280	10		T281	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T8	1		T58	1		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T35	1		T133	15		T201	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T20	9		T127	6		T34	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T58	1		T124	1		T241	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T273	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T36	15		T186	16		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	25		T8	4		T90	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T22	15		T122	1		T198	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T3	22		T5	14		T7	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T120	1		T132	1		T143	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T120	1		T130	1		T144	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T8	6		T20	4		T224	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T8	15		T120	1		T137	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	1		T89	1		T12	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T207	1		T142	1		T209	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T247	1		T124	1		T252	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T5	1		T36	11		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T123	23		T134	1		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	1		T161	1		T39	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1524	1			T2	1		T4	1		T6	39
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T161	1		T138	1		T234	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T121	9		T30	2		T229	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T5	12		T10	1		T22	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16899	1			T8	296		T25	107		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T20	8		T34	1		T230	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T229	10		T237	2		T252	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T186	9		T282	6		T239	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T8	4		T11	3		T121	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T22	10		T122	4		T198	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T3	18		T5	13		T7	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T120	10		T143	8		T257	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T120	6		T144	10		T234	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T8	21		T224	12		T223	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T8	2		T120	9		T137	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T89	3		T12	8		T240	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T207	10		T142	1		T209	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T252	10		T253	10		T276	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T137	1		T223	17		T233	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T123	10		T28	12		T187	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T39	8		T122	13		T151	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	887	1			T2	7		T9	10		T23	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T35	3		T230	10		T254	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T121	13		T229	6		T32	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T5	11		T22	7		T136	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	1		T58	1		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T22	11		T186	10		T230	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T1	1		T3	9		T7	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T122	5		T198	16		T256	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T3	11		T5	14		T7	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T120	11		T224	13		T223	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T120	7		T130	1		T144	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	1		T8	24		T20	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T8	3		T120	10		T207	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	13		T130	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T36	1		T142	2		T137	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T247	1		T124	1		T274	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T5	1		T223	4		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1258	1			T2	8		T4	1		T6	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T161	2		T39	9		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T30	2		T125	7		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T10	1		T136	11		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T20	9		T121	14		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	12		T10	1		T22	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T34	2		T231	7		T275	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T127	1		T124	1		T241	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17128	1			T8	297		T25	107		T37	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T1	1		T227	1		T35	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T22	14		T186	15		T230	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T1	7		T3	11		T8	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T261	2		T283	12		T284	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T3	9		T5	13		T22	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T224	11		T223	11		T143	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T144	9		T269	12		T258	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T8	3		T20	3		T127	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T8	14		T137	5		T285	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T12	3		T240	7		T221	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T36	10		T223	13		T209	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T149	14		T253	8		T286	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T261	1		T278	11		T258	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T6	36		T21	40		T36	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T39	10		T137	5		T185	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T32	4		T35	5		T135	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T136	9		T145	11		T230	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T20	8		T121	8		T127	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T5	11		T22	5		T32	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T34	1		T275	3		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T127	10		T241	4		T237	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T36	14		T163	8		T287	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T1	16		T35	1		T133	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T20	9		T127	1		T34	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T58	1		T124	1		T241	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T273	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T36	1		T186	10		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T1	2		T8	7		T90	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T22	11		T122	5		T198	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T3	20		T5	14		T7	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T120	11		T132	1		T143	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T120	7		T130	1		T144	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T8	24		T20	1		T224	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T8	3		T120	10		T137	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T1	1		T89	4		T12	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T207	11		T142	2		T209	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T247	1		T124	1		T252	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T5	1		T36	1		T137	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T123	12		T134	1		T28	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T10	1		T161	1		T39	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1209	1			T2	8		T4	1		T6	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T161	1		T138	1		T234	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T121	14		T30	2		T229	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	12		T10	1		T22	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17033	1			T8	297		T25	107		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T20	8		T127	5		T34	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T241	4		T237	7		T280	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T36	14		T186	15		T149	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	23		T8	1		T11	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T22	14		T230	5		T16	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T3	20		T5	13		T22	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T143	5		T257	1		T288	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T144	9		T69	9		T258	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T8	3		T20	3		T224	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T8	14		T137	5		T269	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	3		T240	7		T221	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T209	2		T246	9		T180	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T253	8		T286	19		T289	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T36	10		T223	13		T233	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T123	21		T149	14		T187	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T39	10		T137	5		T185	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1202	1			T6	36		T21	40		T36	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T271	6		T145	11		T35	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T121	8		T229	5		T32	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T5	11		T22	5		T136	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

auto[0]

4036

1

T1

23

T3

20

T5

24