Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26057

1

T1

26

T2

8

T3

40

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22253

1

T1

9

T2

8

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3804

1

T1

17

T3

40

T5

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20090

1

T1

18

T5

1

T7

11

auto[1]

5967

1

T1

8

T2

8

T3

40

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22024

1

T1

26

T2

1

T3

22

auto[1]

4033

1

T2

7

T3

18

T5

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	157	1			T89	4		T161	1		T225	1
values[0]	5	1			T18	5		-	-		-	-
values[1]	809	1			T3	20		T22	31		T227	1
values[2]	600	1			T7	11		T227	1		T247	1
values[3]	780	1			T1	1		T5	27		T7	1
values[4]	515	1			T1	8		T3	20		T7	1
values[5]	848	1			T120	10		T36	11		T207	11
values[6]	694	1			T5	23		T8	25		T10	1
values[7]	638	1			T1	17		T8	3		T20	17
values[8]	792	1			T5	1		T10	1		T36	15
values[9]	3186	1			T2	8		T4	1		T6	39
minimum	17033	1			T8	297		T25	107		T37	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	685	1			T22	31		T227	1		T142	18
values[1]	510	1			T7	11		T227	1		T247	1
values[2]	793	1			T1	9		T3	20		T5	27
values[3]	565	1			T22	13		T120	11		T47	5
values[4]	976	1			T5	23		T8	8		T120	17
values[5]	532	1			T8	17		T10	1		T11	7
values[6]	2896	1			T1	17		T2	8		T4	1
values[7]	765	1			T5	1		T10	1		T36	15
values[8]	914	1			T20	4		T22	25		T26	1
values[9]	91	1			T121	22		T161	1		T198	1
minimum	17330	1			T3	20		T8	297		T25	107

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

4036

1

T1

23

T3

20

T5

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T227	1		T142	11		T35	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T22	14		T127	17		T31	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T247	1		T125	1		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T7	1		T227	1		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T1	9		T5	14		T7	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	12		T7	1		T8	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T120	1		T127	10		T12	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T22	6		T47	5		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T8	4		T120	1		T36	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T5	12		T120	1		T36	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T10	1		T142	2		T58	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	15		T11	4		T121	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1577	1			T2	1		T4	1		T6	39
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T1	17		T122	1		T192	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T5	1		T36	15		T186	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T10	1		T223	1		T198	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T20	4		T22	15		T224	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T26	1		T89	1		T136	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T121	9		T198	1		T290	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T161	1		T32	8		T266	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16958	1			T8	296		T25	107		T37	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T3	10		T248	1		T291	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T142	7		T35	1		T230	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T22	17		T31	1		T151	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T125	6		T221	13		T254	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T7	10		T234	11		T257	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T5	13		T121	12		T39	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	8		T8	21		T123	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T120	10		T12	8		T231	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T22	7		T223	14		T13	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T8	4		T120	6		T128	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T5	11		T120	9		T207	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T142	2		T122	8		T143	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T8	2		T11	3		T121	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	922	1			T2	7		T8	2		T9	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T122	13		T192	10		T233	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T186	9		T32	4		T253	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T223	3		T198	15		T33	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T22	10		T224	12		T229	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T89	3		T136	10		T225	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T121	13		T265	2		T292	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T32	7		T266	13		T293	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T8	1		T58	1		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T3	10		T254	13		T288	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T225	1		T229	1		T256	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T89	1		T161	1		T15	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T18	4		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T227	1		T142	11		T34	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T3	10		T22	14		T127	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T247	1		T125	1		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T7	1		T227	1		T31	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	1		T5	14		T90	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T7	1		T8	6		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T1	8		T7	1		T120	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T3	12		T22	6		T47	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T58	1		T137	6		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T120	1		T36	11		T207	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T8	4		T10	1		T120	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T5	12		T8	15		T121	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T8	1		T20	9		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T1	17		T11	4		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	1		T36	15		T241	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T10	1		T223	1		T122	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1657	1			T2	1		T4	1		T6	39
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T26	1		T136	10		T124	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16899	1			T8	296		T25	107		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T229	10		T294	15		T295	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T89	3		T15	2		T164	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T18	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T142	7		T34	10		T35	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T3	10		T22	17		T151	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T125	6		T221	13		T230	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T7	10		T31	1		T143	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T5	13		T121	12		T123	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T8	21		T123	2		T234	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T120	10		T39	8		T12	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T3	8		T22	7		T13	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T229	6		T28	12		T237	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T120	9		T207	10		T137	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T8	4		T120	6		T142	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T5	11		T8	2		T121	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T8	2		T20	8		T142	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T11	3		T137	1		T33	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T32	4		T230	10		T268	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T223	3		T122	13		T192	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	977	1			T2	7		T9	10		T22	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T136	10		T225	9		T32	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	1		T58	1		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T227	1		T142	8		T35	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T22	18		T127	2		T31	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T247	1		T125	7		T131	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T7	11		T227	1		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T1	2		T5	14		T7	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T3	9		T7	1		T8	24
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T120	11		T127	1		T12	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T22	8		T47	1		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T8	7		T120	7		T36	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T5	12		T120	10		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T10	1		T142	4		T58	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T8	3		T11	5		T121	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1253	1			T2	8		T4	1		T6	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T1	1		T122	14		T192	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T5	1		T36	1		T186	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T10	1		T223	4		T198	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T20	1		T22	11		T224	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T26	1		T89	4		T136	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T121	14		T198	1		T290	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T161	1		T32	11		T266	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17098	1			T8	297		T25	107		T37	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T3	11		T248	1		T291	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T142	10		T35	1		T230	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T22	13		T127	15		T143	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T221	12		T269	12		T270	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T145	11		T257	1		T239	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	7		T5	13		T121	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T3	11		T8	3		T123	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T127	9		T12	3		T271	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T22	5		T47	4		T223	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T8	1		T36	7		T137	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T5	11		T36	10		T137	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T143	13		T152	2		T274	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T8	14		T11	2		T121	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T6	36		T20	8		T21	40
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	16		T233	9		T152	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T36	14		T186	15		T32	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T33	4		T144	7		T233	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T20	3		T22	14		T224	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T136	9		T240	7		T15	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T121	8		T265	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T32	4		T266	15		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T261	1		T296	2		T286	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T3	9		T291	12		T288	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T225	1		T229	11		T256	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T89	4		T161	1		T15	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T18	5		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T227	1		T142	8		T34	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T3	11		T22	18		T127	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T247	1		T125	7		T131	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T7	11		T227	1		T31	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T1	1		T5	14		T90	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	1		T8	24		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T1	1		T7	1		T120	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	9		T22	8		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T58	1		T137	1		T130	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T120	10		T36	1		T207	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	7		T10	1		T120	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T5	12		T8	3		T121	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T8	3		T20	9		T142	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T1	1		T11	5		T137	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	1		T36	1		T241	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T10	1		T223	4		T122	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1314	1			T2	8		T4	1		T6	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T26	1		T136	11		T124	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17033	1			T8	297		T25	107		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T259	1		T297	15		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T15	2		T266	15		T298	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T142	10		T35	1		T235	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	9		T22	13		T127	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T221	12		T230	11		T269	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T143	5		T145	11		T257	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	13		T121	11		T123	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T8	3		T123	12		T238	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T1	7		T39	10		T127	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T3	11		T22	5		T47	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T137	5		T229	5		T271	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T36	10		T137	5		T223	24
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T8	1		T36	7		T128	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	11		T8	14		T121	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T20	8		T146	14		T246	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T1	16		T11	2		T33	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T36	14		T241	4		T32	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T144	7		T235	2		T217	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1320	1			T6	36		T20	3		T21	40
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T136	9		T32	4		T240	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

auto[0]

4036

1

T1

23

T3

20

T5

24