Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26057

1

T1

26

T2

8

T3

40

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22810

1

T1

18

T2

8

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3247

1

T1

8

T3

20

T5

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19864

1

T1

18

T3

20

T5

23

auto[1]

6193

1

T1

8

T2

8

T3

20

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22024

1

T1

26

T2

1

T3

22

auto[1]

4033

1

T2

7

T3

18

T5

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	491	1			T1	1		T8	7		T25	7
values[0]	45	1			T228	23		T164	3		T299	1
values[1]	798	1			T3	20		T7	1		T227	1
values[2]	2937	1			T2	8		T4	1		T6	39
values[3]	767	1			T10	1		T22	13		T26	1
values[4]	655	1			T7	12		T36	15		T137	18
values[5]	659	1			T22	31		T36	8		T161	1
values[6]	776	1			T1	8		T3	20		T5	24
values[7]	566	1			T1	17		T89	4		T47	5
values[8]	590	1			T8	27		T20	4		T90	1
values[9]	1209	1			T5	27		T8	25		T10	1
minimum	16564	1			T8	290		T25	100		T37	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	998	1			T7	1		T20	17		T227	1
values[1]	2863	1			T2	8		T3	20		T4	1
values[2]	769	1			T10	1		T22	13		T142	2
values[3]	637	1			T7	12		T36	15		T161	1
values[4]	652	1			T1	8		T3	20		T22	31
values[5]	799	1			T5	24		T8	3		T89	4
values[6]	621	1			T1	17		T136	20		T247	1
values[7]	585	1			T8	44		T20	4		T90	1
values[8]	865	1			T1	1		T5	27		T8	8
values[9]	172	1			T10	1		T207	11		T39	19
minimum	17096	1			T8	297		T25	107		T37	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

4036

1

T1

23

T3

20

T5

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T7	1		T120	1		T161	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T20	9		T227	1		T36	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1594	1			T2	1		T3	10		T4	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T26	1		T58	1		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T10	1		T22	6		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T142	1		T12	8		T122	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T7	1		T36	15		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	1		T223	12		T128	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T36	8		T121	12		T122	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T1	8		T3	12		T22	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T5	1		T89	1		T11	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	12		T8	1		T142	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T1	17		T136	10		T144	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T247	1		T221	13		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T8	6		T90	1		T227	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T8	15		T20	4		T121	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T1	1		T5	14		T22	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T8	4		T121	9		T224	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T10	1		T207	1		T39	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T35	2		T300	1		T284	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16938	1			T8	296		T25	107		T37	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T256	1		T282	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T120	6		T223	14		T31	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T20	8		T228	10		T257	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	925	1			T2	7		T3	10		T9	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T34	10		T35	8		T230	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T22	7		T151	7		T32	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T142	1		T12	8		T122	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T137	12		T198	15		T229	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T7	10		T223	6		T128	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T121	12		T122	8		T123	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	8		T22	17		T142	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T89	3		T11	3		T35	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T5	11		T8	2		T142	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T136	10		T144	10		T237	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T221	13		T28	7		T252	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T8	21		T120	9		T223	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T8	2		T121	12		T125	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	13		T22	10		T209	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T8	4		T121	13		T224	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T207	10		T39	8		T152	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T35	1		T300	10		T263	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T8	1		T58	1		T123	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	471	1			T1	1		T8	7		T25	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T284	13		T301	3		T302	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T299	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T228	13		T164	1		T303	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T3	10		T7	1		T120	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T227	1		T36	11		T256	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1600	1			T2	1		T4	1		T6	39
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T20	9		T58	1		T127	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T10	1		T22	6		T120	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T26	1		T142	1		T12	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T7	1		T36	15		T137	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T7	1		T223	12		T128	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T36	8		T161	1		T186	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T22	14		T198	1		T271	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T5	1		T11	4		T121	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T1	8		T3	12		T5	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T1	17		T89	1		T47	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T127	6		T247	1		T254	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T8	6		T90	1		T227	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T20	4		T224	12		T125	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T5	14		T10	1		T22	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T8	19		T121	21		T137	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16430	1			T8	289		T25	100		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T304	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T301	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T228	10		T164	2		T303	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	10		T120	6		T223	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T257	1		T305	1		T69	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	981	1			T2	7		T9	10		T23	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T20	8		T34	10		T35	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T22	7		T120	10		T151	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T142	1		T12	8		T122	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T137	12		T198	15		T229	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T7	10		T223	6		T128	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T186	9		T152	10		T231	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T22	17		T254	13		T235	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	3		T121	12		T122	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	8		T5	11		T8	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T89	3		T144	10		T239	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T254	10		T270	12		T253	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T8	21		T120	9		T136	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T224	12		T125	6		T28	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T5	13		T22	10		T207	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T8	6		T121	25		T137	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	1		T58	1		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	326	1			T7	1		T120	7		T161	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T20	9		T227	1		T36	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1259	1			T2	8		T3	11		T4	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T26	1		T58	1		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T10	1		T22	8		T151	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T142	2		T12	13		T122	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	1		T36	1		T161	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T7	11		T223	7		T128	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T36	1		T121	13		T122	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T1	1		T3	9		T22	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T5	1		T89	4		T11	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	12		T8	3		T142	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	1		T136	11		T144	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T247	1		T221	14		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T8	24		T90	1		T227	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T8	3		T20	1		T121	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T1	1		T5	14		T22	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T8	7		T121	14		T224	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T10	1		T207	11		T39	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T35	2		T300	11		T284	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17059	1			T8	297		T25	107		T37	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T256	1		T282	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T137	5		T223	13		T233	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T20	8		T36	10		T127	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1260	1			T3	9		T6	36		T21	40
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T35	5		T230	11		T306	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T22	5		T32	6		T135	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T12	3		T240	7		T133	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T36	14		T137	5		T229	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T223	11		T128	3		T269	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T36	7		T121	11		T123	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T1	7		T3	11		T22	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T11	2		T47	4		T35	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	11		T142	10		T127	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	16		T136	9		T144	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T221	12		T270	11		T253	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T8	3		T241	4		T291	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T8	14		T20	3		T121	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T5	13		T22	14		T209	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T8	1		T121	8		T224	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T39	10		T185	11		T152	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T35	1		T284	12		T263	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T123	12		T154	11		T307	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	472	1			T1	1		T8	7		T25	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T284	1		T301	3		T302	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T299	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T228	11		T164	3		T303	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T3	11		T7	1		T120	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T227	1		T36	1		T256	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T2	8		T4	1		T6	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T20	9		T58	1		T127	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T10	1		T22	8		T120	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T26	1		T142	2		T12	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T7	1		T36	1		T137	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T7	11		T223	7		T128	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T36	1		T161	1		T186	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T22	18		T198	1		T271	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	1		T11	5		T121	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	1		T3	9		T5	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T1	1		T89	4		T47	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T127	1		T247	1		T254	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T8	24		T90	1		T227	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T20	1		T224	13		T125	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	375	1			T5	14		T10	1		T22	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T8	10		T121	27		T137	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16564	1			T8	290		T25	100		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T284	12		T301	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T228	12		T303	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	9		T137	5		T223	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T36	10		T257	1		T300	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1263	1			T6	36		T21	40		T245	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T20	8		T127	10		T35	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T22	5		T32	3		T230	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T12	3		T240	7		T230	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T36	14		T137	5		T229	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T223	11		T128	3		T154	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T36	7		T186	15		T152	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T22	13		T271	6		T269	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	2		T121	11		T123	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T1	7		T3	11		T5	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	16		T47	4		T144	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T127	5		T270	11		T253	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T8	3		T136	9		T241	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T20	3		T224	11		T258	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T5	13		T22	14		T39	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T8	15		T121	19		T127	9

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

auto[0]

4036

1

T1

23

T3

20

T5

24