Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26057

1

T1

26

T2

8

T3

40

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22462

1

T1

1

T2

8

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3595

1

T1

25

T3

40

T5

28

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20301

1

T1

26

T3

40

T5

28

auto[1]

5756

1

T2

8

T4

1

T5

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22024

1

T1

26

T2

1

T3

22

auto[1]

4033

1

T2

7

T3

18

T5

24

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	41	1			T20	17		T203	12		T166	1
values[0]	26	1			T147	1		T273	1		T308	14
values[1]	851	1			T1	25		T8	8		T90	1
values[2]	778	1			T3	20		T5	27		T7	12
values[3]	711	1			T3	20		T120	7		T122	9
values[4]	676	1			T1	1		T8	44		T120	11
values[5]	850	1			T5	1		T20	4		T89	4
values[6]	830	1			T36	11		T161	1		T137	2
values[7]	660	1			T10	1		T39	19		T137	6
values[8]	2639	1			T2	8		T4	1		T6	39
values[9]	962	1			T5	23		T10	1		T22	13
minimum	17033	1			T8	297		T25	107		T37	13

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1119	1			T1	25		T3	20		T7	1
values[1]	657	1			T3	20		T5	27		T7	11
values[2]	750	1			T120	18		T224	24		T223	18
values[3]	728	1			T1	1		T8	44		T20	4
values[4]	801	1			T36	11		T142	2		T137	2
values[5]	717	1			T5	1		T223	4		T247	1
values[6]	2943	1			T2	8		T4	1		T6	39
values[7]	456	1			T10	1		T136	20		T121	22
values[8]	720	1			T5	23		T10	1		T20	17
values[9]	120	1			T26	1		T127	11		T124	1
minimum	17046	1			T8	297		T25	107		T37	13

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

4036

1

T1

23

T3

20

T5

24

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T36	15		T186	16		T230	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	360	1			T1	25		T3	12		T7	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T22	15		T122	1		T198	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	10		T5	14		T7	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T120	1		T224	12		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T120	1		T223	12		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	1		T8	6		T20	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T8	15		T120	1		T207	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	8		T130	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T36	11		T142	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T247	1		T124	1		T274	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T5	1		T223	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1604	1			T2	1		T4	1		T6	39
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T121	12		T161	2		T39	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T121	9		T30	2		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T10	1		T136	10		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T5	12		T20	9		T127	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T10	1		T22	6		T227	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T34	2		T237	9		T309	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T26	1		T127	11		T124	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16910	1			T8	296		T25	107		T37	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T186	9		T230	7		T16	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T3	8		T8	4		T11	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T22	10		T122	4		T198	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	10		T5	13		T7	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T120	10		T224	12		T143	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T120	6		T223	6		T144	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T8	21		T89	3		T128	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T8	2		T120	9		T207	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T12	8		T240	7		T221	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T142	1		T137	1		T223	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T253	10		T276	8		T277	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T223	3		T235	10		T261	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	933	1			T2	7		T9	10		T23	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T121	12		T39	8		T122	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T121	13		T32	7		T35	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T136	10		T151	7		T230	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T5	11		T20	8		T229	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T22	7		T142	1		T229	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T34	1		T237	2		T309	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T237	2		T281	13		T265	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T8	1		T58	1		T31	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T20	9		T310	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T203	12		T166	1		T188	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T311	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T147	1		T273	1		T308	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T36	15		T282	1		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T1	25		T8	4		T90	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T22	15		T122	1		T186	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T3	12		T5	14		T7	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T122	1		T132	1		T143	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T3	10		T120	1		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T1	1		T8	6		T120	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T8	15		T137	6		T223	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T20	4		T89	1		T12	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T5	1		T120	1		T207	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T247	1		T123	13		T124	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T36	11		T161	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T123	10		T134	1		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T10	1		T39	11		T137	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1485	1			T2	1		T4	1		T6	39
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T136	10		T121	12		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T5	12		T121	9		T127	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T10	1		T22	6		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16899	1			T8	296		T25	107		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T20	8		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T188	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T308	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T282	6		T239	9		T163	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T8	4		T11	3		T121	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T22	10		T122	4		T186	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	8		T5	13		T7	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T122	8		T143	8		T228	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T3	10		T120	6		T144	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T8	21		T120	10		T224	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T8	2		T137	12		T223	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T89	3		T12	8		T240	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T120	9		T207	10		T142	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T123	2		T221	13		T252	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T137	1		T223	17		T233	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T123	8		T28	12		T187	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T39	8		T122	13		T151	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	855	1			T2	7		T9	10		T23	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T136	10		T121	12		T192	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	11		T121	13		T229	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T22	7		T142	1		T229	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T8	1		T58	1		T31	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T36	1		T186	10		T230	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T1	2		T3	9		T7	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T22	11		T122	5		T198	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	11		T5	14		T7	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T120	11		T224	13		T132	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T120	7		T223	7		T130	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T1	1		T8	24		T20	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T8	3		T120	10		T207	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	13		T130	1		T131	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T36	1		T142	2		T137	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T247	1		T124	1		T274	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T5	1		T223	4		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T2	8		T4	1		T6	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T121	13		T161	2		T39	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T121	14		T30	2		T131	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T10	1		T136	11		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T5	12		T20	9		T127	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T10	1		T22	8		T227	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T34	2		T237	3		T309	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T26	1		T127	1		T124	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17036	1			T8	297		T25	107		T37	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T36	14		T186	15		T230	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T1	23		T3	11		T8	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T22	14		T152	2		T261	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T3	9		T5	13		T22	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T224	11		T143	5		T228	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T223	11		T144	9		T269	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T8	3		T20	3		T127	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T8	14		T137	5		T285	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T12	3		T240	7		T221	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T36	10		T223	13		T209	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T149	14		T253	8		T286	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T291	12		T235	4		T261	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T6	36		T21	40		T36	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T121	11		T39	10		T137	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T121	8		T32	4		T35	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T136	9		T145	11		T230	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	11		T20	8		T127	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T22	5		T32	3		T233	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T34	1		T237	8		T309	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T127	10		T241	4		T237	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T242	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T20	9		T310	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T203	1		T166	1		T188	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T311	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T147	1		T273	1		T308	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T36	1		T282	7		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T1	2		T8	7		T90	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T22	11		T122	5		T186	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T3	9		T5	14		T7	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T122	9		T132	1		T143	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T3	11		T120	7		T130	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	1		T8	24		T120	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T8	3		T137	13		T223	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T20	1		T89	4		T12	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T5	1		T120	10		T207	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T247	1		T123	3		T124	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T36	1		T161	1		T137	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T123	9		T134	1		T28	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T10	1		T39	9		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1172	1			T2	8		T4	1		T6	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T136	11		T121	13		T161	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T5	12		T121	14		T127	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T10	1		T22	8		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17033	1			T8	297		T25	107		T37	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T20	8		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T203	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T311	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T308	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T36	14		T149	12		T239	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T1	23		T8	1		T11	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T22	14		T186	15		T230	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	11		T5	13		T22	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T143	5		T228	12		T257	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T3	9		T144	9		T239	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	3		T224	11		T127	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T8	14		T137	5		T223	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T20	3		T12	3		T240	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T209	2		T66	17		T246	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T123	12		T221	12		T274	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T36	10		T223	13		T233	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T123	9		T149	14		T187	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T39	10		T137	5		T185	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1168	1			T6	36		T21	40		T36	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T136	9		T121	11		T271	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T5	11		T121	8		T127	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T22	5		T127	10		T241	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22021

1

T1

3

T2

8

T3

20

auto[1]

auto[0]

4036

1

T1

23

T3

20

T5

24